1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv04.h"
25 
26 #include <core/gpuobj.h>
27 #include <core/option.h>
28 #include <subdev/timer.h>
29 
30 #define NV41_GART_SIZE (512 * 1024 * 1024)
31 #define NV41_GART_PAGE (  4 * 1024)
32 
33 /*******************************************************************************
34  * VM map/unmap callbacks
35  ******************************************************************************/
36 
37 static void
38 nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
39 	       struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
40 {
41 	pte = pte * 4;
42 	nvkm_kmap(pgt);
43 	while (cnt) {
44 		u32 page = PAGE_SIZE / NV41_GART_PAGE;
45 		u64 phys = (u64)*list++;
46 		while (cnt && page--) {
47 			nvkm_wo32(pgt, pte, (phys >> 7) | 1);
48 			phys += NV41_GART_PAGE;
49 			pte += 4;
50 			cnt -= 1;
51 		}
52 	}
53 	nvkm_done(pgt);
54 }
55 
56 static void
57 nv41_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
58 {
59 	pte = pte * 4;
60 	nvkm_kmap(pgt);
61 	while (cnt--) {
62 		nvkm_wo32(pgt, pte, 0x00000000);
63 		pte += 4;
64 	}
65 	nvkm_done(pgt);
66 }
67 
68 static void
69 nv41_vm_flush(struct nvkm_vm *vm)
70 {
71 	struct nv04_mmu *mmu = nv04_mmu(vm->mmu);
72 	struct nvkm_device *device = mmu->base.subdev.device;
73 
74 	mutex_lock(&nv_subdev(mmu)->mutex);
75 	nvkm_wr32(device, 0x100810, 0x00000022);
76 	nvkm_msec(device, 2000,
77 		if (nvkm_rd32(device, 0x100810) & 0x00000020)
78 			break;
79 	);
80 	nvkm_wr32(device, 0x100810, 0x00000000);
81 	mutex_unlock(&nv_subdev(mmu)->mutex);
82 }
83 
84 /*******************************************************************************
85  * MMU subdev
86  ******************************************************************************/
87 
88 static int
89 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
90 	      struct nvkm_oclass *oclass, void *data, u32 size,
91 	      struct nvkm_object **pobject)
92 {
93 	struct nvkm_device *device = nv_device(parent);
94 	struct nv04_mmu *mmu;
95 	int ret;
96 
97 	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
98 	    !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
99 		return nvkm_object_old(parent, engine, &nv04_mmu_oclass,
100 					data, size, pobject);
101 	}
102 
103 	ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
104 			      "mmu", &mmu);
105 	*pobject = nv_object(mmu);
106 	if (ret)
107 		return ret;
108 
109 	mmu->base.create = nv04_vm_create;
110 	mmu->base.limit = NV41_GART_SIZE;
111 	mmu->base.dma_bits = 39;
112 	mmu->base.pgt_bits = 32 - 12;
113 	mmu->base.spg_shift = 12;
114 	mmu->base.lpg_shift = 12;
115 	mmu->base.map_sg = nv41_vm_map_sg;
116 	mmu->base.unmap = nv41_vm_unmap;
117 	mmu->base.flush = nv41_vm_flush;
118 
119 	ret = nvkm_vm_create(&mmu->base, 0, NV41_GART_SIZE, 0, 4096, NULL,
120 			     &mmu->vm);
121 	if (ret)
122 		return ret;
123 
124 	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
125 			      (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16, true,
126 			      &mmu->vm->pgt[0].mem[0]);
127 	mmu->vm->pgt[0].refcount[0] = 1;
128 	if (ret)
129 		return ret;
130 
131 	return 0;
132 }
133 
134 static int
135 nv41_mmu_init(struct nvkm_object *object)
136 {
137 	struct nv04_mmu *mmu = (void *)object;
138 	struct nvkm_device *device = mmu->base.subdev.device;
139 	struct nvkm_memory *dma = mmu->vm->pgt[0].mem[0];
140 	int ret;
141 
142 	ret = nvkm_mmu_init(&mmu->base);
143 	if (ret)
144 		return ret;
145 
146 	nvkm_wr32(device, 0x100800, 0x00000002 | nvkm_memory_addr(dma));
147 	nvkm_mask(device, 0x10008c, 0x00000100, 0x00000100);
148 	nvkm_wr32(device, 0x100820, 0x00000000);
149 	return 0;
150 }
151 
152 struct nvkm_oclass
153 nv41_mmu_oclass = {
154 	.handle = NV_SUBDEV(MMU, 0x41),
155 	.ofuncs = &(struct nvkm_ofuncs) {
156 		.ctor = nv41_mmu_ctor,
157 		.dtor = nv04_mmu_dtor,
158 		.init = nv41_mmu_init,
159 		.fini = _nvkm_mmu_fini,
160 	},
161 };
162