1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv04.h" 25 26 #include <core/device.h> 27 #include <core/gpuobj.h> 28 29 #define NV04_PDMA_SIZE (128 * 1024 * 1024) 30 #define NV04_PDMA_PAGE ( 4 * 1024) 31 32 /******************************************************************************* 33 * VM map/unmap callbacks 34 ******************************************************************************/ 35 36 static void 37 nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 38 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 39 { 40 pte = 0x00008 + (pte * 4); 41 while (cnt) { 42 u32 page = PAGE_SIZE / NV04_PDMA_PAGE; 43 u32 phys = (u32)*list++; 44 while (cnt && page--) { 45 nv_wo32(pgt, pte, phys | 3); 46 phys += NV04_PDMA_PAGE; 47 pte += 4; 48 cnt -= 1; 49 } 50 } 51 } 52 53 static void 54 nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) 55 { 56 pte = 0x00008 + (pte * 4); 57 while (cnt--) { 58 nv_wo32(pgt, pte, 0x00000000); 59 pte += 4; 60 } 61 } 62 63 static void 64 nv04_vm_flush(struct nvkm_vm *vm) 65 { 66 } 67 68 /******************************************************************************* 69 * VM object 70 ******************************************************************************/ 71 72 int 73 nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart, 74 struct nvkm_vm **pvm) 75 { 76 return -EINVAL; 77 } 78 79 /******************************************************************************* 80 * MMU subdev 81 ******************************************************************************/ 82 83 static int 84 nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 85 struct nvkm_oclass *oclass, void *data, u32 size, 86 struct nvkm_object **pobject) 87 { 88 struct nv04_mmu_priv *priv; 89 struct nvkm_gpuobj *dma; 90 int ret; 91 92 ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", 93 "pcigart", &priv); 94 *pobject = nv_object(priv); 95 if (ret) 96 return ret; 97 98 priv->base.create = nv04_vm_create; 99 priv->base.limit = NV04_PDMA_SIZE; 100 priv->base.dma_bits = 32; 101 priv->base.pgt_bits = 32 - 12; 102 priv->base.spg_shift = 12; 103 priv->base.lpg_shift = 12; 104 priv->base.map_sg = nv04_vm_map_sg; 105 priv->base.unmap = nv04_vm_unmap; 106 priv->base.flush = nv04_vm_flush; 107 108 ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, 109 &priv->vm); 110 if (ret) 111 return ret; 112 113 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 114 (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8, 115 16, NVOBJ_FLAG_ZERO_ALLOC, 116 &priv->vm->pgt[0].obj[0]); 117 dma = priv->vm->pgt[0].obj[0]; 118 priv->vm->pgt[0].refcount[0] = 1; 119 if (ret) 120 return ret; 121 122 nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ 123 nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); 124 return 0; 125 } 126 127 void 128 nv04_mmu_dtor(struct nvkm_object *object) 129 { 130 struct nv04_mmu_priv *priv = (void *)object; 131 if (priv->vm) { 132 nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); 133 nvkm_vm_ref(NULL, &priv->vm, NULL); 134 } 135 if (priv->nullp) { 136 pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, 137 priv->nullp, priv->null); 138 } 139 nvkm_mmu_destroy(&priv->base); 140 } 141 142 struct nvkm_oclass 143 nv04_mmu_oclass = { 144 .handle = NV_SUBDEV(MMU, 0x04), 145 .ofuncs = &(struct nvkm_ofuncs) { 146 .ctor = nv04_mmu_ctor, 147 .dtor = nv04_mmu_dtor, 148 .init = _nvkm_mmu_init, 149 .fini = _nvkm_mmu_fini, 150 }, 151 }; 152