1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #define gp100_mc(p) container_of((p), struct gp100_mc, base)
25 #include "priv.h"
26 
27 struct gp100_mc {
28 	struct nvkm_mc base;
29 	spinlock_t lock;
30 	bool intr;
31 	u32 mask;
32 };
33 
34 static void
35 gp100_mc_intr_update(struct gp100_mc *mc)
36 {
37 	struct nvkm_device *device = mc->base.subdev.device;
38 	u32 mask = mc->intr ? mc->mask : 0, i;
39 	for (i = 0; i < 2; i++) {
40 		nvkm_wr32(device, 0x000180 + (i * 0x04), ~mask);
41 		nvkm_wr32(device, 0x000160 + (i * 0x04),  mask);
42 	}
43 }
44 
45 void
46 gp100_mc_intr_unarm(struct nvkm_mc *base)
47 {
48 	struct gp100_mc *mc = gp100_mc(base);
49 	unsigned long flags;
50 	spin_lock_irqsave(&mc->lock, flags);
51 	mc->intr = false;
52 	gp100_mc_intr_update(mc);
53 	spin_unlock_irqrestore(&mc->lock, flags);
54 }
55 
56 void
57 gp100_mc_intr_rearm(struct nvkm_mc *base)
58 {
59 	struct gp100_mc *mc = gp100_mc(base);
60 	unsigned long flags;
61 	spin_lock_irqsave(&mc->lock, flags);
62 	mc->intr = true;
63 	gp100_mc_intr_update(mc);
64 	spin_unlock_irqrestore(&mc->lock, flags);
65 }
66 
67 void
68 gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr)
69 {
70 	struct gp100_mc *mc = gp100_mc(base);
71 	unsigned long flags;
72 	spin_lock_irqsave(&mc->lock, flags);
73 	mc->mask = (mc->mask & ~mask) | intr;
74 	gp100_mc_intr_update(mc);
75 	spin_unlock_irqrestore(&mc->lock, flags);
76 }
77 
78 const struct nvkm_mc_map
79 gp100_mc_intr[] = {
80 	{ 0x04000000, NVKM_ENGINE_DISP },
81 	{ 0x00000100, NVKM_ENGINE_FIFO },
82 	{ 0x00000200, NVKM_SUBDEV_FAULT },
83 	{ 0x40000000, NVKM_SUBDEV_PRIVRING },
84 	{ 0x10000000, NVKM_SUBDEV_BUS },
85 	{ 0x08000000, NVKM_SUBDEV_FB },
86 	{ 0x02000000, NVKM_SUBDEV_LTC },
87 	{ 0x01000000, NVKM_SUBDEV_PMU },
88 	{ 0x00200000, NVKM_SUBDEV_GPIO },
89 	{ 0x00200000, NVKM_SUBDEV_I2C },
90 	{ 0x00100000, NVKM_SUBDEV_TIMER },
91 	{ 0x00040000, NVKM_SUBDEV_THERM },
92 	{ 0x00002000, NVKM_SUBDEV_FB },
93 	{},
94 };
95 
96 static const struct nvkm_mc_func
97 gp100_mc = {
98 	.init = nv50_mc_init,
99 	.intr = gp100_mc_intr,
100 	.intr_unarm = gp100_mc_intr_unarm,
101 	.intr_rearm = gp100_mc_intr_rearm,
102 	.intr_mask = gp100_mc_intr_mask,
103 	.intr_stat = gf100_mc_intr_stat,
104 	.reset = gk104_mc_reset,
105 };
106 
107 int
108 gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device,
109 	      enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
110 {
111 	struct gp100_mc *mc;
112 
113 	if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL)))
114 		return -ENOMEM;
115 	nvkm_mc_ctor(func, device, type, inst, &mc->base);
116 	*pmc = &mc->base;
117 
118 	spin_lock_init(&mc->lock);
119 	mc->intr = false;
120 	mc->mask = 0x7fffffff;
121 	return 0;
122 }
123 
124 int
125 gp100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
126 {
127 	return gp100_mc_new_(&gp100_mc, device, type, inst, pmc);
128 }
129