1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 const struct nvkm_mc_intr 27 gf100_mc_intr[] = { 28 { 0x04000000, NVKM_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ 29 { 0x00000001, NVKM_ENGINE_MSPPP }, 30 { 0x00000020, NVKM_ENGINE_CE0 }, 31 { 0x00000040, NVKM_ENGINE_CE1 }, 32 { 0x00000080, NVKM_ENGINE_CE2 }, 33 { 0x00000100, NVKM_ENGINE_FIFO }, 34 { 0x00001000, NVKM_ENGINE_GR }, 35 { 0x00002000, NVKM_SUBDEV_FB }, 36 { 0x00008000, NVKM_ENGINE_MSVLD }, 37 { 0x00040000, NVKM_SUBDEV_THERM }, 38 { 0x00020000, NVKM_ENGINE_MSPDEC }, 39 { 0x00100000, NVKM_SUBDEV_TIMER }, 40 { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */ 41 { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */ 42 { 0x01000000, NVKM_SUBDEV_PMU }, 43 { 0x02000000, NVKM_SUBDEV_LTC }, 44 { 0x08000000, NVKM_SUBDEV_FB }, 45 { 0x10000000, NVKM_SUBDEV_BUS }, 46 { 0x40000000, NVKM_SUBDEV_IBUS }, 47 { 0x80000000, NVKM_ENGINE_SW }, 48 {}, 49 }; 50 51 void 52 gf100_mc_intr_unarm(struct nvkm_mc *mc) 53 { 54 struct nvkm_device *device = mc->subdev.device; 55 nvkm_wr32(device, 0x000140, 0x00000000); 56 nvkm_wr32(device, 0x000144, 0x00000000); 57 nvkm_rd32(device, 0x000140); 58 } 59 60 void 61 gf100_mc_intr_rearm(struct nvkm_mc *mc) 62 { 63 struct nvkm_device *device = mc->subdev.device; 64 nvkm_wr32(device, 0x000140, 0x00000001); 65 nvkm_wr32(device, 0x000144, 0x00000001); 66 } 67 68 u32 69 gf100_mc_intr_mask(struct nvkm_mc *mc) 70 { 71 struct nvkm_device *device = mc->subdev.device; 72 u32 intr0 = nvkm_rd32(device, 0x000100); 73 u32 intr1 = nvkm_rd32(device, 0x000104); 74 return intr0 | intr1; 75 } 76 77 void 78 gf100_mc_unk260(struct nvkm_mc *mc, u32 data) 79 { 80 nvkm_wr32(mc->subdev.device, 0x000260, data); 81 } 82 83 static const struct nvkm_mc_func 84 gf100_mc = { 85 .init = nv50_mc_init, 86 .intr = gf100_mc_intr, 87 .intr_unarm = gf100_mc_intr_unarm, 88 .intr_rearm = gf100_mc_intr_rearm, 89 .intr_mask = gf100_mc_intr_mask, 90 .unk260 = gf100_mc_unk260, 91 }; 92 93 int 94 gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) 95 { 96 return nvkm_mc_new_(&gf100_mc, device, index, pmc); 97 } 98