1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv04.h"
25 
26 const struct nvkm_mc_intr
27 gf100_mc_intr[] = {
28 	{ 0x04000000, NVDEV_ENGINE_DISP },  /* DISP first, so pageflip timestamps work. */
29 	{ 0x00000001, NVDEV_ENGINE_MSPPP },
30 	{ 0x00000020, NVDEV_ENGINE_CE0 },
31 	{ 0x00000040, NVDEV_ENGINE_CE1 },
32 	{ 0x00000080, NVDEV_ENGINE_CE2 },
33 	{ 0x00000100, NVDEV_ENGINE_FIFO },
34 	{ 0x00001000, NVDEV_ENGINE_GR },
35 	{ 0x00002000, NVDEV_SUBDEV_FB },
36 	{ 0x00008000, NVDEV_ENGINE_MSVLD },
37 	{ 0x00040000, NVDEV_SUBDEV_THERM },
38 	{ 0x00020000, NVDEV_ENGINE_MSPDEC },
39 	{ 0x00100000, NVDEV_SUBDEV_TIMER },
40 	{ 0x00200000, NVDEV_SUBDEV_GPIO },	/* PMGR->GPIO */
41 	{ 0x00200000, NVDEV_SUBDEV_I2C },	/* PMGR->I2C/AUX */
42 	{ 0x01000000, NVDEV_SUBDEV_PMU },
43 	{ 0x02000000, NVDEV_SUBDEV_LTC },
44 	{ 0x08000000, NVDEV_SUBDEV_FB },
45 	{ 0x10000000, NVDEV_SUBDEV_BUS },
46 	{ 0x40000000, NVDEV_SUBDEV_IBUS },
47 	{ 0x80000000, NVDEV_ENGINE_SW },
48 	{},
49 };
50 
51 static void
52 gf100_mc_msi_rearm(struct nvkm_mc *mc)
53 {
54 	nv_wr32(mc, 0x088704, 0x00000000);
55 }
56 
57 void
58 gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
59 {
60 	nv_wr32(mc, 0x000260, data);
61 }
62 
63 struct nvkm_oclass *
64 gf100_mc_oclass = &(struct nvkm_mc_oclass) {
65 	.base.handle = NV_SUBDEV(MC, 0xc0),
66 	.base.ofuncs = &(struct nvkm_ofuncs) {
67 		.ctor = nv04_mc_ctor,
68 		.dtor = _nvkm_mc_dtor,
69 		.init = nv50_mc_init,
70 		.fini = _nvkm_mc_fini,
71 	},
72 	.intr = gf100_mc_intr,
73 	.msi_rearm = gf100_mc_msi_rearm,
74 	.unk260 = gf100_mc_unk260,
75 }.base;
76