1 /* 2 * Copyright 2014 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 #include <subdev/fb.h> 27 #include <subdev/timer.h> 28 29 static void 30 gm107_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit) 31 { 32 struct nvkm_device *device = ltc->base.subdev.device; 33 nvkm_wr32(device, 0x17e270, start); 34 nvkm_wr32(device, 0x17e274, limit); 35 nvkm_wr32(device, 0x17e26c, 0x00000004); 36 } 37 38 static void 39 gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) 40 { 41 int c, s; 42 for (c = 0; c < ltc->ltc_nr; c++) { 43 for (s = 0; s < ltc->lts_nr; s++) 44 nv_wait(ltc, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0); 45 } 46 } 47 48 static void 49 gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) 50 { 51 struct nvkm_device *device = ltc->base.subdev.device; 52 nvkm_mask(device, 0x17e338, 0x0000000f, i); 53 nvkm_wr32(device, 0x17e33c, color[0]); 54 nvkm_wr32(device, 0x17e340, color[1]); 55 nvkm_wr32(device, 0x17e344, color[2]); 56 nvkm_wr32(device, 0x17e348, color[3]); 57 } 58 59 static void 60 gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth) 61 { 62 struct nvkm_device *device = ltc->base.subdev.device; 63 nvkm_mask(device, 0x17e338, 0x0000000f, i); 64 nvkm_wr32(device, 0x17e34c, depth); 65 } 66 67 static void 68 gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s) 69 { 70 struct nvkm_device *device = ltc->base.subdev.device; 71 u32 base = 0x140000 + (c * 0x2000) + (s * 0x400); 72 u32 stat = nvkm_rd32(device, base + 0x00c); 73 74 if (stat) { 75 nv_info(ltc, "LTC%d_LTS%d: 0x%08x\n", c, s, stat); 76 nvkm_wr32(device, base + 0x00c, stat); 77 } 78 } 79 80 static void 81 gm107_ltc_intr(struct nvkm_subdev *subdev) 82 { 83 struct nvkm_ltc_priv *ltc = (void *)subdev; 84 struct nvkm_device *device = ltc->base.subdev.device; 85 u32 mask; 86 87 mask = nvkm_rd32(device, 0x00017c); 88 while (mask) { 89 u32 s, c = __ffs(mask); 90 for (s = 0; s < ltc->lts_nr; s++) 91 gm107_ltc_lts_isr(ltc, c, s); 92 mask &= ~(1 << c); 93 } 94 } 95 96 static int 97 gm107_ltc_init(struct nvkm_object *object) 98 { 99 struct nvkm_ltc_priv *ltc = (void *)object; 100 struct nvkm_device *device = ltc->base.subdev.device; 101 u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); 102 int ret; 103 104 ret = nvkm_ltc_init(ltc); 105 if (ret) 106 return ret; 107 108 nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); 109 nvkm_wr32(device, 0x17e278, ltc->tag_base); 110 nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); 111 return 0; 112 } 113 114 static int 115 gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 116 struct nvkm_oclass *oclass, void *data, u32 size, 117 struct nvkm_object **pobject) 118 { 119 struct nvkm_device *device = (void *)parent; 120 struct nvkm_fb *fb = device->fb; 121 struct nvkm_ltc_priv *ltc; 122 u32 parts, mask; 123 int ret, i; 124 125 ret = nvkm_ltc_create(parent, engine, oclass, <c); 126 *pobject = nv_object(ltc); 127 if (ret) 128 return ret; 129 130 parts = nvkm_rd32(device, 0x022438); 131 mask = nvkm_rd32(device, 0x021c14); 132 for (i = 0; i < parts; i++) { 133 if (!(mask & (1 << i))) 134 ltc->ltc_nr++; 135 } 136 ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; 137 138 ret = gf100_ltc_init_tag_ram(fb, ltc); 139 if (ret) 140 return ret; 141 142 return 0; 143 } 144 145 struct nvkm_oclass * 146 gm107_ltc_oclass = &(struct nvkm_ltc_impl) { 147 .base.handle = NV_SUBDEV(LTC, 0xff), 148 .base.ofuncs = &(struct nvkm_ofuncs) { 149 .ctor = gm107_ltc_ctor, 150 .dtor = gf100_ltc_dtor, 151 .init = gm107_ltc_init, 152 .fini = _nvkm_ltc_fini, 153 }, 154 .intr = gm107_ltc_intr, 155 .cbc_clear = gm107_ltc_cbc_clear, 156 .cbc_wait = gm107_ltc_cbc_wait, 157 .zbc = 16, 158 .zbc_clear_color = gm107_ltc_zbc_clear_color, 159 .zbc_clear_depth = gm107_ltc_zbc_clear_depth, 160 }.base; 161