1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 #include <core/enum.h> 27 #include <subdev/fb.h> 28 #include <subdev/timer.h> 29 30 void 31 gf100_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit) 32 { 33 struct nvkm_device *device = ltc->base.subdev.device; 34 nvkm_wr32(device, 0x17e8cc, start); 35 nvkm_wr32(device, 0x17e8d0, limit); 36 nvkm_wr32(device, 0x17e8c8, 0x00000004); 37 } 38 39 void 40 gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) 41 { 42 struct nvkm_device *device = ltc->base.subdev.device; 43 int c, s; 44 for (c = 0; c < ltc->ltc_nr; c++) { 45 for (s = 0; s < ltc->lts_nr; s++) { 46 const u32 addr = 0x1410c8 + (c * 0x2000) + (s * 0x400); 47 nvkm_msec(device, 2000, 48 if (!nvkm_rd32(device, addr)) 49 break; 50 ); 51 } 52 } 53 } 54 55 void 56 gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) 57 { 58 struct nvkm_device *device = ltc->base.subdev.device; 59 nvkm_mask(device, 0x17ea44, 0x0000000f, i); 60 nvkm_wr32(device, 0x17ea48, color[0]); 61 nvkm_wr32(device, 0x17ea4c, color[1]); 62 nvkm_wr32(device, 0x17ea50, color[2]); 63 nvkm_wr32(device, 0x17ea54, color[3]); 64 } 65 66 void 67 gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth) 68 { 69 struct nvkm_device *device = ltc->base.subdev.device; 70 nvkm_mask(device, 0x17ea44, 0x0000000f, i); 71 nvkm_wr32(device, 0x17ea58, depth); 72 } 73 74 static const struct nvkm_bitfield 75 gf100_ltc_lts_intr_name[] = { 76 { 0x00000001, "IDLE_ERROR_IQ" }, 77 { 0x00000002, "IDLE_ERROR_CBC" }, 78 { 0x00000004, "IDLE_ERROR_TSTG" }, 79 { 0x00000008, "IDLE_ERROR_DSTG" }, 80 { 0x00000010, "EVICTED_CB" }, 81 { 0x00000020, "ILLEGAL_COMPSTAT" }, 82 { 0x00000040, "BLOCKLINEAR_CB" }, 83 { 0x00000100, "ECC_SEC_ERROR" }, 84 { 0x00000200, "ECC_DED_ERROR" }, 85 { 0x00000400, "DEBUG" }, 86 { 0x00000800, "ATOMIC_TO_Z" }, 87 { 0x00001000, "ILLEGAL_ATOMIC" }, 88 { 0x00002000, "BLKACTIVITY_ERR" }, 89 {} 90 }; 91 92 static void 93 gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s) 94 { 95 struct nvkm_subdev *subdev = <c->base.subdev; 96 struct nvkm_device *device = subdev->device; 97 u32 base = 0x141000 + (c * 0x2000) + (s * 0x400); 98 u32 intr = nvkm_rd32(device, base + 0x020); 99 u32 stat = intr & 0x0000ffff; 100 char msg[128]; 101 102 if (stat) { 103 nvkm_snprintbf(msg, sizeof(msg), gf100_ltc_lts_intr_name, stat); 104 nvkm_error(subdev, "LTC%d_LTS%d: %08x [%s]\n", c, s, stat, msg); 105 } 106 107 nvkm_wr32(device, base + 0x020, intr); 108 } 109 110 void 111 gf100_ltc_intr(struct nvkm_subdev *subdev) 112 { 113 struct nvkm_ltc_priv *ltc = (void *)subdev; 114 struct nvkm_device *device = ltc->base.subdev.device; 115 u32 mask; 116 117 mask = nvkm_rd32(device, 0x00017c); 118 while (mask) { 119 u32 s, c = __ffs(mask); 120 for (s = 0; s < ltc->lts_nr; s++) 121 gf100_ltc_lts_intr(ltc, c, s); 122 mask &= ~(1 << c); 123 } 124 } 125 126 static int 127 gf100_ltc_init(struct nvkm_object *object) 128 { 129 struct nvkm_ltc_priv *ltc = (void *)object; 130 struct nvkm_device *device = ltc->base.subdev.device; 131 u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); 132 int ret; 133 134 ret = nvkm_ltc_init(ltc); 135 if (ret) 136 return ret; 137 138 nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ 139 nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr); 140 nvkm_wr32(device, 0x17e8d4, ltc->tag_base); 141 nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); 142 return 0; 143 } 144 145 void 146 gf100_ltc_dtor(struct nvkm_object *object) 147 { 148 struct nvkm_fb *fb = nvkm_fb(object); 149 struct nvkm_ltc_priv *ltc = (void *)object; 150 151 nvkm_mm_fini(<c->tags); 152 if (fb->ram) 153 nvkm_mm_free(&fb->vram, <c->tag_ram); 154 155 nvkm_ltc_destroy(ltc); 156 } 157 158 /* TODO: Figure out tag memory details and drop the over-cautious allocation. 159 */ 160 int 161 gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *ltc) 162 { 163 u32 tag_size, tag_margin, tag_align; 164 int ret; 165 166 /* No VRAM, no tags for now. */ 167 if (!fb->ram) { 168 ltc->num_tags = 0; 169 goto mm_init; 170 } 171 172 /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ 173 ltc->num_tags = (fb->ram->size >> 17) / 4; 174 if (ltc->num_tags > (1 << 17)) 175 ltc->num_tags = 1 << 17; /* we have 17 bits in PTE */ 176 ltc->num_tags = (ltc->num_tags + 63) & ~63; /* round up to 64 */ 177 178 tag_align = ltc->ltc_nr * 0x800; 179 tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align; 180 181 /* 4 part 4 sub: 0x2000 bytes for 56 tags */ 182 /* 3 part 4 sub: 0x6000 bytes for 168 tags */ 183 /* 184 * About 147 bytes per tag. Let's be safe and allocate x2, which makes 185 * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags. 186 * 187 * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %. 188 */ 189 tag_size = (ltc->num_tags / 64) * 0x6000 + tag_margin; 190 tag_size += tag_align; 191 tag_size = (tag_size + 0xfff) >> 12; /* round up */ 192 193 ret = nvkm_mm_tail(&fb->vram, 1, 1, tag_size, tag_size, 1, 194 <c->tag_ram); 195 if (ret) { 196 ltc->num_tags = 0; 197 } else { 198 u64 tag_base = ((u64)ltc->tag_ram->offset << 12) + tag_margin; 199 200 tag_base += tag_align - 1; 201 do_div(tag_base, tag_align); 202 203 ltc->tag_base = tag_base; 204 } 205 206 mm_init: 207 ret = nvkm_mm_init(<c->tags, 0, ltc->num_tags, 1); 208 return ret; 209 } 210 211 int 212 gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 213 struct nvkm_oclass *oclass, void *data, u32 size, 214 struct nvkm_object **pobject) 215 { 216 struct nvkm_device *device = (void *)parent; 217 struct nvkm_fb *fb = device->fb; 218 struct nvkm_ltc_priv *ltc; 219 u32 parts, mask; 220 int ret, i; 221 222 ret = nvkm_ltc_create(parent, engine, oclass, <c); 223 *pobject = nv_object(ltc); 224 if (ret) 225 return ret; 226 227 parts = nvkm_rd32(device, 0x022438); 228 mask = nvkm_rd32(device, 0x022554); 229 for (i = 0; i < parts; i++) { 230 if (!(mask & (1 << i))) 231 ltc->ltc_nr++; 232 } 233 ltc->lts_nr = nvkm_rd32(device, 0x17e8dc) >> 28; 234 235 ret = gf100_ltc_init_tag_ram(fb, ltc); 236 if (ret) 237 return ret; 238 239 nv_subdev(ltc)->intr = gf100_ltc_intr; 240 return 0; 241 } 242 243 struct nvkm_oclass * 244 gf100_ltc_oclass = &(struct nvkm_ltc_impl) { 245 .base.handle = NV_SUBDEV(LTC, 0xc0), 246 .base.ofuncs = &(struct nvkm_ofuncs) { 247 .ctor = gf100_ltc_ctor, 248 .dtor = gf100_ltc_dtor, 249 .init = gf100_ltc_init, 250 .fini = _nvkm_ltc_fini, 251 }, 252 .intr = gf100_ltc_intr, 253 .cbc_clear = gf100_ltc_cbc_clear, 254 .cbc_wait = gf100_ltc_cbc_wait, 255 .zbc = 16, 256 .zbc_clear_color = gf100_ltc_zbc_clear_color, 257 .zbc_clear_depth = gf100_ltc_zbc_clear_depth, 258 }.base; 259