1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv04.h" 25 26 #include <core/ramht.h> 27 #include <engine/gr/nv40.h> 28 29 /****************************************************************************** 30 * instmem subdev implementation 31 *****************************************************************************/ 32 33 static u32 34 nv40_instmem_rd32(struct nvkm_object *object, u64 addr) 35 { 36 struct nv04_instmem *imem = (void *)object; 37 return ioread32_native(imem->iomem + addr); 38 } 39 40 static void 41 nv40_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data) 42 { 43 struct nv04_instmem *imem = (void *)object; 44 iowrite32_native(data, imem->iomem + addr); 45 } 46 47 static int 48 nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 49 struct nvkm_oclass *oclass, void *data, u32 size, 50 struct nvkm_object **pobject) 51 { 52 struct nvkm_device *device = nv_device(parent); 53 struct nv04_instmem *imem; 54 int ret, bar, vs; 55 56 ret = nvkm_instmem_create(parent, engine, oclass, &imem); 57 *pobject = nv_object(imem); 58 if (ret) 59 return ret; 60 61 /* map bar */ 62 if (nv_device_resource_len(device, 2)) 63 bar = 2; 64 else 65 bar = 3; 66 67 imem->iomem = ioremap(nv_device_resource_start(device, bar), 68 nv_device_resource_len(device, bar)); 69 if (!imem->iomem) { 70 nv_error(imem, "unable to map PRAMIN BAR\n"); 71 return -EFAULT; 72 } 73 74 /* PRAMIN aperture maps over the end of vram, reserve enough space 75 * to fit graphics contexts for every channel, the magics come 76 * from engine/gr/nv40.c 77 */ 78 vs = hweight8((nv_rd32(imem, 0x001540) & 0x0000ff00) >> 8); 79 if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; 80 else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; 81 else if (nv44_gr_class(imem)) imem->base.reserved = 0x4980 * vs; 82 else imem->base.reserved = 0x4a40 * vs; 83 imem->base.reserved += 16 * 1024; 84 imem->base.reserved *= 32; /* per-channel */ 85 imem->base.reserved += 512 * 1024; /* pci(e)gart table */ 86 imem->base.reserved += 512 * 1024; /* object storage */ 87 88 imem->base.reserved = round_up(imem->base.reserved, 4096); 89 90 ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1); 91 if (ret) 92 return ret; 93 94 /* 0x00000-0x10000: reserve for probable vbios image */ 95 ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x10000, 0, 0, 96 &imem->vbios); 97 if (ret) 98 return ret; 99 100 /* 0x10000-0x18000: reserve for RAMHT */ 101 ret = nvkm_ramht_new(nv_object(imem), NULL, 0x08000, 0, &imem->ramht); 102 if (ret) 103 return ret; 104 105 /* 0x18000-0x18200: reserve for RAMRO 106 * 0x18200-0x20000: padding 107 */ 108 ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x08000, 0, 0, 109 &imem->ramro); 110 if (ret) 111 return ret; 112 113 /* 0x20000-0x21000: reserve for RAMFC 114 * 0x21000-0x40000: padding and some unknown crap 115 */ 116 ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x20000, 0, 117 NVOBJ_FLAG_ZERO_ALLOC, &imem->ramfc); 118 if (ret) 119 return ret; 120 121 return 0; 122 } 123 124 struct nvkm_oclass * 125 nv40_instmem_oclass = &(struct nvkm_instmem_impl) { 126 .base.handle = NV_SUBDEV(INSTMEM, 0x40), 127 .base.ofuncs = &(struct nvkm_ofuncs) { 128 .ctor = nv40_instmem_ctor, 129 .dtor = nv04_instmem_dtor, 130 .init = _nvkm_instmem_init, 131 .fini = _nvkm_instmem_fini, 132 .rd32 = nv40_instmem_rd32, 133 .wr32 = nv40_instmem_wr32, 134 }, 135 .instobj = &nv04_instobj_oclass.base, 136 }.base; 137