1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #define nv40_instmem(p) container_of((p), struct nv40_instmem, base) 25 #include "priv.h" 26 27 #include <core/memory.h> 28 #include <core/ramht.h> 29 #include <engine/gr/nv40.h> 30 31 struct nv40_instmem { 32 struct nvkm_instmem base; 33 struct nvkm_mm heap; 34 void __iomem *iomem; 35 }; 36 37 /****************************************************************************** 38 * instmem object implementation 39 *****************************************************************************/ 40 #define nv40_instobj(p) container_of((p), struct nv40_instobj, memory) 41 42 struct nv40_instobj { 43 struct nvkm_memory memory; 44 struct nv40_instmem *imem; 45 struct nvkm_mm_node *node; 46 }; 47 48 static enum nvkm_memory_target 49 nv40_instobj_target(struct nvkm_memory *memory) 50 { 51 return NVKM_MEM_TARGET_INST; 52 } 53 54 static u64 55 nv40_instobj_addr(struct nvkm_memory *memory) 56 { 57 return nv40_instobj(memory)->node->offset; 58 } 59 60 static u64 61 nv40_instobj_size(struct nvkm_memory *memory) 62 { 63 return nv40_instobj(memory)->node->length; 64 } 65 66 static void __iomem * 67 nv40_instobj_acquire(struct nvkm_memory *memory) 68 { 69 struct nv40_instobj *iobj = nv40_instobj(memory); 70 return iobj->imem->iomem + iobj->node->offset; 71 } 72 73 static void 74 nv40_instobj_release(struct nvkm_memory *memory) 75 { 76 } 77 78 static u32 79 nv40_instobj_rd32(struct nvkm_memory *memory, u64 offset) 80 { 81 struct nv40_instobj *iobj = nv40_instobj(memory); 82 return ioread32_native(iobj->imem->iomem + iobj->node->offset + offset); 83 } 84 85 static void 86 nv40_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) 87 { 88 struct nv40_instobj *iobj = nv40_instobj(memory); 89 iowrite32_native(data, iobj->imem->iomem + iobj->node->offset + offset); 90 } 91 92 static void * 93 nv40_instobj_dtor(struct nvkm_memory *memory) 94 { 95 struct nv40_instobj *iobj = nv40_instobj(memory); 96 mutex_lock(&iobj->imem->base.subdev.mutex); 97 nvkm_mm_free(&iobj->imem->heap, &iobj->node); 98 mutex_unlock(&iobj->imem->base.subdev.mutex); 99 return iobj; 100 } 101 102 static const struct nvkm_memory_func 103 nv40_instobj_func = { 104 .dtor = nv40_instobj_dtor, 105 .target = nv40_instobj_target, 106 .size = nv40_instobj_size, 107 .addr = nv40_instobj_addr, 108 .acquire = nv40_instobj_acquire, 109 .release = nv40_instobj_release, 110 .rd32 = nv40_instobj_rd32, 111 .wr32 = nv40_instobj_wr32, 112 }; 113 114 static int 115 nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, 116 struct nvkm_memory **pmemory) 117 { 118 struct nv40_instmem *imem = nv40_instmem(base); 119 struct nv40_instobj *iobj; 120 int ret; 121 122 if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) 123 return -ENOMEM; 124 *pmemory = &iobj->memory; 125 126 nvkm_memory_ctor(&nv40_instobj_func, &iobj->memory); 127 iobj->imem = imem; 128 129 mutex_lock(&imem->base.subdev.mutex); 130 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, 131 align ? align : 1, &iobj->node); 132 mutex_unlock(&imem->base.subdev.mutex); 133 return ret; 134 } 135 136 /****************************************************************************** 137 * instmem subdev implementation 138 *****************************************************************************/ 139 140 static u32 141 nv40_instmem_rd32(struct nvkm_instmem *obj, u32 addr) 142 { 143 struct nv40_instmem *imem = container_of(obj, typeof(*imem), base); 144 return ioread32_native(imem->iomem + addr); 145 } 146 147 static void 148 nv40_instmem_wr32(struct nvkm_instmem *obj, u32 addr, u32 data) 149 { 150 struct nv40_instmem *imem = container_of(obj, typeof(*imem), base); 151 iowrite32_native(data, imem->iomem + addr); 152 } 153 154 static void 155 nv40_instmem_dtor(struct nvkm_object *object) 156 { 157 struct nv40_instmem *imem = (void *)object; 158 nvkm_memory_del(&imem->base.ramfc); 159 nvkm_memory_del(&imem->base.ramro); 160 nvkm_ramht_del(&imem->base.ramht); 161 nvkm_memory_del(&imem->base.vbios); 162 nvkm_mm_fini(&imem->heap); 163 if (imem->iomem) 164 iounmap(imem->iomem); 165 nvkm_instmem_destroy(&imem->base); 166 } 167 168 static const struct nvkm_instmem_func 169 nv40_instmem_func = { 170 .rd32 = nv40_instmem_rd32, 171 .wr32 = nv40_instmem_wr32, 172 }; 173 174 static int 175 nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 176 struct nvkm_oclass *oclass, void *data, u32 size, 177 struct nvkm_object **pobject) 178 { 179 struct nvkm_device *device = (void *)parent; 180 struct nv40_instmem *imem; 181 int ret, bar, vs; 182 183 ret = nvkm_instmem_create(parent, engine, oclass, &imem); 184 *pobject = nv_object(imem); 185 if (ret) 186 return ret; 187 188 imem->base.func = &nv40_instmem_func; 189 190 /* map bar */ 191 if (nv_device_resource_len(device, 2)) 192 bar = 2; 193 else 194 bar = 3; 195 196 imem->iomem = ioremap(nv_device_resource_start(device, bar), 197 nv_device_resource_len(device, bar)); 198 if (!imem->iomem) { 199 nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n"); 200 return -EFAULT; 201 } 202 203 /* PRAMIN aperture maps over the end of vram, reserve enough space 204 * to fit graphics contexts for every channel, the magics come 205 * from engine/gr/nv40.c 206 */ 207 vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8); 208 if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; 209 else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; 210 else if (nv44_gr_class(imem)) imem->base.reserved = 0x4980 * vs; 211 else imem->base.reserved = 0x4a40 * vs; 212 imem->base.reserved += 16 * 1024; 213 imem->base.reserved *= 32; /* per-channel */ 214 imem->base.reserved += 512 * 1024; /* pci(e)gart table */ 215 imem->base.reserved += 512 * 1024; /* object storage */ 216 217 imem->base.reserved = round_up(imem->base.reserved, 4096); 218 219 ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1); 220 if (ret) 221 return ret; 222 223 /* 0x00000-0x10000: reserve for probable vbios image */ 224 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, 225 &imem->base.vbios); 226 if (ret) 227 return ret; 228 229 /* 0x10000-0x18000: reserve for RAMHT */ 230 ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); 231 if (ret) 232 return ret; 233 234 /* 0x18000-0x18200: reserve for RAMRO 235 * 0x18200-0x20000: padding 236 */ 237 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x08000, 0, false, 238 &imem->base.ramro); 239 if (ret) 240 return ret; 241 242 /* 0x20000-0x21000: reserve for RAMFC 243 * 0x21000-0x40000: padding and some unknown crap 244 */ 245 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x20000, 0, true, 246 &imem->base.ramfc); 247 if (ret) 248 return ret; 249 250 return 0; 251 } 252 253 struct nvkm_oclass * 254 nv40_instmem_oclass = &(struct nvkm_instmem_impl) { 255 .base.handle = NV_SUBDEV(INSTMEM, 0x40), 256 .base.ofuncs = &(struct nvkm_ofuncs) { 257 .ctor = nv40_instmem_ctor, 258 .dtor = nv40_instmem_dtor, 259 .init = _nvkm_instmem_init, 260 .fini = _nvkm_instmem_fini, 261 }, 262 .memory_new = nv40_instobj_new, 263 .persistent = false, 264 .zero = false, 265 }.base; 266