1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv04.h" 25 26 #include <core/ramht.h> 27 28 /****************************************************************************** 29 * instmem object implementation 30 *****************************************************************************/ 31 32 static u32 33 nv04_instobj_rd32(struct nvkm_object *object, u64 addr) 34 { 35 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object); 36 struct nv04_instobj_priv *node = (void *)object; 37 return nv_ro32(priv, node->mem->offset + addr); 38 } 39 40 static void 41 nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data) 42 { 43 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object); 44 struct nv04_instobj_priv *node = (void *)object; 45 nv_wo32(priv, node->mem->offset + addr, data); 46 } 47 48 static void 49 nv04_instobj_dtor(struct nvkm_object *object) 50 { 51 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object); 52 struct nv04_instobj_priv *node = (void *)object; 53 nvkm_mm_free(&priv->heap, &node->mem); 54 nvkm_instobj_destroy(&node->base); 55 } 56 57 static int 58 nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 59 struct nvkm_oclass *oclass, void *data, u32 size, 60 struct nvkm_object **pobject) 61 { 62 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent); 63 struct nv04_instobj_priv *node; 64 struct nvkm_instobj_args *args = data; 65 int ret; 66 67 if (!args->align) 68 args->align = 1; 69 70 ret = nvkm_instobj_create(parent, engine, oclass, &node); 71 *pobject = nv_object(node); 72 if (ret) 73 return ret; 74 75 ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size, 76 args->align, &node->mem); 77 if (ret) 78 return ret; 79 80 node->base.addr = node->mem->offset; 81 node->base.size = node->mem->length; 82 return 0; 83 } 84 85 struct nvkm_instobj_impl 86 nv04_instobj_oclass = { 87 .base.ofuncs = &(struct nvkm_ofuncs) { 88 .ctor = nv04_instobj_ctor, 89 .dtor = nv04_instobj_dtor, 90 .init = _nvkm_instobj_init, 91 .fini = _nvkm_instobj_fini, 92 .rd32 = nv04_instobj_rd32, 93 .wr32 = nv04_instobj_wr32, 94 }, 95 }; 96 97 /****************************************************************************** 98 * instmem subdev implementation 99 *****************************************************************************/ 100 101 static u32 102 nv04_instmem_rd32(struct nvkm_object *object, u64 addr) 103 { 104 return nv_rd32(object, 0x700000 + addr); 105 } 106 107 static void 108 nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data) 109 { 110 return nv_wr32(object, 0x700000 + addr, data); 111 } 112 113 void 114 nv04_instmem_dtor(struct nvkm_object *object) 115 { 116 struct nv04_instmem_priv *priv = (void *)object; 117 nvkm_gpuobj_ref(NULL, &priv->ramfc); 118 nvkm_gpuobj_ref(NULL, &priv->ramro); 119 nvkm_ramht_ref(NULL, &priv->ramht); 120 nvkm_gpuobj_ref(NULL, &priv->vbios); 121 nvkm_mm_fini(&priv->heap); 122 if (priv->iomem) 123 iounmap(priv->iomem); 124 nvkm_instmem_destroy(&priv->base); 125 } 126 127 static int 128 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 129 struct nvkm_oclass *oclass, void *data, u32 size, 130 struct nvkm_object **pobject) 131 { 132 struct nv04_instmem_priv *priv; 133 int ret; 134 135 ret = nvkm_instmem_create(parent, engine, oclass, &priv); 136 *pobject = nv_object(priv); 137 if (ret) 138 return ret; 139 140 /* PRAMIN aperture maps over the end of VRAM, reserve it */ 141 priv->base.reserved = 512 * 1024; 142 143 ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1); 144 if (ret) 145 return ret; 146 147 /* 0x00000-0x10000: reserve for probable vbios image */ 148 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, 149 &priv->vbios); 150 if (ret) 151 return ret; 152 153 /* 0x10000-0x18000: reserve for RAMHT */ 154 ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht); 155 if (ret) 156 return ret; 157 158 /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */ 159 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00800, 0, 160 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); 161 if (ret) 162 return ret; 163 164 /* 0x18800-0x18a00: reserve for RAMRO */ 165 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0, 166 &priv->ramro); 167 if (ret) 168 return ret; 169 170 return 0; 171 } 172 173 struct nvkm_oclass * 174 nv04_instmem_oclass = &(struct nvkm_instmem_impl) { 175 .base.handle = NV_SUBDEV(INSTMEM, 0x04), 176 .base.ofuncs = &(struct nvkm_ofuncs) { 177 .ctor = nv04_instmem_ctor, 178 .dtor = nv04_instmem_dtor, 179 .init = _nvkm_instmem_init, 180 .fini = _nvkm_instmem_fini, 181 .rd32 = nv04_instmem_rd32, 182 .wr32 = nv04_instmem_wr32, 183 }, 184 .instobj = &nv04_instobj_oclass.base, 185 }.base; 186