1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #define nv04_instmem(p) container_of((p), struct nv04_instmem, base) 25 #include "priv.h" 26 27 #include <core/memory.h> 28 #include <core/ramht.h> 29 30 struct nv04_instmem { 31 struct nvkm_instmem base; 32 struct nvkm_mm heap; 33 }; 34 35 /****************************************************************************** 36 * instmem object implementation 37 *****************************************************************************/ 38 #define nv04_instobj(p) container_of((p), struct nv04_instobj, memory) 39 40 struct nv04_instobj { 41 struct nvkm_memory memory; 42 struct nv04_instmem *imem; 43 struct nvkm_mm_node *node; 44 }; 45 46 static enum nvkm_memory_target 47 nv04_instobj_target(struct nvkm_memory *memory) 48 { 49 return NVKM_MEM_TARGET_INST; 50 } 51 52 static u64 53 nv04_instobj_addr(struct nvkm_memory *memory) 54 { 55 return nv04_instobj(memory)->node->offset; 56 } 57 58 static u64 59 nv04_instobj_size(struct nvkm_memory *memory) 60 { 61 return nv04_instobj(memory)->node->length; 62 } 63 64 static void __iomem * 65 nv04_instobj_acquire(struct nvkm_memory *memory) 66 { 67 struct nv04_instobj *iobj = nv04_instobj(memory); 68 struct nvkm_device *device = iobj->imem->base.subdev.device; 69 return device->pri + 0x700000 + iobj->node->offset; 70 } 71 72 static void 73 nv04_instobj_release(struct nvkm_memory *memory) 74 { 75 } 76 77 static u32 78 nv04_instobj_rd32(struct nvkm_memory *memory, u64 offset) 79 { 80 struct nv04_instobj *iobj = nv04_instobj(memory); 81 struct nvkm_device *device = iobj->imem->base.subdev.device; 82 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); 83 } 84 85 static void 86 nv04_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) 87 { 88 struct nv04_instobj *iobj = nv04_instobj(memory); 89 struct nvkm_device *device = iobj->imem->base.subdev.device; 90 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); 91 } 92 93 static void * 94 nv04_instobj_dtor(struct nvkm_memory *memory) 95 { 96 struct nv04_instobj *iobj = nv04_instobj(memory); 97 mutex_lock(&iobj->imem->base.subdev.mutex); 98 nvkm_mm_free(&iobj->imem->heap, &iobj->node); 99 mutex_unlock(&iobj->imem->base.subdev.mutex); 100 return iobj; 101 } 102 103 static const struct nvkm_memory_func 104 nv04_instobj_func = { 105 .dtor = nv04_instobj_dtor, 106 .target = nv04_instobj_target, 107 .size = nv04_instobj_size, 108 .addr = nv04_instobj_addr, 109 .acquire = nv04_instobj_acquire, 110 .release = nv04_instobj_release, 111 .rd32 = nv04_instobj_rd32, 112 .wr32 = nv04_instobj_wr32, 113 }; 114 115 static int 116 nv04_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, 117 struct nvkm_memory **pmemory) 118 { 119 struct nv04_instmem *imem = nv04_instmem(base); 120 struct nv04_instobj *iobj; 121 int ret; 122 123 if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) 124 return -ENOMEM; 125 *pmemory = &iobj->memory; 126 127 nvkm_memory_ctor(&nv04_instobj_func, &iobj->memory); 128 iobj->imem = imem; 129 130 mutex_lock(&imem->base.subdev.mutex); 131 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, 132 align ? align : 1, &iobj->node); 133 mutex_unlock(&imem->base.subdev.mutex); 134 return ret; 135 } 136 137 /****************************************************************************** 138 * instmem subdev implementation 139 *****************************************************************************/ 140 141 static u32 142 nv04_instmem_rd32(struct nvkm_instmem *imem, u32 addr) 143 { 144 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); 145 } 146 147 static void 148 nv04_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data) 149 { 150 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); 151 } 152 153 static void 154 nv04_instmem_dtor(struct nvkm_object *object) 155 { 156 struct nv04_instmem *imem = (void *)object; 157 nvkm_memory_del(&imem->base.ramfc); 158 nvkm_memory_del(&imem->base.ramro); 159 nvkm_ramht_del(&imem->base.ramht); 160 nvkm_memory_del(&imem->base.vbios); 161 nvkm_mm_fini(&imem->heap); 162 nvkm_instmem_destroy(&imem->base); 163 } 164 165 static const struct nvkm_instmem_func 166 nv04_instmem_func = { 167 .rd32 = nv04_instmem_rd32, 168 .wr32 = nv04_instmem_wr32, 169 }; 170 171 static int 172 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 173 struct nvkm_oclass *oclass, void *data, u32 size, 174 struct nvkm_object **pobject) 175 { 176 struct nvkm_device *device = (void *)parent; 177 struct nv04_instmem *imem; 178 int ret; 179 180 ret = nvkm_instmem_create(parent, engine, oclass, &imem); 181 *pobject = nv_object(imem); 182 if (ret) 183 return ret; 184 185 imem->base.func = &nv04_instmem_func; 186 187 /* PRAMIN aperture maps over the end of VRAM, reserve it */ 188 imem->base.reserved = 512 * 1024; 189 190 ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1); 191 if (ret) 192 return ret; 193 194 /* 0x00000-0x10000: reserve for probable vbios image */ 195 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, 196 &imem->base.vbios); 197 if (ret) 198 return ret; 199 200 /* 0x10000-0x18000: reserve for RAMHT */ 201 ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); 202 if (ret) 203 return ret; 204 205 /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */ 206 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x00800, 0, true, 207 &imem->base.ramfc); 208 if (ret) 209 return ret; 210 211 /* 0x18800-0x18a00: reserve for RAMRO */ 212 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x00200, 0, false, 213 &imem->base.ramro); 214 if (ret) 215 return ret; 216 217 return 0; 218 } 219 220 struct nvkm_oclass * 221 nv04_instmem_oclass = &(struct nvkm_instmem_impl) { 222 .base.handle = NV_SUBDEV(INSTMEM, 0x04), 223 .base.ofuncs = &(struct nvkm_ofuncs) { 224 .ctor = nv04_instmem_ctor, 225 .dtor = nv04_instmem_dtor, 226 .init = _nvkm_instmem_init, 227 .fini = _nvkm_instmem_fini, 228 }, 229 .memory_new = nv04_instobj_new, 230 .persistent = false, 231 .zero = false, 232 }.base; 233