1 /*
2  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  */
22 
23 /*
24  * GK20A does not have dedicated video memory, and to accurately represent this
25  * fact Nouveau will not create a RAM device for it. Therefore its instmem
26  * implementation must be done directly on top of system memory, while providing
27  * coherent read and write operations.
28  *
29  * Instmem can be allocated through two means:
30  * 1) If an IOMMU mapping has been probed, the IOMMU API is used to make memory
31  *    pages contiguous to the GPU. This is the preferred way.
32  * 2) If no IOMMU mapping is probed, the DMA API is used to allocate physically
33  *    contiguous memory.
34  *
35  * In both cases CPU read and writes are performed using PRAMIN (i.e. using the
36  * GPU path) to ensure these operations are coherent for the GPU. This allows us
37  * to use more "relaxed" allocation parameters when using the DMA API, since we
38  * never need a kernel mapping.
39  */
40 
41 #include <subdev/fb.h>
42 #include <core/mm.h>
43 
44 #ifdef __KERNEL__
45 #include <linux/dma-attrs.h>
46 #include <linux/iommu.h>
47 #include <nouveau_platform.h>
48 #endif
49 
50 #include "priv.h"
51 
52 struct gk20a_instobj {
53 	struct nvkm_instobj base;
54 	/* Must be second member here - see nouveau_gpuobj_map_vm() */
55 	struct nvkm_mem *mem;
56 	/* Pointed by mem */
57 	struct nvkm_mem _mem;
58 };
59 
60 /*
61  * Used for objects allocated using the DMA API
62  */
63 struct gk20a_instobj_dma {
64 	struct gk20a_instobj base;
65 
66 	void *cpuaddr;
67 	dma_addr_t handle;
68 	struct nvkm_mm_node r;
69 };
70 
71 /*
72  * Used for objects flattened using the IOMMU API
73  */
74 struct gk20a_instobj_iommu {
75 	struct gk20a_instobj base;
76 
77 	/* array of base.mem->size pages */
78 	struct page *pages[];
79 };
80 
81 struct gk20a_instmem {
82 	struct nvkm_instmem base;
83 	spinlock_t lock;
84 	u64 addr;
85 
86 	/* Only used if IOMMU if present */
87 	struct mutex *mm_mutex;
88 	struct nvkm_mm *mm;
89 	struct iommu_domain *domain;
90 	unsigned long iommu_pgshift;
91 
92 	/* Only used by DMA API */
93 	struct dma_attrs attrs;
94 };
95 
96 /*
97  * Use PRAMIN to read/write data and avoid coherency issues.
98  * PRAMIN uses the GPU path and ensures data will always be coherent.
99  *
100  * A dynamic mapping based solution would be desirable in the future, but
101  * the issue remains of how to maintain coherency efficiently. On ARM it is
102  * not easy (if possible at all?) to create uncached temporary mappings.
103  */
104 
105 static u32
106 gk20a_instobj_rd32(struct nvkm_object *object, u64 offset)
107 {
108 	struct gk20a_instmem *imem = (void *)nvkm_instmem(object);
109 	struct gk20a_instobj *node = (void *)object;
110 	unsigned long flags;
111 	u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
112 	u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
113 	u32 data;
114 
115 	spin_lock_irqsave(&imem->lock, flags);
116 	if (unlikely(imem->addr != base)) {
117 		nv_wr32(imem, 0x001700, base >> 16);
118 		imem->addr = base;
119 	}
120 	data = nv_rd32(imem, 0x700000 + addr);
121 	spin_unlock_irqrestore(&imem->lock, flags);
122 	return data;
123 }
124 
125 static void
126 gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
127 {
128 	struct gk20a_instmem *imem = (void *)nvkm_instmem(object);
129 	struct gk20a_instobj *node = (void *)object;
130 	unsigned long flags;
131 	u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
132 	u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
133 
134 	spin_lock_irqsave(&imem->lock, flags);
135 	if (unlikely(imem->addr != base)) {
136 		nv_wr32(imem, 0x001700, base >> 16);
137 		imem->addr = base;
138 	}
139 	nv_wr32(imem, 0x700000 + addr, data);
140 	spin_unlock_irqrestore(&imem->lock, flags);
141 }
142 
143 static void
144 gk20a_instobj_dtor_dma(struct gk20a_instobj *_node)
145 {
146 	struct gk20a_instobj_dma *node = (void *)_node;
147 	struct gk20a_instmem *imem = (void *)nvkm_instmem(node);
148 	struct device *dev = nv_device_base(nv_device(imem));
149 
150 	if (unlikely(!node->cpuaddr))
151 		return;
152 
153 	dma_free_attrs(dev, _node->mem->size << PAGE_SHIFT, node->cpuaddr,
154 		       node->handle, &imem->attrs);
155 }
156 
157 static void
158 gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node)
159 {
160 	struct gk20a_instobj_iommu *node = (void *)_node;
161 	struct gk20a_instmem *imem = (void *)nvkm_instmem(node);
162 	struct nvkm_mm_node *r;
163 	int i;
164 
165 	if (unlikely(list_empty(&_node->mem->regions)))
166 		return;
167 
168 	r = list_first_entry(&_node->mem->regions, struct nvkm_mm_node,
169 			     rl_entry);
170 
171 	/* clear bit 34 to unmap pages */
172 	r->offset &= ~BIT(34 - imem->iommu_pgshift);
173 
174 	/* Unmap pages from GPU address space and free them */
175 	for (i = 0; i < _node->mem->size; i++) {
176 		iommu_unmap(imem->domain,
177 			    (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE);
178 		__free_page(node->pages[i]);
179 	}
180 
181 	/* Release area from GPU address space */
182 	mutex_lock(imem->mm_mutex);
183 	nvkm_mm_free(imem->mm, &r);
184 	mutex_unlock(imem->mm_mutex);
185 }
186 
187 static void
188 gk20a_instobj_dtor(struct nvkm_object *object)
189 {
190 	struct gk20a_instobj *node = (void *)object;
191 	struct gk20a_instmem *imem = (void *)nvkm_instmem(node);
192 
193 	if (imem->domain)
194 		gk20a_instobj_dtor_iommu(node);
195 	else
196 		gk20a_instobj_dtor_dma(node);
197 
198 	nvkm_instobj_destroy(&node->base);
199 }
200 
201 static int
202 gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
203 		       struct nvkm_oclass *oclass, u32 npages, u32 align,
204 		       struct gk20a_instobj **_node)
205 {
206 	struct gk20a_instobj_dma *node;
207 	struct gk20a_instmem *imem = (void *)nvkm_instmem(parent);
208 	struct device *dev = nv_device_base(nv_device(parent));
209 	int ret;
210 
211 	ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node),
212 				   (void **)&node);
213 	*_node = &node->base;
214 	if (ret)
215 		return ret;
216 
217 	node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT,
218 					&node->handle, GFP_KERNEL,
219 					&imem->attrs);
220 	if (!node->cpuaddr) {
221 		nv_error(imem, "cannot allocate DMA memory\n");
222 		return -ENOMEM;
223 	}
224 
225 	/* alignment check */
226 	if (unlikely(node->handle & (align - 1)))
227 		nv_warn(imem, "memory not aligned as requested: %pad (0x%x)\n",
228 			&node->handle, align);
229 
230 	/* present memory for being mapped using small pages */
231 	node->r.type = 12;
232 	node->r.offset = node->handle >> 12;
233 	node->r.length = (npages << PAGE_SHIFT) >> 12;
234 
235 	node->base._mem.offset = node->handle;
236 
237 	INIT_LIST_HEAD(&node->base._mem.regions);
238 	list_add_tail(&node->r.rl_entry, &node->base._mem.regions);
239 
240 	return 0;
241 }
242 
243 static int
244 gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine,
245 			 struct nvkm_oclass *oclass, u32 npages, u32 align,
246 			 struct gk20a_instobj **_node)
247 {
248 	struct gk20a_instobj_iommu *node;
249 	struct gk20a_instmem *imem = (void *)nvkm_instmem(parent);
250 	struct nvkm_mm_node *r;
251 	int ret;
252 	int i;
253 
254 	ret = nvkm_instobj_create_(parent, engine, oclass,
255 				sizeof(*node) + sizeof(node->pages[0]) * npages,
256 				(void **)&node);
257 	*_node = &node->base;
258 	if (ret)
259 		return ret;
260 
261 	/* Allocate backing memory */
262 	for (i = 0; i < npages; i++) {
263 		struct page *p = alloc_page(GFP_KERNEL);
264 
265 		if (p == NULL) {
266 			ret = -ENOMEM;
267 			goto free_pages;
268 		}
269 		node->pages[i] = p;
270 	}
271 
272 	mutex_lock(imem->mm_mutex);
273 	/* Reserve area from GPU address space */
274 	ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages,
275 			   align >> imem->iommu_pgshift, &r);
276 	mutex_unlock(imem->mm_mutex);
277 	if (ret) {
278 		nv_error(imem, "virtual space is full!\n");
279 		goto free_pages;
280 	}
281 
282 	/* Map into GPU address space */
283 	for (i = 0; i < npages; i++) {
284 		struct page *p = node->pages[i];
285 		u32 offset = (r->offset + i) << imem->iommu_pgshift;
286 
287 		ret = iommu_map(imem->domain, offset, page_to_phys(p),
288 				PAGE_SIZE, IOMMU_READ | IOMMU_WRITE);
289 		if (ret < 0) {
290 			nv_error(imem, "IOMMU mapping failure: %d\n", ret);
291 
292 			while (i-- > 0) {
293 				offset -= PAGE_SIZE;
294 				iommu_unmap(imem->domain, offset, PAGE_SIZE);
295 			}
296 			goto release_area;
297 		}
298 	}
299 
300 	/* Bit 34 tells that an address is to be resolved through the IOMMU */
301 	r->offset |= BIT(34 - imem->iommu_pgshift);
302 
303 	node->base._mem.offset = ((u64)r->offset) << imem->iommu_pgshift;
304 
305 	INIT_LIST_HEAD(&node->base._mem.regions);
306 	list_add_tail(&r->rl_entry, &node->base._mem.regions);
307 
308 	return 0;
309 
310 release_area:
311 	mutex_lock(imem->mm_mutex);
312 	nvkm_mm_free(imem->mm, &r);
313 	mutex_unlock(imem->mm_mutex);
314 
315 free_pages:
316 	for (i = 0; i < npages && node->pages[i] != NULL; i++)
317 		__free_page(node->pages[i]);
318 
319 	return ret;
320 }
321 
322 static int
323 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
324 		   struct nvkm_oclass *oclass, void *data, u32 _size,
325 		   struct nvkm_object **pobject)
326 {
327 	struct nvkm_instobj_args *args = data;
328 	struct gk20a_instmem *imem = (void *)nvkm_instmem(parent);
329 	struct gk20a_instobj *node;
330 	u32 size, align;
331 	int ret;
332 
333 	nv_debug(parent, "%s (%s): size: %x align: %x\n", __func__,
334 		 imem->domain ? "IOMMU" : "DMA", args->size, args->align);
335 
336 	/* Round size and align to page bounds */
337 	size = max(roundup(args->size, PAGE_SIZE), PAGE_SIZE);
338 	align = max(roundup(args->align, PAGE_SIZE), PAGE_SIZE);
339 
340 	if (imem->domain)
341 		ret = gk20a_instobj_ctor_iommu(parent, engine, oclass,
342 					      size >> PAGE_SHIFT, align, &node);
343 	else
344 		ret = gk20a_instobj_ctor_dma(parent, engine, oclass,
345 					     size >> PAGE_SHIFT, align, &node);
346 	*pobject = nv_object(node);
347 	if (ret)
348 		return ret;
349 
350 	node->mem = &node->_mem;
351 
352 	/* present memory for being mapped using small pages */
353 	node->mem->size = size >> 12;
354 	node->mem->memtype = 0;
355 	node->mem->page_shift = 12;
356 
357 	node->base.addr = node->mem->offset;
358 	node->base.size = size;
359 
360 	nv_debug(parent, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
361 		 size, align, node->mem->offset);
362 
363 	return 0;
364 }
365 
366 static struct nvkm_instobj_impl
367 gk20a_instobj_oclass = {
368 	.base.ofuncs = &(struct nvkm_ofuncs) {
369 		.ctor = gk20a_instobj_ctor,
370 		.dtor = gk20a_instobj_dtor,
371 		.init = _nvkm_instobj_init,
372 		.fini = _nvkm_instobj_fini,
373 		.rd32 = gk20a_instobj_rd32,
374 		.wr32 = gk20a_instobj_wr32,
375 	},
376 };
377 
378 
379 
380 static int
381 gk20a_instmem_fini(struct nvkm_object *object, bool suspend)
382 {
383 	struct gk20a_instmem *imem = (void *)object;
384 	imem->addr = ~0ULL;
385 	return nvkm_instmem_fini(&imem->base, suspend);
386 }
387 
388 static int
389 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
390 		   struct nvkm_oclass *oclass, void *data, u32 size,
391 		   struct nvkm_object **pobject)
392 {
393 	struct gk20a_instmem *imem;
394 	struct nouveau_platform_device *plat;
395 	int ret;
396 
397 	ret = nvkm_instmem_create(parent, engine, oclass, &imem);
398 	*pobject = nv_object(imem);
399 	if (ret)
400 		return ret;
401 
402 	spin_lock_init(&imem->lock);
403 
404 	plat = nv_device_to_platform(nv_device(parent));
405 	if (plat->gpu->iommu.domain) {
406 		imem->domain = plat->gpu->iommu.domain;
407 		imem->mm = plat->gpu->iommu.mm;
408 		imem->iommu_pgshift = plat->gpu->iommu.pgshift;
409 		imem->mm_mutex = &plat->gpu->iommu.mutex;
410 
411 		nv_info(imem, "using IOMMU\n");
412 	} else {
413 		init_dma_attrs(&imem->attrs);
414 		/*
415 		 * We will access instmem through PRAMIN and thus do not need a
416 		 * consistent CPU pointer or kernel mapping
417 		 */
418 		dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs);
419 		dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs);
420 		dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs);
421 		dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs);
422 
423 		nv_info(imem, "using DMA API\n");
424 	}
425 
426 	return 0;
427 }
428 
429 struct nvkm_oclass *
430 gk20a_instmem_oclass = &(struct nvkm_instmem_impl) {
431 	.base.handle = NV_SUBDEV(INSTMEM, 0xea),
432 	.base.ofuncs = &(struct nvkm_ofuncs) {
433 		.ctor = gk20a_instmem_ctor,
434 		.dtor = _nvkm_instmem_dtor,
435 		.init = _nvkm_instmem_init,
436 		.fini = gk20a_instmem_fini,
437 	},
438 	.instobj = &gk20a_instobj_oclass.base,
439 }.base;
440