1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* 24 * GK20A does not have dedicated video memory, and to accurately represent this 25 * fact Nouveau will not create a RAM device for it. Therefore its instmem 26 * implementation must be done directly on top of system memory, while providing 27 * coherent read and write operations. 28 * 29 * Instmem can be allocated through two means: 30 * 1) If an IOMMU mapping has been probed, the IOMMU API is used to make memory 31 * pages contiguous to the GPU. This is the preferred way. 32 * 2) If no IOMMU mapping is probed, the DMA API is used to allocate physically 33 * contiguous memory. 34 * 35 * In both cases CPU read and writes are performed using PRAMIN (i.e. using the 36 * GPU path) to ensure these operations are coherent for the GPU. This allows us 37 * to use more "relaxed" allocation parameters when using the DMA API, since we 38 * never need a kernel mapping. 39 */ 40 41 #include <subdev/fb.h> 42 #include <core/mm.h> 43 44 #ifdef __KERNEL__ 45 #include <linux/dma-attrs.h> 46 #include <linux/iommu.h> 47 #include <nouveau_platform.h> 48 #endif 49 50 #include "priv.h" 51 52 struct gk20a_instobj { 53 struct nvkm_instobj base; 54 /* Must be second member here - see nouveau_gpuobj_map_vm() */ 55 struct nvkm_mem *mem; 56 /* Pointed by mem */ 57 struct nvkm_mem _mem; 58 }; 59 60 /* 61 * Used for objects allocated using the DMA API 62 */ 63 struct gk20a_instobj_dma { 64 struct gk20a_instobj base; 65 66 void *cpuaddr; 67 dma_addr_t handle; 68 struct nvkm_mm_node r; 69 }; 70 71 /* 72 * Used for objects flattened using the IOMMU API 73 */ 74 struct gk20a_instobj_iommu { 75 struct gk20a_instobj base; 76 77 /* array of base.mem->size pages */ 78 struct page *pages[]; 79 }; 80 81 struct gk20a_instmem { 82 struct nvkm_instmem base; 83 spinlock_t lock; 84 u64 addr; 85 86 /* Only used if IOMMU if present */ 87 struct mutex *mm_mutex; 88 struct nvkm_mm *mm; 89 struct iommu_domain *domain; 90 unsigned long iommu_pgshift; 91 92 /* Only used by DMA API */ 93 struct dma_attrs attrs; 94 }; 95 96 /* 97 * Use PRAMIN to read/write data and avoid coherency issues. 98 * PRAMIN uses the GPU path and ensures data will always be coherent. 99 * 100 * A dynamic mapping based solution would be desirable in the future, but 101 * the issue remains of how to maintain coherency efficiently. On ARM it is 102 * not easy (if possible at all?) to create uncached temporary mappings. 103 */ 104 105 static u32 106 gk20a_instobj_rd32(struct nvkm_object *object, u64 offset) 107 { 108 struct gk20a_instmem *imem = (void *)nvkm_instmem(object); 109 struct gk20a_instobj *node = (void *)object; 110 struct nvkm_device *device = imem->base.subdev.device; 111 unsigned long flags; 112 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; 113 u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; 114 u32 data; 115 116 spin_lock_irqsave(&imem->lock, flags); 117 if (unlikely(imem->addr != base)) { 118 nvkm_wr32(device, 0x001700, base >> 16); 119 imem->addr = base; 120 } 121 data = nvkm_rd32(device, 0x700000 + addr); 122 spin_unlock_irqrestore(&imem->lock, flags); 123 return data; 124 } 125 126 static void 127 gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data) 128 { 129 struct gk20a_instmem *imem = (void *)nvkm_instmem(object); 130 struct gk20a_instobj *node = (void *)object; 131 struct nvkm_device *device = imem->base.subdev.device; 132 unsigned long flags; 133 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; 134 u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; 135 136 spin_lock_irqsave(&imem->lock, flags); 137 if (unlikely(imem->addr != base)) { 138 nvkm_wr32(device, 0x001700, base >> 16); 139 imem->addr = base; 140 } 141 nvkm_wr32(device, 0x700000 + addr, data); 142 spin_unlock_irqrestore(&imem->lock, flags); 143 } 144 145 static void 146 gk20a_instobj_dtor_dma(struct gk20a_instobj *_node) 147 { 148 struct gk20a_instobj_dma *node = (void *)_node; 149 struct gk20a_instmem *imem = (void *)nvkm_instmem(node); 150 struct device *dev = nv_device_base(nv_device(imem)); 151 152 if (unlikely(!node->cpuaddr)) 153 return; 154 155 dma_free_attrs(dev, _node->mem->size << PAGE_SHIFT, node->cpuaddr, 156 node->handle, &imem->attrs); 157 } 158 159 static void 160 gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node) 161 { 162 struct gk20a_instobj_iommu *node = (void *)_node; 163 struct gk20a_instmem *imem = (void *)nvkm_instmem(node); 164 struct nvkm_mm_node *r; 165 int i; 166 167 if (unlikely(list_empty(&_node->mem->regions))) 168 return; 169 170 r = list_first_entry(&_node->mem->regions, struct nvkm_mm_node, 171 rl_entry); 172 173 /* clear bit 34 to unmap pages */ 174 r->offset &= ~BIT(34 - imem->iommu_pgshift); 175 176 /* Unmap pages from GPU address space and free them */ 177 for (i = 0; i < _node->mem->size; i++) { 178 iommu_unmap(imem->domain, 179 (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE); 180 __free_page(node->pages[i]); 181 } 182 183 /* Release area from GPU address space */ 184 mutex_lock(imem->mm_mutex); 185 nvkm_mm_free(imem->mm, &r); 186 mutex_unlock(imem->mm_mutex); 187 } 188 189 static void 190 gk20a_instobj_dtor(struct nvkm_object *object) 191 { 192 struct gk20a_instobj *node = (void *)object; 193 struct gk20a_instmem *imem = (void *)nvkm_instmem(node); 194 195 if (imem->domain) 196 gk20a_instobj_dtor_iommu(node); 197 else 198 gk20a_instobj_dtor_dma(node); 199 200 nvkm_instobj_destroy(&node->base); 201 } 202 203 static int 204 gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, 205 struct nvkm_oclass *oclass, u32 npages, u32 align, 206 struct gk20a_instobj **_node) 207 { 208 struct gk20a_instobj_dma *node; 209 struct gk20a_instmem *imem = (void *)nvkm_instmem(parent); 210 struct nvkm_subdev *subdev = &imem->base.subdev; 211 struct device *dev = nv_device_base(nv_device(parent)); 212 int ret; 213 214 ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node), 215 (void **)&node); 216 *_node = &node->base; 217 if (ret) 218 return ret; 219 220 node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, 221 &node->handle, GFP_KERNEL, 222 &imem->attrs); 223 if (!node->cpuaddr) { 224 nvkm_error(subdev, "cannot allocate DMA memory\n"); 225 return -ENOMEM; 226 } 227 228 /* alignment check */ 229 if (unlikely(node->handle & (align - 1))) 230 nvkm_warn(subdev, 231 "memory not aligned as requested: %pad (0x%x)\n", 232 &node->handle, align); 233 234 /* present memory for being mapped using small pages */ 235 node->r.type = 12; 236 node->r.offset = node->handle >> 12; 237 node->r.length = (npages << PAGE_SHIFT) >> 12; 238 239 node->base._mem.offset = node->handle; 240 241 INIT_LIST_HEAD(&node->base._mem.regions); 242 list_add_tail(&node->r.rl_entry, &node->base._mem.regions); 243 244 return 0; 245 } 246 247 static int 248 gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine, 249 struct nvkm_oclass *oclass, u32 npages, u32 align, 250 struct gk20a_instobj **_node) 251 { 252 struct gk20a_instobj_iommu *node; 253 struct gk20a_instmem *imem = (void *)nvkm_instmem(parent); 254 struct nvkm_subdev *subdev = &imem->base.subdev; 255 struct nvkm_mm_node *r; 256 int ret; 257 int i; 258 259 ret = nvkm_instobj_create_(parent, engine, oclass, 260 sizeof(*node) + sizeof(node->pages[0]) * npages, 261 (void **)&node); 262 *_node = &node->base; 263 if (ret) 264 return ret; 265 266 /* Allocate backing memory */ 267 for (i = 0; i < npages; i++) { 268 struct page *p = alloc_page(GFP_KERNEL); 269 270 if (p == NULL) { 271 ret = -ENOMEM; 272 goto free_pages; 273 } 274 node->pages[i] = p; 275 } 276 277 mutex_lock(imem->mm_mutex); 278 /* Reserve area from GPU address space */ 279 ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages, 280 align >> imem->iommu_pgshift, &r); 281 mutex_unlock(imem->mm_mutex); 282 if (ret) { 283 nvkm_error(subdev, "virtual space is full!\n"); 284 goto free_pages; 285 } 286 287 /* Map into GPU address space */ 288 for (i = 0; i < npages; i++) { 289 struct page *p = node->pages[i]; 290 u32 offset = (r->offset + i) << imem->iommu_pgshift; 291 292 ret = iommu_map(imem->domain, offset, page_to_phys(p), 293 PAGE_SIZE, IOMMU_READ | IOMMU_WRITE); 294 if (ret < 0) { 295 nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret); 296 297 while (i-- > 0) { 298 offset -= PAGE_SIZE; 299 iommu_unmap(imem->domain, offset, PAGE_SIZE); 300 } 301 goto release_area; 302 } 303 } 304 305 /* Bit 34 tells that an address is to be resolved through the IOMMU */ 306 r->offset |= BIT(34 - imem->iommu_pgshift); 307 308 node->base._mem.offset = ((u64)r->offset) << imem->iommu_pgshift; 309 310 INIT_LIST_HEAD(&node->base._mem.regions); 311 list_add_tail(&r->rl_entry, &node->base._mem.regions); 312 313 return 0; 314 315 release_area: 316 mutex_lock(imem->mm_mutex); 317 nvkm_mm_free(imem->mm, &r); 318 mutex_unlock(imem->mm_mutex); 319 320 free_pages: 321 for (i = 0; i < npages && node->pages[i] != NULL; i++) 322 __free_page(node->pages[i]); 323 324 return ret; 325 } 326 327 static int 328 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 329 struct nvkm_oclass *oclass, void *data, u32 _size, 330 struct nvkm_object **pobject) 331 { 332 struct nvkm_instobj_args *args = data; 333 struct gk20a_instmem *imem = (void *)nvkm_instmem(parent); 334 struct gk20a_instobj *node; 335 struct nvkm_subdev *subdev = &imem->base.subdev; 336 u32 size, align; 337 int ret; 338 339 nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__, 340 imem->domain ? "IOMMU" : "DMA", args->size, args->align); 341 342 /* Round size and align to page bounds */ 343 size = max(roundup(args->size, PAGE_SIZE), PAGE_SIZE); 344 align = max(roundup(args->align, PAGE_SIZE), PAGE_SIZE); 345 346 if (imem->domain) 347 ret = gk20a_instobj_ctor_iommu(parent, engine, oclass, 348 size >> PAGE_SHIFT, align, &node); 349 else 350 ret = gk20a_instobj_ctor_dma(parent, engine, oclass, 351 size >> PAGE_SHIFT, align, &node); 352 *pobject = nv_object(node); 353 if (ret) 354 return ret; 355 356 node->mem = &node->_mem; 357 358 /* present memory for being mapped using small pages */ 359 node->mem->size = size >> 12; 360 node->mem->memtype = 0; 361 node->mem->page_shift = 12; 362 363 node->base.addr = node->mem->offset; 364 node->base.size = size; 365 366 nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n", 367 size, align, node->mem->offset); 368 369 return 0; 370 } 371 372 static struct nvkm_instobj_impl 373 gk20a_instobj_oclass = { 374 .base.ofuncs = &(struct nvkm_ofuncs) { 375 .ctor = gk20a_instobj_ctor, 376 .dtor = gk20a_instobj_dtor, 377 .init = _nvkm_instobj_init, 378 .fini = _nvkm_instobj_fini, 379 .rd32 = gk20a_instobj_rd32, 380 .wr32 = gk20a_instobj_wr32, 381 }, 382 }; 383 384 385 386 static int 387 gk20a_instmem_fini(struct nvkm_object *object, bool suspend) 388 { 389 struct gk20a_instmem *imem = (void *)object; 390 imem->addr = ~0ULL; 391 return nvkm_instmem_fini(&imem->base, suspend); 392 } 393 394 static int 395 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 396 struct nvkm_oclass *oclass, void *data, u32 size, 397 struct nvkm_object **pobject) 398 { 399 struct nvkm_device *device = (void *)parent; 400 struct gk20a_instmem *imem; 401 int ret; 402 403 ret = nvkm_instmem_create(parent, engine, oclass, &imem); 404 *pobject = nv_object(imem); 405 if (ret) 406 return ret; 407 408 spin_lock_init(&imem->lock); 409 410 if (device->gpu->iommu.domain) { 411 imem->domain = device->gpu->iommu.domain; 412 imem->mm = device->gpu->iommu.mm; 413 imem->iommu_pgshift = device->gpu->iommu.pgshift; 414 imem->mm_mutex = &device->gpu->iommu.mutex; 415 416 nvkm_info(&imem->base.subdev, "using IOMMU\n"); 417 } else { 418 init_dma_attrs(&imem->attrs); 419 /* 420 * We will access instmem through PRAMIN and thus do not need a 421 * consistent CPU pointer or kernel mapping 422 */ 423 dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); 424 dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); 425 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); 426 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs); 427 428 nvkm_info(&imem->base.subdev, "using DMA API\n"); 429 } 430 431 return 0; 432 } 433 434 struct nvkm_oclass * 435 gk20a_instmem_oclass = &(struct nvkm_instmem_impl) { 436 .base.handle = NV_SUBDEV(INSTMEM, 0xea), 437 .base.ofuncs = &(struct nvkm_ofuncs) { 438 .ctor = gk20a_instmem_ctor, 439 .dtor = _nvkm_instmem_dtor, 440 .init = _nvkm_instmem_init, 441 .fini = gk20a_instmem_fini, 442 }, 443 .instobj = &gk20a_instobj_oclass.base, 444 }.base; 445