1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* 24 * GK20A does not have dedicated video memory, and to accurately represent this 25 * fact Nouveau will not create a RAM device for it. Therefore its instmem 26 * implementation must be done directly on top of system memory, while 27 * preserving coherency for read and write operations. 28 * 29 * Instmem can be allocated through two means: 30 * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory 31 * pages contiguous to the GPU. This is the preferred way. 32 * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically 33 * contiguous memory. 34 * 35 * In both cases CPU read and writes are performed by creating a write-combined 36 * mapping. The GPU L2 cache must thus be flushed/invalidated when required. To 37 * be conservative we do this every time we acquire or release an instobj, but 38 * ideally L2 management should be handled at a higher level. 39 * 40 * To improve performance, CPU mappings are not removed upon instobj release. 41 * Instead they are placed into a LRU list to be recycled when the mapped space 42 * goes beyond a certain threshold. At the moment this limit is 1MB. 43 */ 44 #include "priv.h" 45 46 #include <core/memory.h> 47 #include <core/mm.h> 48 #include <core/tegra.h> 49 #include <subdev/fb.h> 50 #include <subdev/ltc.h> 51 52 struct gk20a_instobj { 53 struct nvkm_memory memory; 54 struct nvkm_mem mem; 55 struct gk20a_instmem *imem; 56 57 /* CPU mapping */ 58 u32 *vaddr; 59 }; 60 #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) 61 62 /* 63 * Used for objects allocated using the DMA API 64 */ 65 struct gk20a_instobj_dma { 66 struct gk20a_instobj base; 67 68 dma_addr_t handle; 69 struct nvkm_mm_node r; 70 }; 71 #define gk20a_instobj_dma(p) \ 72 container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base) 73 74 /* 75 * Used for objects flattened using the IOMMU API 76 */ 77 struct gk20a_instobj_iommu { 78 struct gk20a_instobj base; 79 80 /* to link into gk20a_instmem::vaddr_lru */ 81 struct list_head vaddr_node; 82 /* how many clients are using vaddr? */ 83 u32 use_cpt; 84 85 /* will point to the higher half of pages */ 86 dma_addr_t *dma_addrs; 87 /* array of base.mem->size pages (+ dma_addr_ts) */ 88 struct page *pages[]; 89 }; 90 #define gk20a_instobj_iommu(p) \ 91 container_of(gk20a_instobj(p), struct gk20a_instobj_iommu, base) 92 93 struct gk20a_instmem { 94 struct nvkm_instmem base; 95 96 /* protects vaddr_* and gk20a_instobj::vaddr* */ 97 spinlock_t lock; 98 99 /* CPU mappings LRU */ 100 unsigned int vaddr_use; 101 unsigned int vaddr_max; 102 struct list_head vaddr_lru; 103 104 /* Only used if IOMMU if present */ 105 struct mutex *mm_mutex; 106 struct nvkm_mm *mm; 107 struct iommu_domain *domain; 108 unsigned long iommu_pgshift; 109 u16 iommu_bit; 110 111 /* Only used by DMA API */ 112 unsigned long attrs; 113 }; 114 #define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base) 115 116 static enum nvkm_memory_target 117 gk20a_instobj_target(struct nvkm_memory *memory) 118 { 119 return NVKM_MEM_TARGET_HOST; 120 } 121 122 static u64 123 gk20a_instobj_addr(struct nvkm_memory *memory) 124 { 125 return gk20a_instobj(memory)->mem.offset; 126 } 127 128 static u64 129 gk20a_instobj_size(struct nvkm_memory *memory) 130 { 131 return (u64)gk20a_instobj(memory)->mem.size << 12; 132 } 133 134 /* 135 * Recycle the vaddr of obj. Must be called with gk20a_instmem::lock held. 136 */ 137 static void 138 gk20a_instobj_iommu_recycle_vaddr(struct gk20a_instobj_iommu *obj) 139 { 140 struct gk20a_instmem *imem = obj->base.imem; 141 /* there should not be any user left... */ 142 WARN_ON(obj->use_cpt); 143 list_del(&obj->vaddr_node); 144 vunmap(obj->base.vaddr); 145 obj->base.vaddr = NULL; 146 imem->vaddr_use -= nvkm_memory_size(&obj->base.memory); 147 nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use, 148 imem->vaddr_max); 149 } 150 151 /* 152 * Must be called while holding gk20a_instmem::lock 153 */ 154 static void 155 gk20a_instmem_vaddr_gc(struct gk20a_instmem *imem, const u64 size) 156 { 157 while (imem->vaddr_use + size > imem->vaddr_max) { 158 /* no candidate that can be unmapped, abort... */ 159 if (list_empty(&imem->vaddr_lru)) 160 break; 161 162 gk20a_instobj_iommu_recycle_vaddr( 163 list_first_entry(&imem->vaddr_lru, 164 struct gk20a_instobj_iommu, vaddr_node)); 165 } 166 } 167 168 static void __iomem * 169 gk20a_instobj_acquire_dma(struct nvkm_memory *memory) 170 { 171 struct gk20a_instobj *node = gk20a_instobj(memory); 172 struct gk20a_instmem *imem = node->imem; 173 struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; 174 175 nvkm_ltc_flush(ltc); 176 177 return node->vaddr; 178 } 179 180 static void __iomem * 181 gk20a_instobj_acquire_iommu(struct nvkm_memory *memory) 182 { 183 struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); 184 struct gk20a_instmem *imem = node->base.imem; 185 struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; 186 const u64 size = nvkm_memory_size(memory); 187 unsigned long flags; 188 189 nvkm_ltc_flush(ltc); 190 191 spin_lock_irqsave(&imem->lock, flags); 192 193 if (node->base.vaddr) { 194 if (!node->use_cpt) { 195 /* remove from LRU list since mapping in use again */ 196 list_del(&node->vaddr_node); 197 } 198 goto out; 199 } 200 201 /* try to free some address space if we reached the limit */ 202 gk20a_instmem_vaddr_gc(imem, size); 203 204 /* map the pages */ 205 node->base.vaddr = vmap(node->pages, size >> PAGE_SHIFT, VM_MAP, 206 pgprot_writecombine(PAGE_KERNEL)); 207 if (!node->base.vaddr) { 208 nvkm_error(&imem->base.subdev, "cannot map instobj - " 209 "this is not going to end well...\n"); 210 goto out; 211 } 212 213 imem->vaddr_use += size; 214 nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", 215 imem->vaddr_use, imem->vaddr_max); 216 217 out: 218 node->use_cpt++; 219 spin_unlock_irqrestore(&imem->lock, flags); 220 221 return node->base.vaddr; 222 } 223 224 static void 225 gk20a_instobj_release_dma(struct nvkm_memory *memory) 226 { 227 struct gk20a_instobj *node = gk20a_instobj(memory); 228 struct gk20a_instmem *imem = node->imem; 229 struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; 230 231 /* in case we got a write-combined mapping */ 232 wmb(); 233 nvkm_ltc_invalidate(ltc); 234 } 235 236 static void 237 gk20a_instobj_release_iommu(struct nvkm_memory *memory) 238 { 239 struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); 240 struct gk20a_instmem *imem = node->base.imem; 241 struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; 242 unsigned long flags; 243 244 spin_lock_irqsave(&imem->lock, flags); 245 246 /* we should at least have one user to release... */ 247 if (WARN_ON(node->use_cpt == 0)) 248 goto out; 249 250 /* add unused objs to the LRU list to recycle their mapping */ 251 if (--node->use_cpt == 0) 252 list_add_tail(&node->vaddr_node, &imem->vaddr_lru); 253 254 out: 255 spin_unlock_irqrestore(&imem->lock, flags); 256 257 wmb(); 258 nvkm_ltc_invalidate(ltc); 259 } 260 261 static u32 262 gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset) 263 { 264 struct gk20a_instobj *node = gk20a_instobj(memory); 265 266 return node->vaddr[offset / 4]; 267 } 268 269 static void 270 gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) 271 { 272 struct gk20a_instobj *node = gk20a_instobj(memory); 273 274 node->vaddr[offset / 4] = data; 275 } 276 277 static void 278 gk20a_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset) 279 { 280 struct gk20a_instobj *node = gk20a_instobj(memory); 281 282 nvkm_vm_map_at(vma, offset, &node->mem); 283 } 284 285 static void * 286 gk20a_instobj_dtor_dma(struct nvkm_memory *memory) 287 { 288 struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory); 289 struct gk20a_instmem *imem = node->base.imem; 290 struct device *dev = imem->base.subdev.device->dev; 291 292 if (unlikely(!node->base.vaddr)) 293 goto out; 294 295 dma_free_attrs(dev, node->base.mem.size << PAGE_SHIFT, node->base.vaddr, 296 node->handle, imem->attrs); 297 298 out: 299 return node; 300 } 301 302 static void * 303 gk20a_instobj_dtor_iommu(struct nvkm_memory *memory) 304 { 305 struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); 306 struct gk20a_instmem *imem = node->base.imem; 307 struct device *dev = imem->base.subdev.device->dev; 308 struct nvkm_mm_node *r; 309 unsigned long flags; 310 int i; 311 312 if (unlikely(list_empty(&node->base.mem.regions))) 313 goto out; 314 315 spin_lock_irqsave(&imem->lock, flags); 316 317 /* vaddr has already been recycled */ 318 if (node->base.vaddr) 319 gk20a_instobj_iommu_recycle_vaddr(node); 320 321 spin_unlock_irqrestore(&imem->lock, flags); 322 323 r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, 324 rl_entry); 325 326 /* clear IOMMU bit to unmap pages */ 327 r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift); 328 329 /* Unmap pages from GPU address space and free them */ 330 for (i = 0; i < node->base.mem.size; i++) { 331 iommu_unmap(imem->domain, 332 (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE); 333 dma_unmap_page(dev, node->dma_addrs[i], PAGE_SIZE, 334 DMA_BIDIRECTIONAL); 335 __free_page(node->pages[i]); 336 } 337 338 /* Release area from GPU address space */ 339 mutex_lock(imem->mm_mutex); 340 nvkm_mm_free(imem->mm, &r); 341 mutex_unlock(imem->mm_mutex); 342 343 out: 344 return node; 345 } 346 347 static const struct nvkm_memory_func 348 gk20a_instobj_func_dma = { 349 .dtor = gk20a_instobj_dtor_dma, 350 .target = gk20a_instobj_target, 351 .addr = gk20a_instobj_addr, 352 .size = gk20a_instobj_size, 353 .acquire = gk20a_instobj_acquire_dma, 354 .release = gk20a_instobj_release_dma, 355 .rd32 = gk20a_instobj_rd32, 356 .wr32 = gk20a_instobj_wr32, 357 .map = gk20a_instobj_map, 358 }; 359 360 static const struct nvkm_memory_func 361 gk20a_instobj_func_iommu = { 362 .dtor = gk20a_instobj_dtor_iommu, 363 .target = gk20a_instobj_target, 364 .addr = gk20a_instobj_addr, 365 .size = gk20a_instobj_size, 366 .acquire = gk20a_instobj_acquire_iommu, 367 .release = gk20a_instobj_release_iommu, 368 .rd32 = gk20a_instobj_rd32, 369 .wr32 = gk20a_instobj_wr32, 370 .map = gk20a_instobj_map, 371 }; 372 373 static int 374 gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align, 375 struct gk20a_instobj **_node) 376 { 377 struct gk20a_instobj_dma *node; 378 struct nvkm_subdev *subdev = &imem->base.subdev; 379 struct device *dev = subdev->device->dev; 380 381 if (!(node = kzalloc(sizeof(*node), GFP_KERNEL))) 382 return -ENOMEM; 383 *_node = &node->base; 384 385 nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory); 386 387 node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, 388 &node->handle, GFP_KERNEL, 389 imem->attrs); 390 if (!node->base.vaddr) { 391 nvkm_error(subdev, "cannot allocate DMA memory\n"); 392 return -ENOMEM; 393 } 394 395 /* alignment check */ 396 if (unlikely(node->handle & (align - 1))) 397 nvkm_warn(subdev, 398 "memory not aligned as requested: %pad (0x%x)\n", 399 &node->handle, align); 400 401 /* present memory for being mapped using small pages */ 402 node->r.type = 12; 403 node->r.offset = node->handle >> 12; 404 node->r.length = (npages << PAGE_SHIFT) >> 12; 405 406 node->base.mem.offset = node->handle; 407 408 INIT_LIST_HEAD(&node->base.mem.regions); 409 list_add_tail(&node->r.rl_entry, &node->base.mem.regions); 410 411 return 0; 412 } 413 414 static int 415 gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align, 416 struct gk20a_instobj **_node) 417 { 418 struct gk20a_instobj_iommu *node; 419 struct nvkm_subdev *subdev = &imem->base.subdev; 420 struct device *dev = subdev->device->dev; 421 struct nvkm_mm_node *r; 422 int ret; 423 int i; 424 425 /* 426 * despite their variable size, instmem allocations are small enough 427 * (< 1 page) to be handled by kzalloc 428 */ 429 if (!(node = kzalloc(sizeof(*node) + ((sizeof(node->pages[0]) + 430 sizeof(*node->dma_addrs)) * npages), GFP_KERNEL))) 431 return -ENOMEM; 432 *_node = &node->base; 433 node->dma_addrs = (void *)(node->pages + npages); 434 435 nvkm_memory_ctor(&gk20a_instobj_func_iommu, &node->base.memory); 436 437 /* Allocate backing memory */ 438 for (i = 0; i < npages; i++) { 439 struct page *p = alloc_page(GFP_KERNEL); 440 dma_addr_t dma_adr; 441 442 if (p == NULL) { 443 ret = -ENOMEM; 444 goto free_pages; 445 } 446 node->pages[i] = p; 447 dma_adr = dma_map_page(dev, p, 0, PAGE_SIZE, DMA_BIDIRECTIONAL); 448 if (dma_mapping_error(dev, dma_adr)) { 449 nvkm_error(subdev, "DMA mapping error!\n"); 450 ret = -ENOMEM; 451 goto free_pages; 452 } 453 node->dma_addrs[i] = dma_adr; 454 } 455 456 mutex_lock(imem->mm_mutex); 457 /* Reserve area from GPU address space */ 458 ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages, 459 align >> imem->iommu_pgshift, &r); 460 mutex_unlock(imem->mm_mutex); 461 if (ret) { 462 nvkm_error(subdev, "IOMMU space is full!\n"); 463 goto free_pages; 464 } 465 466 /* Map into GPU address space */ 467 for (i = 0; i < npages; i++) { 468 u32 offset = (r->offset + i) << imem->iommu_pgshift; 469 470 ret = iommu_map(imem->domain, offset, node->dma_addrs[i], 471 PAGE_SIZE, IOMMU_READ | IOMMU_WRITE); 472 if (ret < 0) { 473 nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret); 474 475 while (i-- > 0) { 476 offset -= PAGE_SIZE; 477 iommu_unmap(imem->domain, offset, PAGE_SIZE); 478 } 479 goto release_area; 480 } 481 } 482 483 /* IOMMU bit tells that an address is to be resolved through the IOMMU */ 484 r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift); 485 486 node->base.mem.offset = ((u64)r->offset) << imem->iommu_pgshift; 487 488 INIT_LIST_HEAD(&node->base.mem.regions); 489 list_add_tail(&r->rl_entry, &node->base.mem.regions); 490 491 return 0; 492 493 release_area: 494 mutex_lock(imem->mm_mutex); 495 nvkm_mm_free(imem->mm, &r); 496 mutex_unlock(imem->mm_mutex); 497 498 free_pages: 499 for (i = 0; i < npages && node->pages[i] != NULL; i++) { 500 dma_addr_t dma_addr = node->dma_addrs[i]; 501 if (dma_addr) 502 dma_unmap_page(dev, dma_addr, PAGE_SIZE, 503 DMA_BIDIRECTIONAL); 504 __free_page(node->pages[i]); 505 } 506 507 return ret; 508 } 509 510 static int 511 gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, 512 struct nvkm_memory **pmemory) 513 { 514 struct gk20a_instmem *imem = gk20a_instmem(base); 515 struct nvkm_subdev *subdev = &imem->base.subdev; 516 struct gk20a_instobj *node = NULL; 517 int ret; 518 519 nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__, 520 imem->domain ? "IOMMU" : "DMA", size, align); 521 522 /* Round size and align to page bounds */ 523 size = max(roundup(size, PAGE_SIZE), PAGE_SIZE); 524 align = max(roundup(align, PAGE_SIZE), PAGE_SIZE); 525 526 if (imem->domain) 527 ret = gk20a_instobj_ctor_iommu(imem, size >> PAGE_SHIFT, 528 align, &node); 529 else 530 ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT, 531 align, &node); 532 *pmemory = node ? &node->memory : NULL; 533 if (ret) 534 return ret; 535 536 node->imem = imem; 537 538 /* present memory for being mapped using small pages */ 539 node->mem.size = size >> 12; 540 node->mem.memtype = 0; 541 node->mem.page_shift = 12; 542 543 nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n", 544 size, align, node->mem.offset); 545 546 return 0; 547 } 548 549 static void * 550 gk20a_instmem_dtor(struct nvkm_instmem *base) 551 { 552 struct gk20a_instmem *imem = gk20a_instmem(base); 553 554 /* perform some sanity checks... */ 555 if (!list_empty(&imem->vaddr_lru)) 556 nvkm_warn(&base->subdev, "instobj LRU not empty!\n"); 557 558 if (imem->vaddr_use != 0) 559 nvkm_warn(&base->subdev, "instobj vmap area not empty! " 560 "0x%x bytes still mapped\n", imem->vaddr_use); 561 562 return imem; 563 } 564 565 static const struct nvkm_instmem_func 566 gk20a_instmem = { 567 .dtor = gk20a_instmem_dtor, 568 .memory_new = gk20a_instobj_new, 569 .persistent = true, 570 .zero = false, 571 }; 572 573 int 574 gk20a_instmem_new(struct nvkm_device *device, int index, 575 struct nvkm_instmem **pimem) 576 { 577 struct nvkm_device_tegra *tdev = device->func->tegra(device); 578 struct gk20a_instmem *imem; 579 580 if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) 581 return -ENOMEM; 582 nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); 583 spin_lock_init(&imem->lock); 584 *pimem = &imem->base; 585 586 /* do not allow more than 1MB of CPU-mapped instmem */ 587 imem->vaddr_use = 0; 588 imem->vaddr_max = 0x100000; 589 INIT_LIST_HEAD(&imem->vaddr_lru); 590 591 if (tdev->iommu.domain) { 592 imem->mm_mutex = &tdev->iommu.mutex; 593 imem->mm = &tdev->iommu.mm; 594 imem->domain = tdev->iommu.domain; 595 imem->iommu_pgshift = tdev->iommu.pgshift; 596 imem->iommu_bit = tdev->func->iommu_bit; 597 598 nvkm_info(&imem->base.subdev, "using IOMMU\n"); 599 } else { 600 imem->attrs = DMA_ATTR_NON_CONSISTENT | 601 DMA_ATTR_WEAK_ORDERING | 602 DMA_ATTR_WRITE_COMBINE; 603 604 nvkm_info(&imem->base.subdev, "using DMA API\n"); 605 } 606 607 return 0; 608 } 609