1 /*
2  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  */
22 
23 /*
24  * GK20A does not have dedicated video memory, and to accurately represent this
25  * fact Nouveau will not create a RAM device for it. Therefore its instmem
26  * implementation must be done directly on top of system memory, while providing
27  * coherent read and write operations.
28  *
29  * Instmem can be allocated through two means:
30  * 1) If an IOMMU mapping has been probed, the IOMMU API is used to make memory
31  *    pages contiguous to the GPU. This is the preferred way.
32  * 2) If no IOMMU mapping is probed, the DMA API is used to allocate physically
33  *    contiguous memory.
34  *
35  * In both cases CPU read and writes are performed using PRAMIN (i.e. using the
36  * GPU path) to ensure these operations are coherent for the GPU. This allows us
37  * to use more "relaxed" allocation parameters when using the DMA API, since we
38  * never need a kernel mapping.
39  */
40 #define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base)
41 #include "priv.h"
42 
43 #include <core/memory.h>
44 #include <core/mm.h>
45 #include <subdev/fb.h>
46 
47 #ifdef __KERNEL__
48 #include <linux/dma-attrs.h>
49 #include <linux/iommu.h>
50 #include <nouveau_platform.h>
51 #endif
52 
53 #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory)
54 
55 struct gk20a_instobj {
56 	struct nvkm_memory memory;
57 	struct gk20a_instmem *imem;
58 	struct nvkm_mem mem;
59 };
60 
61 /*
62  * Used for objects allocated using the DMA API
63  */
64 struct gk20a_instobj_dma {
65 	struct gk20a_instobj base;
66 
67 	void *cpuaddr;
68 	dma_addr_t handle;
69 	struct nvkm_mm_node r;
70 };
71 
72 /*
73  * Used for objects flattened using the IOMMU API
74  */
75 struct gk20a_instobj_iommu {
76 	struct gk20a_instobj base;
77 
78 	/* array of base.mem->size pages */
79 	struct page *pages[];
80 };
81 
82 struct gk20a_instmem {
83 	struct nvkm_instmem base;
84 	unsigned long lock_flags;
85 	spinlock_t lock;
86 	u64 addr;
87 
88 	/* Only used if IOMMU if present */
89 	struct mutex *mm_mutex;
90 	struct nvkm_mm *mm;
91 	struct iommu_domain *domain;
92 	unsigned long iommu_pgshift;
93 
94 	/* Only used by DMA API */
95 	struct dma_attrs attrs;
96 };
97 
98 static enum nvkm_memory_target
99 gk20a_instobj_target(struct nvkm_memory *memory)
100 {
101 	return NVKM_MEM_TARGET_HOST;
102 }
103 
104 static u64
105 gk20a_instobj_addr(struct nvkm_memory *memory)
106 {
107 	return gk20a_instobj(memory)->mem.offset;
108 
109 }
110 
111 static u64
112 gk20a_instobj_size(struct nvkm_memory *memory)
113 {
114 	return (u64)gk20a_instobj(memory)->mem.size << 12;
115 }
116 
117 static void __iomem *
118 gk20a_instobj_acquire(struct nvkm_memory *memory)
119 {
120 	struct gk20a_instmem *imem = gk20a_instobj(memory)->imem;
121 	unsigned long flags;
122 	spin_lock_irqsave(&imem->lock, flags);
123 	imem->lock_flags = flags;
124 	return NULL;
125 }
126 
127 static void
128 gk20a_instobj_release(struct nvkm_memory *memory)
129 {
130 	struct gk20a_instmem *imem = gk20a_instobj(memory)->imem;
131 	spin_unlock_irqrestore(&imem->lock, imem->lock_flags);
132 }
133 
134 /*
135  * Use PRAMIN to read/write data and avoid coherency issues.
136  * PRAMIN uses the GPU path and ensures data will always be coherent.
137  *
138  * A dynamic mapping based solution would be desirable in the future, but
139  * the issue remains of how to maintain coherency efficiently. On ARM it is
140  * not easy (if possible at all?) to create uncached temporary mappings.
141  */
142 
143 static u32
144 gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset)
145 {
146 	struct gk20a_instobj *node = gk20a_instobj(memory);
147 	struct gk20a_instmem *imem = node->imem;
148 	struct nvkm_device *device = imem->base.subdev.device;
149 	u64 base = (node->mem.offset + offset) & 0xffffff00000ULL;
150 	u64 addr = (node->mem.offset + offset) & 0x000000fffffULL;
151 	u32 data;
152 
153 	if (unlikely(imem->addr != base)) {
154 		nvkm_wr32(device, 0x001700, base >> 16);
155 		imem->addr = base;
156 	}
157 	data = nvkm_rd32(device, 0x700000 + addr);
158 	return data;
159 }
160 
161 static void
162 gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data)
163 {
164 	struct gk20a_instobj *node = gk20a_instobj(memory);
165 	struct gk20a_instmem *imem = node->imem;
166 	struct nvkm_device *device = imem->base.subdev.device;
167 	u64 base = (node->mem.offset + offset) & 0xffffff00000ULL;
168 	u64 addr = (node->mem.offset + offset) & 0x000000fffffULL;
169 
170 	if (unlikely(imem->addr != base)) {
171 		nvkm_wr32(device, 0x001700, base >> 16);
172 		imem->addr = base;
173 	}
174 	nvkm_wr32(device, 0x700000 + addr, data);
175 }
176 
177 static void
178 gk20a_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset)
179 {
180 	struct gk20a_instobj *node = gk20a_instobj(memory);
181 	nvkm_vm_map_at(vma, offset, &node->mem);
182 }
183 
184 static void
185 gk20a_instobj_dtor_dma(struct gk20a_instobj *_node)
186 {
187 	struct gk20a_instobj_dma *node = (void *)_node;
188 	struct gk20a_instmem *imem = _node->imem;
189 	struct device *dev = nv_device_base(nv_device(imem));
190 
191 	if (unlikely(!node->cpuaddr))
192 		return;
193 
194 	dma_free_attrs(dev, _node->mem.size << PAGE_SHIFT, node->cpuaddr,
195 		       node->handle, &imem->attrs);
196 }
197 
198 static void
199 gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node)
200 {
201 	struct gk20a_instobj_iommu *node = (void *)_node;
202 	struct gk20a_instmem *imem = _node->imem;
203 	struct nvkm_mm_node *r;
204 	int i;
205 
206 	if (unlikely(list_empty(&_node->mem.regions)))
207 		return;
208 
209 	r = list_first_entry(&_node->mem.regions, struct nvkm_mm_node,
210 			     rl_entry);
211 
212 	/* clear bit 34 to unmap pages */
213 	r->offset &= ~BIT(34 - imem->iommu_pgshift);
214 
215 	/* Unmap pages from GPU address space and free them */
216 	for (i = 0; i < _node->mem.size; i++) {
217 		iommu_unmap(imem->domain,
218 			    (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE);
219 		__free_page(node->pages[i]);
220 	}
221 
222 	/* Release area from GPU address space */
223 	mutex_lock(imem->mm_mutex);
224 	nvkm_mm_free(imem->mm, &r);
225 	mutex_unlock(imem->mm_mutex);
226 }
227 
228 static void *
229 gk20a_instobj_dtor(struct nvkm_memory *memory)
230 {
231 	struct gk20a_instobj *node = gk20a_instobj(memory);
232 	struct gk20a_instmem *imem = node->imem;
233 
234 	if (imem->domain)
235 		gk20a_instobj_dtor_iommu(node);
236 	else
237 		gk20a_instobj_dtor_dma(node);
238 
239 	return node;
240 }
241 
242 static const struct nvkm_memory_func
243 gk20a_instobj_func = {
244 	.dtor = gk20a_instobj_dtor,
245 	.target = gk20a_instobj_target,
246 	.addr = gk20a_instobj_addr,
247 	.size = gk20a_instobj_size,
248 	.acquire = gk20a_instobj_acquire,
249 	.release = gk20a_instobj_release,
250 	.rd32 = gk20a_instobj_rd32,
251 	.wr32 = gk20a_instobj_wr32,
252 	.map = gk20a_instobj_map,
253 };
254 
255 static int
256 gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align,
257 		       struct gk20a_instobj **_node)
258 {
259 	struct gk20a_instobj_dma *node;
260 	struct nvkm_subdev *subdev = &imem->base.subdev;
261 	struct device *dev = subdev->device->dev;
262 
263 	if (!(node = kzalloc(sizeof(*node), GFP_KERNEL)))
264 		return -ENOMEM;
265 	*_node = &node->base;
266 
267 	node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT,
268 					&node->handle, GFP_KERNEL,
269 					&imem->attrs);
270 	if (!node->cpuaddr) {
271 		nvkm_error(subdev, "cannot allocate DMA memory\n");
272 		return -ENOMEM;
273 	}
274 
275 	/* alignment check */
276 	if (unlikely(node->handle & (align - 1)))
277 		nvkm_warn(subdev,
278 			  "memory not aligned as requested: %pad (0x%x)\n",
279 			  &node->handle, align);
280 
281 	/* present memory for being mapped using small pages */
282 	node->r.type = 12;
283 	node->r.offset = node->handle >> 12;
284 	node->r.length = (npages << PAGE_SHIFT) >> 12;
285 
286 	node->base.mem.offset = node->handle;
287 
288 	INIT_LIST_HEAD(&node->base.mem.regions);
289 	list_add_tail(&node->r.rl_entry, &node->base.mem.regions);
290 
291 	return 0;
292 }
293 
294 static int
295 gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align,
296 			 struct gk20a_instobj **_node)
297 {
298 	struct gk20a_instobj_iommu *node;
299 	struct nvkm_subdev *subdev = &imem->base.subdev;
300 	struct nvkm_mm_node *r;
301 	int ret;
302 	int i;
303 
304 	if (!(node = kzalloc(sizeof(*node) +
305 			     sizeof( node->pages[0]) * npages, GFP_KERNEL)))
306 		return -ENOMEM;
307 	*_node = &node->base;
308 
309 	/* Allocate backing memory */
310 	for (i = 0; i < npages; i++) {
311 		struct page *p = alloc_page(GFP_KERNEL);
312 
313 		if (p == NULL) {
314 			ret = -ENOMEM;
315 			goto free_pages;
316 		}
317 		node->pages[i] = p;
318 	}
319 
320 	mutex_lock(imem->mm_mutex);
321 	/* Reserve area from GPU address space */
322 	ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages,
323 			   align >> imem->iommu_pgshift, &r);
324 	mutex_unlock(imem->mm_mutex);
325 	if (ret) {
326 		nvkm_error(subdev, "virtual space is full!\n");
327 		goto free_pages;
328 	}
329 
330 	/* Map into GPU address space */
331 	for (i = 0; i < npages; i++) {
332 		struct page *p = node->pages[i];
333 		u32 offset = (r->offset + i) << imem->iommu_pgshift;
334 
335 		ret = iommu_map(imem->domain, offset, page_to_phys(p),
336 				PAGE_SIZE, IOMMU_READ | IOMMU_WRITE);
337 		if (ret < 0) {
338 			nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret);
339 
340 			while (i-- > 0) {
341 				offset -= PAGE_SIZE;
342 				iommu_unmap(imem->domain, offset, PAGE_SIZE);
343 			}
344 			goto release_area;
345 		}
346 	}
347 
348 	/* Bit 34 tells that an address is to be resolved through the IOMMU */
349 	r->offset |= BIT(34 - imem->iommu_pgshift);
350 
351 	node->base.mem.offset = ((u64)r->offset) << imem->iommu_pgshift;
352 
353 	INIT_LIST_HEAD(&node->base.mem.regions);
354 	list_add_tail(&r->rl_entry, &node->base.mem.regions);
355 
356 	return 0;
357 
358 release_area:
359 	mutex_lock(imem->mm_mutex);
360 	nvkm_mm_free(imem->mm, &r);
361 	mutex_unlock(imem->mm_mutex);
362 
363 free_pages:
364 	for (i = 0; i < npages && node->pages[i] != NULL; i++)
365 		__free_page(node->pages[i]);
366 
367 	return ret;
368 }
369 
370 static int
371 gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
372 		  struct nvkm_memory **pmemory)
373 {
374 	struct gk20a_instmem *imem = gk20a_instmem(base);
375 	struct gk20a_instobj *node;
376 	struct nvkm_subdev *subdev = &imem->base.subdev;
377 	int ret;
378 
379 	nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__,
380 		   imem->domain ? "IOMMU" : "DMA", size, align);
381 
382 	/* Round size and align to page bounds */
383 	size = max(roundup(size, PAGE_SIZE), PAGE_SIZE);
384 	align = max(roundup(align, PAGE_SIZE), PAGE_SIZE);
385 
386 	if (imem->domain)
387 		ret = gk20a_instobj_ctor_iommu(imem, size >> PAGE_SHIFT,
388 					       align, &node);
389 	else
390 		ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT,
391 					     align, &node);
392 	if (ret)
393 		return ret;
394 	*pmemory = &node->memory;
395 
396 	nvkm_memory_ctor(&gk20a_instobj_func, &node->memory);
397 	node->imem = imem;
398 
399 	/* present memory for being mapped using small pages */
400 	node->mem.size = size >> 12;
401 	node->mem.memtype = 0;
402 	node->mem.page_shift = 12;
403 
404 	nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
405 		   size, align, node->mem.offset);
406 
407 	return 0;
408 }
409 
410 static int
411 gk20a_instmem_fini(struct nvkm_object *object, bool suspend)
412 {
413 	struct gk20a_instmem *imem = (void *)object;
414 	imem->addr = ~0ULL;
415 	return nvkm_instmem_fini(&imem->base, suspend);
416 }
417 
418 static int
419 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
420 		   struct nvkm_oclass *oclass, void *data, u32 size,
421 		   struct nvkm_object **pobject)
422 {
423 	struct nvkm_device *device = (void *)parent;
424 	struct gk20a_instmem *imem;
425 	int ret;
426 
427 	ret = nvkm_instmem_create(parent, engine, oclass, &imem);
428 	*pobject = nv_object(imem);
429 	if (ret)
430 		return ret;
431 
432 	spin_lock_init(&imem->lock);
433 
434 	if (device->gpu->iommu.domain) {
435 		imem->domain = device->gpu->iommu.domain;
436 		imem->mm = device->gpu->iommu.mm;
437 		imem->iommu_pgshift = device->gpu->iommu.pgshift;
438 		imem->mm_mutex = &device->gpu->iommu.mutex;
439 
440 		nvkm_info(&imem->base.subdev, "using IOMMU\n");
441 	} else {
442 		init_dma_attrs(&imem->attrs);
443 		/*
444 		 * We will access instmem through PRAMIN and thus do not need a
445 		 * consistent CPU pointer or kernel mapping
446 		 */
447 		dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs);
448 		dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs);
449 		dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs);
450 		dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs);
451 
452 		nvkm_info(&imem->base.subdev, "using DMA API\n");
453 	}
454 
455 	return 0;
456 }
457 
458 struct nvkm_oclass *
459 gk20a_instmem_oclass = &(struct nvkm_instmem_impl) {
460 	.base.handle = NV_SUBDEV(INSTMEM, 0xea),
461 	.base.ofuncs = &(struct nvkm_ofuncs) {
462 		.ctor = gk20a_instmem_ctor,
463 		.dtor = _nvkm_instmem_dtor,
464 		.init = _nvkm_instmem_init,
465 		.fini = gk20a_instmem_fini,
466 	},
467 	.memory_new = gk20a_instobj_new,
468 	.persistent = true,
469 	.zero = false,
470 }.base;
471