1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 void 27 g94_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) 28 { 29 struct nvkm_device *device = i2c->subdev.device; 30 u32 intr = nvkm_rd32(device, 0x00e06c); 31 u32 stat = nvkm_rd32(device, 0x00e068) & intr, i; 32 for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) { 33 if ((stat & (1 << (i * 4)))) *hi |= 1 << i; 34 if ((stat & (2 << (i * 4)))) *lo |= 1 << i; 35 if ((stat & (4 << (i * 4)))) *rq |= 1 << i; 36 if ((stat & (8 << (i * 4)))) *tx |= 1 << i; 37 } 38 nvkm_wr32(device, 0x00e06c, intr); 39 } 40 41 void 42 g94_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data) 43 { 44 struct nvkm_device *device = i2c->subdev.device; 45 u32 temp = nvkm_rd32(device, 0x00e068), i; 46 for (i = 0; i < 8; i++) { 47 if (mask & (1 << i)) { 48 if (!(data & (1 << i))) { 49 temp &= ~(type << (i * 4)); 50 continue; 51 } 52 temp |= type << (i * 4); 53 } 54 } 55 nvkm_wr32(device, 0x00e068, temp); 56 } 57 58 #define AUX_DBG(fmt, args...) nv_debug(i2c, "AUXCH(%d): " fmt, ch, ##args) 59 #define AUX_ERR(fmt, args...) nv_error(i2c, "AUXCH(%d): " fmt, ch, ##args) 60 61 static void 62 auxch_fini(struct nvkm_i2c *i2c, int ch) 63 { 64 struct nvkm_device *device = i2c->subdev.device; 65 nvkm_mask(device, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000); 66 } 67 68 static int 69 auxch_init(struct nvkm_i2c *i2c, int ch) 70 { 71 struct nvkm_device *device = i2c->subdev.device; 72 const u32 unksel = 1; /* nfi which to use, or if it matters.. */ 73 const u32 ureq = unksel ? 0x00100000 : 0x00200000; 74 const u32 urep = unksel ? 0x01000000 : 0x02000000; 75 u32 ctrl, timeout; 76 77 /* wait up to 1ms for any previous transaction to be done... */ 78 timeout = 1000; 79 do { 80 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 81 udelay(1); 82 if (!timeout--) { 83 AUX_ERR("begin idle timeout 0x%08x\n", ctrl); 84 return -EBUSY; 85 } 86 } while (ctrl & 0x03010000); 87 88 /* set some magic, and wait up to 1ms for it to appear */ 89 nvkm_mask(device, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq); 90 timeout = 1000; 91 do { 92 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 93 udelay(1); 94 if (!timeout--) { 95 AUX_ERR("magic wait 0x%08x\n", ctrl); 96 auxch_fini(i2c, ch); 97 return -EBUSY; 98 } 99 } while ((ctrl & 0x03000000) != urep); 100 101 return 0; 102 } 103 104 int 105 g94_aux(struct nvkm_i2c_port *base, bool retry, 106 u8 type, u32 addr, u8 *data, u8 size) 107 { 108 struct nvkm_i2c *i2c = nvkm_i2c(base); 109 struct nvkm_device *device = i2c->subdev.device; 110 struct nv50_i2c_port *port = (void *)base; 111 u32 ctrl, stat, timeout, retries; 112 u32 xbuf[4] = {}; 113 int ch = port->addr; 114 int ret, i; 115 116 AUX_DBG("%d: 0x%08x %d\n", type, addr, size); 117 118 ret = auxch_init(i2c, ch); 119 if (ret < 0) 120 goto out; 121 122 stat = nvkm_rd32(device, 0x00e4e8 + (ch * 0x50)); 123 if (!(stat & 0x10000000)) { 124 AUX_DBG("sink not detected\n"); 125 ret = -ENXIO; 126 goto out; 127 } 128 129 if (!(type & 1)) { 130 memcpy(xbuf, data, size); 131 for (i = 0; i < 16; i += 4) { 132 AUX_DBG("wr 0x%08x\n", xbuf[i / 4]); 133 nvkm_wr32(device, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]); 134 } 135 } 136 137 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 138 ctrl &= ~0x0001f0ff; 139 ctrl |= type << 12; 140 ctrl |= size - 1; 141 nvkm_wr32(device, 0x00e4e0 + (ch * 0x50), addr); 142 143 /* (maybe) retry transaction a number of times on failure... */ 144 for (retries = 0; !ret && retries < 32; retries++) { 145 /* reset, and delay a while if this is a retry */ 146 nvkm_wr32(device, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl); 147 nvkm_wr32(device, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl); 148 if (retries) 149 udelay(400); 150 151 /* transaction request, wait up to 1ms for it to complete */ 152 nvkm_wr32(device, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl); 153 154 timeout = 1000; 155 do { 156 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 157 udelay(1); 158 if (!timeout--) { 159 AUX_ERR("tx req timeout 0x%08x\n", ctrl); 160 ret = -EIO; 161 goto out; 162 } 163 } while (ctrl & 0x00010000); 164 ret = 1; 165 166 /* read status, and check if transaction completed ok */ 167 stat = nvkm_mask(device, 0x00e4e8 + (ch * 0x50), 0, 0); 168 if ((stat & 0x000f0000) == 0x00080000 || 169 (stat & 0x000f0000) == 0x00020000) 170 ret = retry ? 0 : 1; 171 if ((stat & 0x00000100)) 172 ret = -ETIMEDOUT; 173 if ((stat & 0x00000e00)) 174 ret = -EIO; 175 176 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat); 177 } 178 179 if (type & 1) { 180 for (i = 0; i < 16; i += 4) { 181 xbuf[i / 4] = nvkm_rd32(device, 0x00e4d0 + (ch * 0x50) + i); 182 AUX_DBG("rd 0x%08x\n", xbuf[i / 4]); 183 } 184 memcpy(data, xbuf, size); 185 } 186 187 out: 188 auxch_fini(i2c, ch); 189 return ret < 0 ? ret : (stat & 0x000f0000) >> 16; 190 } 191 192 static const struct nvkm_i2c_func 193 g94_i2c_func = { 194 .drive_scl = nv50_i2c_drive_scl, 195 .drive_sda = nv50_i2c_drive_sda, 196 .sense_scl = nv50_i2c_sense_scl, 197 .sense_sda = nv50_i2c_sense_sda, 198 }; 199 200 static int 201 g94_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 202 struct nvkm_oclass *oclass, void *data, u32 index, 203 struct nvkm_object **pobject) 204 { 205 struct dcb_i2c_entry *info = data; 206 struct nv50_i2c_port *port; 207 int ret; 208 209 ret = nvkm_i2c_port_create(parent, engine, oclass, index, 210 &nvkm_i2c_bit_algo, &g94_i2c_func, &port); 211 *pobject = nv_object(port); 212 if (ret) 213 return ret; 214 215 if (info->drive >= nv50_i2c_addr_nr) 216 return -EINVAL; 217 218 port->state = 7; 219 port->addr = nv50_i2c_addr[info->drive]; 220 return 0; 221 } 222 223 static const struct nvkm_i2c_func 224 g94_aux_func = { 225 .aux = g94_aux, 226 }; 227 228 int 229 g94_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 230 struct nvkm_oclass *oclass, void *data, u32 index, 231 struct nvkm_object **pobject) 232 { 233 struct dcb_i2c_entry *info = data; 234 struct nv50_i2c_port *port; 235 int ret; 236 237 ret = nvkm_i2c_port_create(parent, engine, oclass, index, 238 &nvkm_i2c_aux_algo, &g94_aux_func, &port); 239 *pobject = nv_object(port); 240 if (ret) 241 return ret; 242 243 port->base.aux = info->auxch; 244 port->addr = info->auxch; 245 return 0; 246 } 247 248 static struct nvkm_oclass 249 g94_i2c_sclass[] = { 250 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), 251 .ofuncs = &(struct nvkm_ofuncs) { 252 .ctor = g94_i2c_port_ctor, 253 .dtor = _nvkm_i2c_port_dtor, 254 .init = nv50_i2c_port_init, 255 .fini = _nvkm_i2c_port_fini, 256 }, 257 }, 258 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), 259 .ofuncs = &(struct nvkm_ofuncs) { 260 .ctor = g94_aux_port_ctor, 261 .dtor = _nvkm_i2c_port_dtor, 262 .init = _nvkm_i2c_port_init, 263 .fini = _nvkm_i2c_port_fini, 264 }, 265 }, 266 {} 267 }; 268 269 struct nvkm_oclass * 270 g94_i2c_oclass = &(struct nvkm_i2c_impl) { 271 .base.handle = NV_SUBDEV(I2C, 0x94), 272 .base.ofuncs = &(struct nvkm_ofuncs) { 273 .ctor = _nvkm_i2c_ctor, 274 .dtor = _nvkm_i2c_dtor, 275 .init = _nvkm_i2c_init, 276 .fini = _nvkm_i2c_fini, 277 }, 278 .sclass = g94_i2c_sclass, 279 .pad_x = &nv04_i2c_pad_oclass, 280 .pad_s = &g94_i2c_pad_oclass, 281 .aux = 4, 282 .aux_stat = g94_aux_stat, 283 .aux_mask = g94_aux_mask, 284 }.base; 285