1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 void 27 g94_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) 28 { 29 struct nvkm_device *device = i2c->subdev.device; 30 u32 intr = nvkm_rd32(device, 0x00e06c); 31 u32 stat = nvkm_rd32(device, 0x00e068) & intr, i; 32 for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) { 33 if ((stat & (1 << (i * 4)))) *hi |= 1 << i; 34 if ((stat & (2 << (i * 4)))) *lo |= 1 << i; 35 if ((stat & (4 << (i * 4)))) *rq |= 1 << i; 36 if ((stat & (8 << (i * 4)))) *tx |= 1 << i; 37 } 38 nvkm_wr32(device, 0x00e06c, intr); 39 } 40 41 void 42 g94_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data) 43 { 44 struct nvkm_device *device = i2c->subdev.device; 45 u32 temp = nvkm_rd32(device, 0x00e068), i; 46 for (i = 0; i < 8; i++) { 47 if (mask & (1 << i)) { 48 if (!(data & (1 << i))) { 49 temp &= ~(type << (i * 4)); 50 continue; 51 } 52 temp |= type << (i * 4); 53 } 54 } 55 nvkm_wr32(device, 0x00e068, temp); 56 } 57 58 #define AUX_DBG(fmt, args...) \ 59 nvkm_debug(&i2c->subdev, "AUXCH(%d): " fmt, ch, ##args) 60 #define AUX_ERR(fmt, args...) \ 61 nvkm_error(&i2c->subdev, "AUXCH(%d): " fmt, ch, ##args) 62 63 static void 64 auxch_fini(struct nvkm_i2c *i2c, int ch) 65 { 66 struct nvkm_device *device = i2c->subdev.device; 67 nvkm_mask(device, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000); 68 } 69 70 static int 71 auxch_init(struct nvkm_i2c *i2c, int ch) 72 { 73 struct nvkm_device *device = i2c->subdev.device; 74 const u32 unksel = 1; /* nfi which to use, or if it matters.. */ 75 const u32 ureq = unksel ? 0x00100000 : 0x00200000; 76 const u32 urep = unksel ? 0x01000000 : 0x02000000; 77 u32 ctrl, timeout; 78 79 /* wait up to 1ms for any previous transaction to be done... */ 80 timeout = 1000; 81 do { 82 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 83 udelay(1); 84 if (!timeout--) { 85 AUX_ERR("begin idle timeout %08x\n", ctrl); 86 return -EBUSY; 87 } 88 } while (ctrl & 0x03010000); 89 90 /* set some magic, and wait up to 1ms for it to appear */ 91 nvkm_mask(device, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq); 92 timeout = 1000; 93 do { 94 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 95 udelay(1); 96 if (!timeout--) { 97 AUX_ERR("magic wait %08x\n", ctrl); 98 auxch_fini(i2c, ch); 99 return -EBUSY; 100 } 101 } while ((ctrl & 0x03000000) != urep); 102 103 return 0; 104 } 105 106 int 107 g94_aux(struct nvkm_i2c_port *base, bool retry, 108 u8 type, u32 addr, u8 *data, u8 size) 109 { 110 struct nvkm_i2c *i2c = nvkm_i2c(base); 111 struct nvkm_device *device = i2c->subdev.device; 112 struct nv50_i2c_port *port = (void *)base; 113 u32 ctrl, stat, timeout, retries; 114 u32 xbuf[4] = {}; 115 int ch = port->addr; 116 int ret, i; 117 118 AUX_DBG("%d: %08x %d\n", type, addr, size); 119 120 ret = auxch_init(i2c, ch); 121 if (ret < 0) 122 goto out; 123 124 stat = nvkm_rd32(device, 0x00e4e8 + (ch * 0x50)); 125 if (!(stat & 0x10000000)) { 126 AUX_DBG("sink not detected\n"); 127 ret = -ENXIO; 128 goto out; 129 } 130 131 if (!(type & 1)) { 132 memcpy(xbuf, data, size); 133 for (i = 0; i < 16; i += 4) { 134 AUX_DBG("wr %08x\n", xbuf[i / 4]); 135 nvkm_wr32(device, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]); 136 } 137 } 138 139 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 140 ctrl &= ~0x0001f0ff; 141 ctrl |= type << 12; 142 ctrl |= size - 1; 143 nvkm_wr32(device, 0x00e4e0 + (ch * 0x50), addr); 144 145 /* (maybe) retry transaction a number of times on failure... */ 146 for (retries = 0; !ret && retries < 32; retries++) { 147 /* reset, and delay a while if this is a retry */ 148 nvkm_wr32(device, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl); 149 nvkm_wr32(device, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl); 150 if (retries) 151 udelay(400); 152 153 /* transaction request, wait up to 1ms for it to complete */ 154 nvkm_wr32(device, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl); 155 156 timeout = 1000; 157 do { 158 ctrl = nvkm_rd32(device, 0x00e4e4 + (ch * 0x50)); 159 udelay(1); 160 if (!timeout--) { 161 AUX_ERR("tx req timeout %08x\n", ctrl); 162 ret = -EIO; 163 goto out; 164 } 165 } while (ctrl & 0x00010000); 166 ret = 1; 167 168 /* read status, and check if transaction completed ok */ 169 stat = nvkm_mask(device, 0x00e4e8 + (ch * 0x50), 0, 0); 170 if ((stat & 0x000f0000) == 0x00080000 || 171 (stat & 0x000f0000) == 0x00020000) 172 ret = retry ? 0 : 1; 173 if ((stat & 0x00000100)) 174 ret = -ETIMEDOUT; 175 if ((stat & 0x00000e00)) 176 ret = -EIO; 177 178 AUX_DBG("%02d %08x %08x\n", retries, ctrl, stat); 179 } 180 181 if (type & 1) { 182 for (i = 0; i < 16; i += 4) { 183 xbuf[i / 4] = nvkm_rd32(device, 0x00e4d0 + (ch * 0x50) + i); 184 AUX_DBG("rd %08x\n", xbuf[i / 4]); 185 } 186 memcpy(data, xbuf, size); 187 } 188 189 out: 190 auxch_fini(i2c, ch); 191 return ret < 0 ? ret : (stat & 0x000f0000) >> 16; 192 } 193 194 static const struct nvkm_i2c_func 195 g94_i2c_func = { 196 .drive_scl = nv50_i2c_drive_scl, 197 .drive_sda = nv50_i2c_drive_sda, 198 .sense_scl = nv50_i2c_sense_scl, 199 .sense_sda = nv50_i2c_sense_sda, 200 }; 201 202 static int 203 g94_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 204 struct nvkm_oclass *oclass, void *data, u32 index, 205 struct nvkm_object **pobject) 206 { 207 struct dcb_i2c_entry *info = data; 208 struct nv50_i2c_port *port; 209 int ret; 210 211 ret = nvkm_i2c_port_create(parent, engine, oclass, index, 212 &nvkm_i2c_bit_algo, &g94_i2c_func, &port); 213 *pobject = nv_object(port); 214 if (ret) 215 return ret; 216 217 if (info->drive >= nv50_i2c_addr_nr) 218 return -EINVAL; 219 220 port->state = 7; 221 port->addr = nv50_i2c_addr[info->drive]; 222 return 0; 223 } 224 225 static const struct nvkm_i2c_func 226 g94_aux_func = { 227 .aux = g94_aux, 228 }; 229 230 int 231 g94_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 232 struct nvkm_oclass *oclass, void *data, u32 index, 233 struct nvkm_object **pobject) 234 { 235 struct dcb_i2c_entry *info = data; 236 struct nv50_i2c_port *port; 237 int ret; 238 239 ret = nvkm_i2c_port_create(parent, engine, oclass, index, 240 &nvkm_i2c_aux_algo, &g94_aux_func, &port); 241 *pobject = nv_object(port); 242 if (ret) 243 return ret; 244 245 port->base.aux = info->auxch; 246 port->addr = info->auxch; 247 return 0; 248 } 249 250 static struct nvkm_oclass 251 g94_i2c_sclass[] = { 252 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), 253 .ofuncs = &(struct nvkm_ofuncs) { 254 .ctor = g94_i2c_port_ctor, 255 .dtor = _nvkm_i2c_port_dtor, 256 .init = nv50_i2c_port_init, 257 .fini = _nvkm_i2c_port_fini, 258 }, 259 }, 260 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), 261 .ofuncs = &(struct nvkm_ofuncs) { 262 .ctor = g94_aux_port_ctor, 263 .dtor = _nvkm_i2c_port_dtor, 264 .init = _nvkm_i2c_port_init, 265 .fini = _nvkm_i2c_port_fini, 266 }, 267 }, 268 {} 269 }; 270 271 struct nvkm_oclass * 272 g94_i2c_oclass = &(struct nvkm_i2c_impl) { 273 .base.handle = NV_SUBDEV(I2C, 0x94), 274 .base.ofuncs = &(struct nvkm_ofuncs) { 275 .ctor = _nvkm_i2c_ctor, 276 .dtor = _nvkm_i2c_dtor, 277 .init = _nvkm_i2c_init, 278 .fini = _nvkm_i2c_fini, 279 }, 280 .sclass = g94_i2c_sclass, 281 .pad_x = &nv04_i2c_pad_oclass, 282 .pad_s = &g94_i2c_pad_oclass, 283 .aux = 4, 284 .aux_stat = g94_aux_stat, 285 .aux_mask = g94_aux_mask, 286 }.base; 287