1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 void 27 nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match) 28 { 29 struct nvkm_device *device = gpio->subdev.device; 30 struct nvkm_bios *bios = device->bios; 31 u8 ver, len; 32 u16 entry; 33 int ent = -1; 34 35 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { 36 static const u32 regs[] = { 0xe100, 0xe28c }; 37 u32 data = nvbios_rd32(bios, entry); 38 u8 line = (data & 0x0000001f); 39 u8 func = (data & 0x0000ff00) >> 8; 40 u8 defs = !!(data & 0x01000000); 41 u8 unk0 = !!(data & 0x02000000); 42 u8 unk1 = !!(data & 0x04000000); 43 u32 val = (unk1 << 16) | unk0; 44 u32 reg = regs[line >> 4]; 45 u32 lsh = line & 0x0f; 46 47 if ( func == DCB_GPIO_UNUSED || 48 (match != DCB_GPIO_UNUSED && match != func)) 49 continue; 50 51 gpio->set(gpio, 0, func, line, defs); 52 53 nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh); 54 } 55 } 56 57 int 58 nv50_gpio_location(int line, u32 *reg, u32 *shift) 59 { 60 const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 61 62 if (line >= 32) 63 return -EINVAL; 64 65 *reg = nv50_gpio_reg[line >> 3]; 66 *shift = (line & 7) << 2; 67 return 0; 68 } 69 70 int 71 nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) 72 { 73 struct nvkm_device *device = gpio->subdev.device; 74 u32 reg, shift; 75 76 if (nv50_gpio_location(line, ®, &shift)) 77 return -EINVAL; 78 79 nvkm_mask(device, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift); 80 return 0; 81 } 82 83 int 84 nv50_gpio_sense(struct nvkm_gpio *gpio, int line) 85 { 86 struct nvkm_device *device = gpio->subdev.device; 87 u32 reg, shift; 88 89 if (nv50_gpio_location(line, ®, &shift)) 90 return -EINVAL; 91 92 return !!(nvkm_rd32(device, reg) & (4 << shift)); 93 } 94 95 static void 96 nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) 97 { 98 struct nvkm_device *device = gpio->subdev.device; 99 u32 intr = nvkm_rd32(device, 0x00e054); 100 u32 stat = nvkm_rd32(device, 0x00e050) & intr; 101 *lo = (stat & 0xffff0000) >> 16; 102 *hi = (stat & 0x0000ffff); 103 nvkm_wr32(device, 0x00e054, intr); 104 } 105 106 static void 107 nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) 108 { 109 struct nvkm_device *device = gpio->subdev.device; 110 u32 inte = nvkm_rd32(device, 0x00e050); 111 if (type & NVKM_GPIO_LO) 112 inte = (inte & ~(mask << 16)) | (data << 16); 113 if (type & NVKM_GPIO_HI) 114 inte = (inte & ~mask) | data; 115 nvkm_wr32(device, 0x00e050, inte); 116 } 117 118 struct nvkm_oclass * 119 nv50_gpio_oclass = &(struct nvkm_gpio_impl) { 120 .base.handle = NV_SUBDEV(GPIO, 0x50), 121 .base.ofuncs = &(struct nvkm_ofuncs) { 122 .ctor = _nvkm_gpio_ctor, 123 .dtor = _nvkm_gpio_dtor, 124 .init = _nvkm_gpio_init, 125 .fini = _nvkm_gpio_fini, 126 }, 127 .lines = 16, 128 .intr_stat = nv50_gpio_intr_stat, 129 .intr_mask = nv50_gpio_intr_mask, 130 .drive = nv50_gpio_drive, 131 .sense = nv50_gpio_sense, 132 .reset = nv50_gpio_reset, 133 }.base; 134