1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 void 27 g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) 28 { 29 u32 intr0 = nv_rd32(gpio, 0x00e054); 30 u32 intr1 = nv_rd32(gpio, 0x00e074); 31 u32 stat0 = nv_rd32(gpio, 0x00e050) & intr0; 32 u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1; 33 *lo = (stat1 & 0xffff0000) | (stat0 >> 16); 34 *hi = (stat1 << 16) | (stat0 & 0x0000ffff); 35 nv_wr32(gpio, 0x00e054, intr0); 36 nv_wr32(gpio, 0x00e074, intr1); 37 } 38 39 void 40 g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) 41 { 42 u32 inte0 = nv_rd32(gpio, 0x00e050); 43 u32 inte1 = nv_rd32(gpio, 0x00e070); 44 if (type & NVKM_GPIO_LO) 45 inte0 = (inte0 & ~(mask << 16)) | (data << 16); 46 if (type & NVKM_GPIO_HI) 47 inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); 48 mask >>= 16; 49 data >>= 16; 50 if (type & NVKM_GPIO_LO) 51 inte1 = (inte1 & ~(mask << 16)) | (data << 16); 52 if (type & NVKM_GPIO_HI) 53 inte1 = (inte1 & ~mask) | data; 54 nv_wr32(gpio, 0x00e050, inte0); 55 nv_wr32(gpio, 0x00e070, inte1); 56 } 57 58 struct nvkm_oclass * 59 g94_gpio_oclass = &(struct nvkm_gpio_impl) { 60 .base.handle = NV_SUBDEV(GPIO, 0x94), 61 .base.ofuncs = &(struct nvkm_ofuncs) { 62 .ctor = _nvkm_gpio_ctor, 63 .dtor = _nvkm_gpio_dtor, 64 .init = _nvkm_gpio_init, 65 .fini = _nvkm_gpio_fini, 66 }, 67 .lines = 32, 68 .intr_stat = g94_gpio_intr_stat, 69 .intr_mask = g94_gpio_intr_mask, 70 .drive = nv50_gpio_drive, 71 .sense = nv50_gpio_sense, 72 .reset = nv50_gpio_reset, 73 }.base; 74