1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "ramseq.h" 26 27 #include <core/option.h> 28 #include <subdev/bios.h> 29 #include <subdev/bios/perf.h> 30 #include <subdev/bios/pll.h> 31 #include <subdev/bios/rammap.h> 32 #include <subdev/bios/timing.h> 33 #include <subdev/clk/pll.h> 34 35 struct nv50_ramseq { 36 struct hwsq base; 37 struct hwsq_reg r_0x002504; 38 struct hwsq_reg r_0x004008; 39 struct hwsq_reg r_0x00400c; 40 struct hwsq_reg r_0x00c040; 41 struct hwsq_reg r_0x100200; 42 struct hwsq_reg r_0x100210; 43 struct hwsq_reg r_0x10021c; 44 struct hwsq_reg r_0x1002d0; 45 struct hwsq_reg r_0x1002d4; 46 struct hwsq_reg r_0x1002dc; 47 struct hwsq_reg r_0x10053c; 48 struct hwsq_reg r_0x1005a0; 49 struct hwsq_reg r_0x1005a4; 50 struct hwsq_reg r_0x100710; 51 struct hwsq_reg r_0x100714; 52 struct hwsq_reg r_0x100718; 53 struct hwsq_reg r_0x10071c; 54 struct hwsq_reg r_0x100da0; 55 struct hwsq_reg r_0x100e20; 56 struct hwsq_reg r_0x100e24; 57 struct hwsq_reg r_0x611200; 58 struct hwsq_reg r_timing[9]; 59 struct hwsq_reg r_mr[4]; 60 }; 61 62 struct nv50_ram { 63 struct nvkm_ram base; 64 struct nv50_ramseq hwsq; 65 }; 66 67 #define T(t) cfg->timing_10_##t 68 static int 69 nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) 70 { 71 struct nvkm_device *device = fb->subdev.device; 72 struct nv50_ram *ram = (void *)fb->ram; 73 struct nvbios_ramcfg *cfg = &ram->base.target.bios; 74 u32 cur2, cur4, cur7, cur8; 75 u8 unkt3b; 76 77 cur2 = nvkm_rd32(device, 0x100228); 78 cur4 = nvkm_rd32(device, 0x100230); 79 cur7 = nvkm_rd32(device, 0x10023c); 80 cur8 = nvkm_rd32(device, 0x100240); 81 82 switch ((!T(CWL)) * ram->base.type) { 83 case NV_MEM_TYPE_DDR2: 84 T(CWL) = T(CL) - 1; 85 break; 86 case NV_MEM_TYPE_GDDR3: 87 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; 88 break; 89 } 90 91 /* XXX: N=1 is not proper statistics */ 92 if (nv_device(fb)->chipset == 0xa0) { 93 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; 94 timing[6] = (0x2d + T(CL) - T(CWL) + 95 ram->base.next->bios.rammap_00_16_40) << 16 | 96 T(CWL) << 8 | 97 (0x2f + T(CL) - T(CWL)); 98 } else { 99 unkt3b = 0x16; 100 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | 101 max_t(s8, T(CWL) - 2, 1) << 8 | 102 (0x2e + T(CL) - T(CWL)); 103 } 104 105 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 106 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 107 max_t(u8, T(18), 1) << 16 | 108 (T(WTR) + 1 + T(CWL)) << 8 | 109 (3 + T(CL) - T(CWL)); 110 timing[2] = (T(CWL) - 1) << 24 | 111 (T(RRD) << 16) | 112 (T(RCDWR) << 8) | 113 T(RCDRD); 114 timing[3] = (unkt3b - 2 + T(CL)) << 24 | 115 unkt3b << 16 | 116 (T(CL) - 1) << 8 | 117 (T(CL) - 1); 118 timing[4] = (cur4 & 0xffff0000) | 119 T(13) << 8 | 120 T(13); 121 timing[5] = T(RFC) << 24 | 122 max_t(u8, T(RCDRD), T(RCDWR)) << 16 | 123 T(RP); 124 /* Timing 6 is already done above */ 125 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; 126 timing[8] = (cur8 & 0xffffff00); 127 128 /* XXX: P.version == 1 only has DDR2 and GDDR3? */ 129 if (fb->ram->type == NV_MEM_TYPE_DDR2) { 130 timing[5] |= (T(CL) + 3) << 8; 131 timing[8] |= (T(CL) - 4); 132 } else if (fb->ram->type == NV_MEM_TYPE_GDDR3) { 133 timing[5] |= (T(CL) + 2) << 8; 134 timing[8] |= (T(CL) - 2); 135 } 136 137 nv_debug(fb, " 220: %08x %08x %08x %08x\n", 138 timing[0], timing[1], timing[2], timing[3]); 139 nv_debug(fb, " 230: %08x %08x %08x %08x\n", 140 timing[4], timing[5], timing[6], timing[7]); 141 nv_debug(fb, " 240: %08x\n", timing[8]); 142 return 0; 143 } 144 #undef T 145 146 static void 147 nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) 148 { 149 ram_mask(hwsq, mr[0], 0x100, 0x100); 150 ram_mask(hwsq, mr[0], 0x100, 0x000); 151 ram_nsec(hwsq, 24000); 152 } 153 154 static int 155 nv50_ram_calc(struct nvkm_fb *fb, u32 freq) 156 { 157 struct nvkm_bios *bios = nvkm_bios(fb); 158 struct nv50_ram *ram = (void *)fb->ram; 159 struct nv50_ramseq *hwsq = &ram->hwsq; 160 struct nvbios_perfE perfE; 161 struct nvbios_pll mpll; 162 struct nvkm_ram_data *next; 163 u8 ver, hdr, cnt, len, strap, size; 164 u32 data; 165 u32 r100da0, r004008, unk710, unk714, unk718, unk71c; 166 int N1, M1, N2, M2, P; 167 int ret, i; 168 u32 timing[9]; 169 170 next = &ram->base.target; 171 next->freq = freq; 172 ram->base.next = next; 173 174 /* lookup closest matching performance table entry for frequency */ 175 i = 0; 176 do { 177 data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, 178 &size, &perfE); 179 if (!data || (ver < 0x25 || ver >= 0x40) || 180 (size < 2)) { 181 nv_error(fb, "invalid/missing perftab entry\n"); 182 return -EINVAL; 183 } 184 } while (perfE.memory < freq); 185 186 nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios); 187 188 /* locate specific data set for the attached memory */ 189 strap = nvbios_ramcfg_index(nv_subdev(fb)); 190 if (strap >= cnt) { 191 nv_error(fb, "invalid ramcfg strap\n"); 192 return -EINVAL; 193 } 194 195 data = nvbios_rammapSp_from_perf(bios, data + hdr, size, strap, 196 &next->bios); 197 if (!data) { 198 nv_error(fb, "invalid/missing rammap entry "); 199 return -EINVAL; 200 } 201 202 /* lookup memory timings, if bios says they're present */ 203 if (next->bios.ramcfg_timing != 0xff) { 204 data = nvbios_timingEp(bios, next->bios.ramcfg_timing, 205 &ver, &hdr, &cnt, &len, &next->bios); 206 if (!data || ver != 0x10 || hdr < 0x12) { 207 nv_error(fb, "invalid/missing timing entry " 208 "%02x %04x %02x %02x\n", 209 strap, data, ver, hdr); 210 return -EINVAL; 211 } 212 } 213 214 nv50_ram_timing_calc(fb, timing); 215 216 ret = ram_init(hwsq, nv_subdev(fb)); 217 if (ret) 218 return ret; 219 220 /* Determine ram-specific MR values */ 221 ram->base.mr[0] = ram_rd32(hwsq, mr[0]); 222 ram->base.mr[1] = ram_rd32(hwsq, mr[1]); 223 ram->base.mr[2] = ram_rd32(hwsq, mr[2]); 224 225 switch (ram->base.type) { 226 case NV_MEM_TYPE_GDDR3: 227 ret = nvkm_gddr3_calc(&ram->base); 228 break; 229 default: 230 ret = -ENOSYS; 231 break; 232 } 233 234 if (ret) 235 return ret; 236 237 /* Always disable this bit during reclock */ 238 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000); 239 240 ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */ 241 ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */ 242 ram_wr32(hwsq, 0x611200, 0x00003300); 243 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ 244 ram_nsec(hwsq, 8000); 245 ram_setf(hwsq, 0x10, 0x00); /* disable fb */ 246 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 247 ram_nsec(hwsq, 2000); 248 249 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ 250 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ 251 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ 252 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */ 253 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */ 254 255 ret = nvbios_pll_parse(bios, 0x004008, &mpll); 256 mpll.vco2.max_freq = 0; 257 if (ret >= 0) { 258 ret = nv04_pll_calc(nv_subdev(fb), &mpll, freq, 259 &N1, &M1, &N2, &M2, &P); 260 if (ret <= 0) 261 ret = -EINVAL; 262 } 263 264 if (ret < 0) 265 return ret; 266 267 /* XXX: 750MHz seems rather arbitrary */ 268 if (freq <= 750000) { 269 r100da0 = 0x00000010; 270 r004008 = 0x90000000; 271 } else { 272 r100da0 = 0x00000000; 273 r004008 = 0x80000000; 274 } 275 276 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); 277 278 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000); 279 /* XXX: Is rammap_00_16_40 the DLL bit we've seen in GT215? Why does 280 * it have a different rammap bit from DLLoff? */ 281 ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 | 282 next->bios.rammap_00_16_40 << 14); 283 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); 284 ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); 285 if (nv_device(fb)->chipset >= 0x96) 286 ram_wr32(hwsq, 0x100da0, r100da0); 287 ram_nsec(hwsq, 64000); /*XXX*/ 288 ram_nsec(hwsq, 32000); /*XXX*/ 289 290 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000); 291 292 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */ 293 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */ 294 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */ 295 296 ram_nsec(hwsq, 12000); 297 298 switch (ram->base.type) { 299 case NV_MEM_TYPE_DDR2: 300 ram_nuke(hwsq, mr[0]); /* force update */ 301 ram_mask(hwsq, mr[0], 0x000, 0x000); 302 break; 303 case NV_MEM_TYPE_GDDR3: 304 ram_nuke(hwsq, mr[1]); /* force update */ 305 ram_wr32(hwsq, mr[1], ram->base.mr[1]); 306 ram_nuke(hwsq, mr[0]); /* force update */ 307 ram_wr32(hwsq, mr[0], ram->base.mr[0]); 308 break; 309 default: 310 break; 311 } 312 313 ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); 314 ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); 315 ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); 316 ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); 317 ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); 318 ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); 319 ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); 320 ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); 321 ram_mask(hwsq, timing[5], 0xffffffff, timing[5]); 322 323 if (!next->bios.ramcfg_00_03_02) 324 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000); 325 ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12); 326 327 /* XXX: A lot of this could be "chipset"/"ram type" specific stuff */ 328 unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000101; 329 unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020; 330 unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100; 331 unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100; 332 333 if ( next->bios.ramcfg_00_03_01) 334 unk71c |= 0x00000100; 335 if ( next->bios.ramcfg_00_03_02) 336 unk710 |= 0x00000100; 337 if (!next->bios.ramcfg_00_03_08) { 338 unk710 |= 0x1; 339 unk714 |= 0x20; 340 } 341 if ( next->bios.ramcfg_00_04_04) 342 unk714 |= 0x70000000; 343 if ( next->bios.ramcfg_00_04_20) 344 unk718 |= 0x00000100; 345 346 ram_mask(hwsq, 0x100714, 0xffffffff, unk714); 347 ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c); 348 ram_mask(hwsq, 0x100718, 0xffffffff, unk718); 349 ram_mask(hwsq, 0x100710, 0xffffffff, unk710); 350 351 if (next->bios.rammap_00_16_20) { 352 ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 | 353 next->bios.ramcfg_00_06 << 8 | 354 next->bios.ramcfg_00_05); 355 ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 | 356 next->bios.ramcfg_00_08); 357 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000); 358 } else { 359 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000); 360 } 361 ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); 362 363 /* Reset DLL */ 364 if (!next->bios.ramcfg_DLLoff) 365 nvkm_sddr2_dll_reset(hwsq); 366 367 ram_setf(hwsq, 0x10, 0x01); /* enable fb */ 368 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 369 ram_wr32(hwsq, 0x611200, 0x00003330); 370 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */ 371 372 if (next->bios.rammap_00_17_02) 373 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800); 374 if (!next->bios.rammap_00_16_40) 375 ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000); 376 if (next->bios.ramcfg_00_03_02) 377 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000); 378 379 return 0; 380 } 381 382 static int 383 nv50_ram_prog(struct nvkm_fb *fb) 384 { 385 struct nvkm_device *device = nv_device(fb); 386 struct nv50_ram *ram = (void *)fb->ram; 387 struct nv50_ramseq *hwsq = &ram->hwsq; 388 389 ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); 390 return 0; 391 } 392 393 static void 394 nv50_ram_tidy(struct nvkm_fb *fb) 395 { 396 struct nv50_ram *ram = (void *)fb->ram; 397 struct nv50_ramseq *hwsq = &ram->hwsq; 398 ram_exec(hwsq, false); 399 } 400 401 void 402 __nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem *mem) 403 { 404 struct nvkm_mm_node *this; 405 406 while (!list_empty(&mem->regions)) { 407 this = list_first_entry(&mem->regions, typeof(*this), rl_entry); 408 409 list_del(&this->rl_entry); 410 nvkm_mm_free(&fb->vram, &this); 411 } 412 413 nvkm_mm_free(&fb->tags, &mem->tag); 414 } 415 416 void 417 nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) 418 { 419 struct nvkm_mem *mem = *pmem; 420 421 *pmem = NULL; 422 if (unlikely(mem == NULL)) 423 return; 424 425 mutex_lock(&fb->subdev.mutex); 426 __nv50_ram_put(fb, mem); 427 mutex_unlock(&fb->subdev.mutex); 428 429 kfree(mem); 430 } 431 432 int 433 nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, 434 u32 memtype, struct nvkm_mem **pmem) 435 { 436 struct nvkm_mm *heap = &fb->vram; 437 struct nvkm_mm *tags = &fb->tags; 438 struct nvkm_mm_node *r; 439 struct nvkm_mem *mem; 440 int comp = (memtype & 0x300) >> 8; 441 int type = (memtype & 0x07f); 442 int back = (memtype & 0x800); 443 int min, max, ret; 444 445 max = (size >> 12); 446 min = ncmin ? (ncmin >> 12) : max; 447 align >>= 12; 448 449 mem = kzalloc(sizeof(*mem), GFP_KERNEL); 450 if (!mem) 451 return -ENOMEM; 452 453 mutex_lock(&fb->subdev.mutex); 454 if (comp) { 455 if (align == 16) { 456 int n = (max >> 4) * comp; 457 458 ret = nvkm_mm_head(tags, 0, 1, n, n, 1, &mem->tag); 459 if (ret) 460 mem->tag = NULL; 461 } 462 463 if (unlikely(!mem->tag)) 464 comp = 0; 465 } 466 467 INIT_LIST_HEAD(&mem->regions); 468 mem->memtype = (comp << 7) | type; 469 mem->size = max; 470 471 type = nv50_fb_memtype[type]; 472 do { 473 if (back) 474 ret = nvkm_mm_tail(heap, 0, type, max, min, align, &r); 475 else 476 ret = nvkm_mm_head(heap, 0, type, max, min, align, &r); 477 if (ret) { 478 mutex_unlock(&fb->subdev.mutex); 479 fb->ram->put(fb, &mem); 480 return ret; 481 } 482 483 list_add_tail(&r->rl_entry, &mem->regions); 484 max -= r->length; 485 } while (max); 486 mutex_unlock(&fb->subdev.mutex); 487 488 r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); 489 mem->offset = (u64)r->offset << 12; 490 *pmem = mem; 491 return 0; 492 } 493 494 static u32 495 nv50_fb_vram_rblock(struct nvkm_fb *fb, struct nvkm_ram *ram) 496 { 497 struct nvkm_device *device = fb->subdev.device; 498 int colbits, rowbitsa, rowbitsb, banks; 499 u64 rowsize, predicted; 500 u32 r0, r4, rt, rblock_size; 501 502 r0 = nvkm_rd32(device, 0x100200); 503 r4 = nvkm_rd32(device, 0x100204); 504 rt = nvkm_rd32(device, 0x100250); 505 nv_debug(fb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", 506 r0, r4, rt, nvkm_rd32(device, 0x001540)); 507 508 colbits = (r4 & 0x0000f000) >> 12; 509 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; 510 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; 511 banks = 1 << (((r4 & 0x03000000) >> 24) + 2); 512 513 rowsize = ram->parts * banks * (1 << colbits) * 8; 514 predicted = rowsize << rowbitsa; 515 if (r0 & 0x00000004) 516 predicted += rowsize << rowbitsb; 517 518 if (predicted != ram->size) { 519 nv_warn(fb, "memory controller reports %d MiB VRAM\n", 520 (u32)(ram->size >> 20)); 521 } 522 523 rblock_size = rowsize; 524 if (rt & 1) 525 rblock_size *= 3; 526 527 nv_debug(fb, "rblock %d bytes\n", rblock_size); 528 return rblock_size; 529 } 530 531 int 532 nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, 533 struct nvkm_oclass *oclass, int length, void **pobject) 534 { 535 const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ 536 const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ 537 struct nvkm_fb *fb = nvkm_fb(parent); 538 struct nvkm_device *device = fb->subdev.device; 539 struct nvkm_bios *bios = device->bios; 540 struct nvkm_ram *ram; 541 int ret; 542 543 ret = nvkm_ram_create_(parent, engine, oclass, length, pobject); 544 ram = *pobject; 545 if (ret) 546 return ret; 547 548 ram->size = nvkm_rd32(device, 0x10020c); 549 ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); 550 551 ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; 552 ram->parts = hweight8(ram->part_mask); 553 554 switch (nvkm_rd32(device, 0x100714) & 0x00000007) { 555 case 0: ram->type = NV_MEM_TYPE_DDR1; break; 556 case 1: 557 if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) 558 ram->type = NV_MEM_TYPE_DDR3; 559 else 560 ram->type = NV_MEM_TYPE_DDR2; 561 break; 562 case 2: ram->type = NV_MEM_TYPE_GDDR3; break; 563 case 3: ram->type = NV_MEM_TYPE_GDDR4; break; 564 case 4: ram->type = NV_MEM_TYPE_GDDR5; break; 565 default: 566 break; 567 } 568 569 ret = nvkm_mm_init(&fb->vram, rsvd_head, (ram->size >> 12) - 570 (rsvd_head + rsvd_tail), 571 nv50_fb_vram_rblock(fb, ram) >> 12); 572 if (ret) 573 return ret; 574 575 ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1; 576 ram->tags = nvkm_rd32(device, 0x100320); 577 ram->get = nv50_ram_get; 578 ram->put = nv50_ram_put; 579 return 0; 580 } 581 582 static int 583 nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 584 struct nvkm_oclass *oclass, void *data, u32 datasize, 585 struct nvkm_object **pobject) 586 { 587 struct nv50_ram *ram; 588 int ret, i; 589 590 ret = nv50_ram_create(parent, engine, oclass, &ram); 591 *pobject = nv_object(ram); 592 if (ret) 593 return ret; 594 595 switch (ram->base.type) { 596 case NV_MEM_TYPE_GDDR3: 597 ram->base.calc = nv50_ram_calc; 598 ram->base.prog = nv50_ram_prog; 599 ram->base.tidy = nv50_ram_tidy; 600 break; 601 case NV_MEM_TYPE_DDR2: 602 default: 603 nv_warn(ram, "reclocking of this ram type unsupported\n"); 604 return 0; 605 } 606 607 ram->hwsq.r_0x002504 = hwsq_reg(0x002504); 608 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); 609 ram->hwsq.r_0x004008 = hwsq_reg(0x004008); 610 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); 611 ram->hwsq.r_0x100200 = hwsq_reg(0x100200); 612 ram->hwsq.r_0x100210 = hwsq_reg(0x100210); 613 ram->hwsq.r_0x10021c = hwsq_reg(0x10021c); 614 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); 615 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); 616 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); 617 ram->hwsq.r_0x10053c = hwsq_reg(0x10053c); 618 ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0); 619 ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4); 620 ram->hwsq.r_0x100710 = hwsq_reg(0x100710); 621 ram->hwsq.r_0x100714 = hwsq_reg(0x100714); 622 ram->hwsq.r_0x100718 = hwsq_reg(0x100718); 623 ram->hwsq.r_0x10071c = hwsq_reg(0x10071c); 624 ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask); 625 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); 626 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); 627 ram->hwsq.r_0x611200 = hwsq_reg(0x611200); 628 629 for (i = 0; i < 9; i++) 630 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); 631 632 if (ram->base.ranks > 1) { 633 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8); 634 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc); 635 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8); 636 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec); 637 } else { 638 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); 639 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); 640 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); 641 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); 642 } 643 644 return 0; 645 } 646 647 struct nvkm_oclass 648 nv50_ram_oclass = { 649 .ofuncs = &(struct nvkm_ofuncs) { 650 .ctor = nv50_ram_ctor, 651 .dtor = _nvkm_ram_dtor, 652 .init = _nvkm_ram_init, 653 .fini = _nvkm_ram_fini, 654 } 655 }; 656