1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #define nv50_ram(p) container_of((p), struct nv50_ram, base)
25 #include "ram.h"
26 #include "ramseq.h"
27 #include "nv50.h"
28 
29 #include <core/option.h>
30 #include <subdev/bios.h>
31 #include <subdev/bios/perf.h>
32 #include <subdev/bios/pll.h>
33 #include <subdev/bios/rammap.h>
34 #include <subdev/bios/timing.h>
35 #include <subdev/clk/pll.h>
36 #include <subdev/gpio.h>
37 
38 struct nv50_ramseq {
39 	struct hwsq base;
40 	struct hwsq_reg r_0x002504;
41 	struct hwsq_reg r_0x004008;
42 	struct hwsq_reg r_0x00400c;
43 	struct hwsq_reg r_0x00c040;
44 	struct hwsq_reg r_0x100200;
45 	struct hwsq_reg r_0x100210;
46 	struct hwsq_reg r_0x10021c;
47 	struct hwsq_reg r_0x1002d0;
48 	struct hwsq_reg r_0x1002d4;
49 	struct hwsq_reg r_0x1002dc;
50 	struct hwsq_reg r_0x10053c;
51 	struct hwsq_reg r_0x1005a0;
52 	struct hwsq_reg r_0x1005a4;
53 	struct hwsq_reg r_0x100710;
54 	struct hwsq_reg r_0x100714;
55 	struct hwsq_reg r_0x100718;
56 	struct hwsq_reg r_0x10071c;
57 	struct hwsq_reg r_0x100da0;
58 	struct hwsq_reg r_0x100e20;
59 	struct hwsq_reg r_0x100e24;
60 	struct hwsq_reg r_0x611200;
61 	struct hwsq_reg r_timing[9];
62 	struct hwsq_reg r_mr[4];
63 	struct hwsq_reg r_gpio[4];
64 };
65 
66 struct nv50_ram {
67 	struct nvkm_ram base;
68 	struct nv50_ramseq hwsq;
69 };
70 
71 #define T(t) cfg->timing_10_##t
72 static int
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing)
74 {
75 	struct nvbios_ramcfg *cfg = &ram->base.target.bios;
76 	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
77 	struct nvkm_device *device = subdev->device;
78 	u32 cur2, cur4, cur7, cur8;
79 	u8 unkt3b;
80 
81 	cur2 = nvkm_rd32(device, 0x100228);
82 	cur4 = nvkm_rd32(device, 0x100230);
83 	cur7 = nvkm_rd32(device, 0x10023c);
84 	cur8 = nvkm_rd32(device, 0x100240);
85 
86 	switch ((!T(CWL)) * ram->base.type) {
87 	case NVKM_RAM_TYPE_DDR2:
88 		T(CWL) = T(CL) - 1;
89 		break;
90 	case NVKM_RAM_TYPE_GDDR3:
91 		T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
92 		break;
93 	}
94 
95 	/* XXX: N=1 is not proper statistics */
96 	if (device->chipset == 0xa0) {
97 		unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40;
98 		timing[6] = (0x2d + T(CL) - T(CWL) +
99 				ram->base.next->bios.rammap_00_16_40) << 16 |
100 			    T(CWL) << 8 |
101 			    (0x2f + T(CL) - T(CWL));
102 	} else {
103 		unkt3b = 0x16;
104 		timing[6] = (0x2b + T(CL) - T(CWL)) << 16 |
105 			    max_t(s8, T(CWL) - 2, 1) << 8 |
106 			    (0x2e + T(CL) - T(CWL));
107 	}
108 
109 	timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
110 	timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
111 		    max_t(u8, T(18), 1) << 16 |
112 		    (T(WTR) + 1 + T(CWL)) << 8 |
113 		    (3 + T(CL) - T(CWL));
114 	timing[2] = (T(CWL) - 1) << 24 |
115 		    (T(RRD) << 16) |
116 		    (T(RCDWR) << 8) |
117 		    T(RCDRD);
118 	timing[3] = (unkt3b - 2 + T(CL)) << 24 |
119 		    unkt3b << 16 |
120 		    (T(CL) - 1) << 8 |
121 		    (T(CL) - 1);
122 	timing[4] = (cur4 & 0xffff0000) |
123 		    T(13) << 8 |
124 		    T(13);
125 	timing[5] = T(RFC) << 24 |
126 		    max_t(u8, T(RCDRD), T(RCDWR)) << 16 |
127 		    T(RP);
128 	/* Timing 6 is already done above */
129 	timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16;
130 	timing[8] = (cur8 & 0xffffff00);
131 
132 	/* XXX: P.version == 1 only has DDR2 and GDDR3? */
133 	if (ram->base.type == NVKM_RAM_TYPE_DDR2) {
134 		timing[5] |= (T(CL) + 3) << 8;
135 		timing[8] |= (T(CL) - 4);
136 	} else
137 	if (ram->base.type == NVKM_RAM_TYPE_GDDR3) {
138 		timing[5] |= (T(CL) + 2) << 8;
139 		timing[8] |= (T(CL) - 2);
140 	}
141 
142 	nvkm_debug(subdev, " 220: %08x %08x %08x %08x\n",
143 		   timing[0], timing[1], timing[2], timing[3]);
144 	nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n",
145 		   timing[4], timing[5], timing[6], timing[7]);
146 	nvkm_debug(subdev, " 240: %08x\n", timing[8]);
147 	return 0;
148 }
149 
150 static int
151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing)
152 {
153 	unsigned int i;
154 	struct nvbios_ramcfg *cfg = &ram->base.target.bios;
155 	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
156 	struct nvkm_device *device = subdev->device;
157 
158 	for (i = 0; i <= 8; i++)
159 		timing[i] = nvkm_rd32(device, 0x100220 + (i * 4));
160 
161 	/* Derive the bare minimum for the MR calculation to succeed */
162 	cfg->timing_ver = 0x10;
163 	T(CL) = (timing[3] & 0xff) + 1;
164 
165 	switch (ram->base.type) {
166 	case NVKM_RAM_TYPE_DDR2:
167 		T(CWL) = T(CL) - 1;
168 		break;
169 	case NVKM_RAM_TYPE_GDDR3:
170 		T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1;
171 		break;
172 	default:
173 		return -ENOSYS;
174 	}
175 
176 	T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL);
177 
178 	return 0;
179 }
180 #undef T
181 
182 static void
183 nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq)
184 {
185 	ram_mask(hwsq, mr[0], 0x100, 0x100);
186 	ram_mask(hwsq, mr[0], 0x100, 0x000);
187 	ram_nsec(hwsq, 24000);
188 }
189 
190 static void
191 nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val)
192 {
193 	struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio;
194 	struct dcb_gpio_func func;
195 	u32 reg, sh, gpio_val;
196 	int ret;
197 
198 	if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) {
199 		ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func);
200 		if (ret)
201 			return;
202 
203 		reg = func.line >> 3;
204 		sh = (func.line & 0x7) << 2;
205 		gpio_val = ram_rd32(hwsq, gpio[reg]);
206 
207 		if (gpio_val & (8 << sh))
208 			val = !val;
209 		if (!(func.log[1] & 1))
210 			val = !val;
211 
212 		ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh));
213 		ram_nsec(hwsq, 20000);
214 	}
215 }
216 
217 static int
218 nv50_ram_calc(struct nvkm_ram *base, u32 freq)
219 {
220 	struct nv50_ram *ram = nv50_ram(base);
221 	struct nv50_ramseq *hwsq = &ram->hwsq;
222 	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
223 	struct nvkm_bios *bios = subdev->device->bios;
224 	struct nvbios_perfE perfE;
225 	struct nvbios_pll mpll;
226 	struct nvkm_ram_data *next;
227 	u8  ver, hdr, cnt, len, strap, size;
228 	u32 data;
229 	u32 r100da0, r004008, unk710, unk714, unk718, unk71c;
230 	int N1, M1, N2, M2, P;
231 	int ret, i;
232 	u32 timing[9];
233 
234 	next = &ram->base.target;
235 	next->freq = freq;
236 	ram->base.next = next;
237 
238 	/* lookup closest matching performance table entry for frequency */
239 	i = 0;
240 	do {
241 		data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt,
242 				     &size, &perfE);
243 		if (!data || (ver < 0x25 || ver >= 0x40) ||
244 		    (size < 2)) {
245 			nvkm_error(subdev, "invalid/missing perftab entry\n");
246 			return -EINVAL;
247 		}
248 	} while (perfE.memory < freq);
249 
250 	nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios);
251 
252 	/* locate specific data set for the attached memory */
253 	strap = nvbios_ramcfg_index(subdev);
254 	if (strap >= cnt) {
255 		nvkm_error(subdev, "invalid ramcfg strap\n");
256 		return -EINVAL;
257 	}
258 
259 	data = nvbios_rammapSp_from_perf(bios, data + hdr, size, strap,
260 			&next->bios);
261 	if (!data) {
262 		nvkm_error(subdev, "invalid/missing rammap entry ");
263 		return -EINVAL;
264 	}
265 
266 	/* lookup memory timings, if bios says they're present */
267 	if (next->bios.ramcfg_timing != 0xff) {
268 		data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
269 					&ver, &hdr, &cnt, &len, &next->bios);
270 		if (!data || ver != 0x10 || hdr < 0x12) {
271 			nvkm_error(subdev, "invalid/missing timing entry "
272 				 "%02x %04x %02x %02x\n",
273 				 strap, data, ver, hdr);
274 			return -EINVAL;
275 		}
276 		nv50_ram_timing_calc(ram, timing);
277 	} else {
278 		nv50_ram_timing_read(ram, timing);
279 	}
280 
281 	ret = ram_init(hwsq, subdev);
282 	if (ret)
283 		return ret;
284 
285 	/* Determine ram-specific MR values */
286 	ram->base.mr[0] = ram_rd32(hwsq, mr[0]);
287 	ram->base.mr[1] = ram_rd32(hwsq, mr[1]);
288 	ram->base.mr[2] = ram_rd32(hwsq, mr[2]);
289 
290 	switch (ram->base.type) {
291 	case NVKM_RAM_TYPE_GDDR3:
292 		ret = nvkm_gddr3_calc(&ram->base);
293 		break;
294 	default:
295 		ret = -ENOSYS;
296 		break;
297 	}
298 
299 	if (ret) {
300 		nvkm_error(subdev, "Could not calculate MR\n");
301 		return ret;
302 	}
303 
304 	if (subdev->device->chipset <= 0x96 && !next->bios.ramcfg_00_03_02)
305 		ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000);
306 
307 	/* Always disable this bit during reclock */
308 	ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000);
309 
310 	ram_wait_vblank(hwsq);
311 	ram_wr32(hwsq, 0x611200, 0x00003300);
312 	ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */
313 	ram_nsec(hwsq, 8000);
314 	ram_setf(hwsq, 0x10, 0x00); /* disable fb */
315 	ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
316 	ram_nsec(hwsq, 2000);
317 
318 	if (next->bios.timing_10_ODT)
319 		nv50_ram_gpio(hwsq, 0x2e, 1);
320 
321 	ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
322 	ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
323 	ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
324 	ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */
325 	ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */
326 
327 	ret = nvbios_pll_parse(bios, 0x004008, &mpll);
328 	mpll.vco2.max_freq = 0;
329 	if (ret >= 0) {
330 		ret = nv04_pll_calc(subdev, &mpll, freq,
331 				    &N1, &M1, &N2, &M2, &P);
332 		if (ret <= 0)
333 			ret = -EINVAL;
334 	}
335 
336 	if (ret < 0)
337 		return ret;
338 
339 	/* XXX: 750MHz seems rather arbitrary */
340 	if (freq <= 750000) {
341 		r100da0 = 0x00000010;
342 		r004008 = 0x90000000;
343 	} else {
344 		r100da0 = 0x00000000;
345 		r004008 = 0x80000000;
346 	}
347 
348 	r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16);
349 
350 	ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
351 	/* XXX: Is rammap_00_16_40 the DLL bit we've seen in GT215? Why does
352 	 * it have a different rammap bit from DLLoff? */
353 	ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 |
354 			next->bios.rammap_00_16_40 << 14);
355 	ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
356 	ram_mask(hwsq, 0x004008, 0x91ff0000, r004008);
357 
358 	/* XXX: GDDR3 only? */
359 	if (subdev->device->chipset >= 0x92)
360 		ram_wr32(hwsq, 0x100da0, r100da0);
361 
362 	nv50_ram_gpio(hwsq, 0x18, !next->bios.ramcfg_FBVDDQ);
363 	ram_nsec(hwsq, 64000); /*XXX*/
364 	ram_nsec(hwsq, 32000); /*XXX*/
365 
366 	ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
367 
368 	ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
369 	ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */
370 	ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
371 
372 	ram_nsec(hwsq, 12000);
373 
374 	switch (ram->base.type) {
375 	case NVKM_RAM_TYPE_DDR2:
376 		ram_nuke(hwsq, mr[0]); /* force update */
377 		ram_mask(hwsq, mr[0], 0x000, 0x000);
378 		break;
379 	case NVKM_RAM_TYPE_GDDR3:
380 		ram_nuke(hwsq, mr[1]); /* force update */
381 		ram_wr32(hwsq, mr[1], ram->base.mr[1]);
382 		ram_nuke(hwsq, mr[0]); /* force update */
383 		ram_wr32(hwsq, mr[0], ram->base.mr[0]);
384 		break;
385 	default:
386 		break;
387 	}
388 
389 	ram_mask(hwsq, timing[3], 0xffffffff, timing[3]);
390 	ram_mask(hwsq, timing[1], 0xffffffff, timing[1]);
391 	ram_mask(hwsq, timing[6], 0xffffffff, timing[6]);
392 	ram_mask(hwsq, timing[7], 0xffffffff, timing[7]);
393 	ram_mask(hwsq, timing[8], 0xffffffff, timing[8]);
394 	ram_mask(hwsq, timing[0], 0xffffffff, timing[0]);
395 	ram_mask(hwsq, timing[2], 0xffffffff, timing[2]);
396 	ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);
397 	ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);
398 
399 	if (!next->bios.ramcfg_00_03_02)
400 		ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000);
401 	ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12);
402 
403 	/* XXX: A lot of this could be "chipset"/"ram type" specific stuff */
404 	unk710  = ram_rd32(hwsq, 0x100710) & ~0x00000100;
405 	unk714  = ram_rd32(hwsq, 0x100714) & ~0xf0000020;
406 	unk718  = ram_rd32(hwsq, 0x100718) & ~0x00000100;
407 	unk71c  = ram_rd32(hwsq, 0x10071c) & ~0x00000100;
408 	if (subdev->device->chipset <= 0x96) {
409 		unk710 &= ~0x0000006e;
410 		unk714 &= ~0x00000100;
411 
412 		if (!next->bios.ramcfg_00_03_08)
413 			unk710 |= 0x00000060;
414 		if (!next->bios.ramcfg_FBVDDQ)
415 			unk714 |= 0x00000100;
416 		if ( next->bios.ramcfg_00_04_04)
417 			unk710 |= 0x0000000e;
418 	} else {
419 		unk710 &= ~0x00000001;
420 
421 		if (!next->bios.ramcfg_00_03_08)
422 			unk710 |= 0x00000001;
423 	}
424 
425 	if ( next->bios.ramcfg_00_03_01)
426 		unk71c |= 0x00000100;
427 	if ( next->bios.ramcfg_00_03_02)
428 		unk710 |= 0x00000100;
429 	if (!next->bios.ramcfg_00_03_08)
430 		unk714 |= 0x00000020;
431 	if ( next->bios.ramcfg_00_04_04)
432 		unk714 |= 0x70000000;
433 	if ( next->bios.ramcfg_00_04_20)
434 		unk718 |= 0x00000100;
435 
436 	ram_mask(hwsq, 0x100714, 0xffffffff, unk714);
437 	ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c);
438 	ram_mask(hwsq, 0x100718, 0xffffffff, unk718);
439 	ram_mask(hwsq, 0x100710, 0xffffffff, unk710);
440 
441 	/* XXX: G94 does not even test these regs in trace. Harmless we do it,
442 	 * but why is it omitted? */
443 	if (next->bios.rammap_00_16_20) {
444 		ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 |
445 					 next->bios.ramcfg_00_06 << 8 |
446 					 next->bios.ramcfg_00_05);
447 		ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 |
448 					 next->bios.ramcfg_00_08);
449 		ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000);
450 	} else {
451 		ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000);
452 	}
453 	ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]);
454 
455 	if (!next->bios.timing_10_ODT)
456 		nv50_ram_gpio(hwsq, 0x2e, 0);
457 
458 	/* Reset DLL */
459 	if (!next->bios.ramcfg_DLLoff)
460 		nvkm_sddr2_dll_reset(hwsq);
461 
462 	ram_setf(hwsq, 0x10, 0x01); /* enable fb */
463 	ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
464 	ram_wr32(hwsq, 0x611200, 0x00003330);
465 	ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
466 
467 	if (next->bios.rammap_00_17_02)
468 		ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800);
469 	if (!next->bios.rammap_00_16_40)
470 		ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000);
471 	if (next->bios.ramcfg_00_03_02)
472 		ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000);
473 	if (subdev->device->chipset <= 0x96 && next->bios.ramcfg_00_03_02)
474 		ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200);
475 
476 	return 0;
477 }
478 
479 static int
480 nv50_ram_prog(struct nvkm_ram *base)
481 {
482 	struct nv50_ram *ram = nv50_ram(base);
483 	struct nvkm_device *device = ram->base.fb->subdev.device;
484 	ram_exec(&ram->hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
485 	return 0;
486 }
487 
488 static void
489 nv50_ram_tidy(struct nvkm_ram *base)
490 {
491 	struct nv50_ram *ram = nv50_ram(base);
492 	ram_exec(&ram->hwsq, false);
493 }
494 
495 static const struct nvkm_ram_func
496 nv50_ram_func = {
497 	.calc = nv50_ram_calc,
498 	.prog = nv50_ram_prog,
499 	.tidy = nv50_ram_tidy,
500 };
501 
502 static u32
503 nv50_fb_vram_rblock(struct nvkm_ram *ram)
504 {
505 	struct nvkm_subdev *subdev = &ram->fb->subdev;
506 	struct nvkm_device *device = subdev->device;
507 	int colbits, rowbitsa, rowbitsb, banks;
508 	u64 rowsize, predicted;
509 	u32 r0, r4, rt, rblock_size;
510 
511 	r0 = nvkm_rd32(device, 0x100200);
512 	r4 = nvkm_rd32(device, 0x100204);
513 	rt = nvkm_rd32(device, 0x100250);
514 	nvkm_debug(subdev, "memcfg %08x %08x %08x %08x\n",
515 		   r0, r4, rt, nvkm_rd32(device, 0x001540));
516 
517 	colbits  =  (r4 & 0x0000f000) >> 12;
518 	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
519 	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
520 	banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);
521 
522 	rowsize = ram->parts * banks * (1 << colbits) * 8;
523 	predicted = rowsize << rowbitsa;
524 	if (r0 & 0x00000004)
525 		predicted += rowsize << rowbitsb;
526 
527 	if (predicted != ram->size) {
528 		nvkm_warn(subdev, "memory controller reports %d MiB VRAM\n",
529 			  (u32)(ram->size >> 20));
530 	}
531 
532 	rblock_size = rowsize;
533 	if (rt & 1)
534 		rblock_size *= 3;
535 
536 	nvkm_debug(subdev, "rblock %d bytes\n", rblock_size);
537 	return rblock_size;
538 }
539 
540 int
541 nv50_ram_ctor(const struct nvkm_ram_func *func,
542 	      struct nvkm_fb *fb, struct nvkm_ram *ram)
543 {
544 	struct nvkm_device *device = fb->subdev.device;
545 	struct nvkm_bios *bios = device->bios;
546 	const u32 rsvd_head = ( 256 * 1024); /* vga memory */
547 	const u32 rsvd_tail = (1024 * 1024); /* vbios etc */
548 	u64 size = nvkm_rd32(device, 0x10020c);
549 	enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN;
550 	int ret;
551 
552 	switch (nvkm_rd32(device, 0x100714) & 0x00000007) {
553 	case 0: type = NVKM_RAM_TYPE_DDR1; break;
554 	case 1:
555 		if (nvkm_fb_bios_memtype(bios) == NVKM_RAM_TYPE_DDR3)
556 			type = NVKM_RAM_TYPE_DDR3;
557 		else
558 			type = NVKM_RAM_TYPE_DDR2;
559 		break;
560 	case 2: type = NVKM_RAM_TYPE_GDDR3; break;
561 	case 3: type = NVKM_RAM_TYPE_GDDR4; break;
562 	case 4: type = NVKM_RAM_TYPE_GDDR5; break;
563 	default:
564 		break;
565 	}
566 
567 	size = (size & 0x000000ff) << 32 | (size & 0xffffff00);
568 
569 	ret = nvkm_ram_ctor(func, fb, type, size, ram);
570 	if (ret)
571 		return ret;
572 
573 	ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16;
574 	ram->parts = hweight8(ram->part_mask);
575 	ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1;
576 	nvkm_mm_fini(&ram->vram);
577 
578 	return nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
579 			    rsvd_head >> NVKM_RAM_MM_SHIFT,
580 			    (size - rsvd_head - rsvd_tail) >> NVKM_RAM_MM_SHIFT,
581 			    nv50_fb_vram_rblock(ram) >> NVKM_RAM_MM_SHIFT);
582 }
583 
584 int
585 nv50_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
586 {
587 	struct nv50_ram *ram;
588 	int ret, i;
589 
590 	if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
591 		return -ENOMEM;
592 	*pram = &ram->base;
593 
594 	ret = nv50_ram_ctor(&nv50_ram_func, fb, &ram->base);
595 	if (ret)
596 		return ret;
597 
598 	ram->hwsq.r_0x002504 = hwsq_reg(0x002504);
599 	ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
600 	ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
601 	ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
602 	ram->hwsq.r_0x100200 = hwsq_reg(0x100200);
603 	ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
604 	ram->hwsq.r_0x10021c = hwsq_reg(0x10021c);
605 	ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
606 	ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
607 	ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
608 	ram->hwsq.r_0x10053c = hwsq_reg(0x10053c);
609 	ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0);
610 	ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4);
611 	ram->hwsq.r_0x100710 = hwsq_reg(0x100710);
612 	ram->hwsq.r_0x100714 = hwsq_reg(0x100714);
613 	ram->hwsq.r_0x100718 = hwsq_reg(0x100718);
614 	ram->hwsq.r_0x10071c = hwsq_reg(0x10071c);
615 	ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask);
616 	ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
617 	ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
618 	ram->hwsq.r_0x611200 = hwsq_reg(0x611200);
619 
620 	for (i = 0; i < 9; i++)
621 		ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));
622 
623 	if (ram->base.ranks > 1) {
624 		ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);
625 		ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);
626 		ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);
627 		ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);
628 	} else {
629 		ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);
630 		ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);
631 		ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);
632 		ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);
633 	}
634 
635 	ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104);
636 	ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108);
637 	ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120);
638 	ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124);
639 
640 	return 0;
641 }
642