1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #define nv50_ram(p) container_of((p), struct nv50_ram, base) 25 #include "ram.h" 26 #include "ramseq.h" 27 #include "nv50.h" 28 29 #include <core/option.h> 30 #include <subdev/bios.h> 31 #include <subdev/bios/perf.h> 32 #include <subdev/bios/pll.h> 33 #include <subdev/bios/rammap.h> 34 #include <subdev/bios/timing.h> 35 #include <subdev/clk/pll.h> 36 #include <subdev/gpio.h> 37 38 struct nv50_ramseq { 39 struct hwsq base; 40 struct hwsq_reg r_0x002504; 41 struct hwsq_reg r_0x004008; 42 struct hwsq_reg r_0x00400c; 43 struct hwsq_reg r_0x00c040; 44 struct hwsq_reg r_0x100200; 45 struct hwsq_reg r_0x100210; 46 struct hwsq_reg r_0x10021c; 47 struct hwsq_reg r_0x1002d0; 48 struct hwsq_reg r_0x1002d4; 49 struct hwsq_reg r_0x1002dc; 50 struct hwsq_reg r_0x10053c; 51 struct hwsq_reg r_0x1005a0; 52 struct hwsq_reg r_0x1005a4; 53 struct hwsq_reg r_0x100710; 54 struct hwsq_reg r_0x100714; 55 struct hwsq_reg r_0x100718; 56 struct hwsq_reg r_0x10071c; 57 struct hwsq_reg r_0x100da0; 58 struct hwsq_reg r_0x100e20; 59 struct hwsq_reg r_0x100e24; 60 struct hwsq_reg r_0x611200; 61 struct hwsq_reg r_timing[9]; 62 struct hwsq_reg r_mr[4]; 63 struct hwsq_reg r_gpio[4]; 64 }; 65 66 struct nv50_ram { 67 struct nvkm_ram base; 68 struct nv50_ramseq hwsq; 69 }; 70 71 #define T(t) cfg->timing_10_##t 72 static int 73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) 74 { 75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; 76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; 77 struct nvkm_device *device = subdev->device; 78 u32 cur2, cur4, cur7, cur8; 79 u8 unkt3b; 80 81 cur2 = nvkm_rd32(device, 0x100228); 82 cur4 = nvkm_rd32(device, 0x100230); 83 cur7 = nvkm_rd32(device, 0x10023c); 84 cur8 = nvkm_rd32(device, 0x100240); 85 86 switch ((!T(CWL)) * ram->base.type) { 87 case NVKM_RAM_TYPE_DDR2: 88 T(CWL) = T(CL) - 1; 89 break; 90 case NVKM_RAM_TYPE_GDDR3: 91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; 92 break; 93 } 94 95 /* XXX: N=1 is not proper statistics */ 96 if (device->chipset == 0xa0) { 97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; 98 timing[6] = (0x2d + T(CL) - T(CWL) + 99 ram->base.next->bios.rammap_00_16_40) << 16 | 100 T(CWL) << 8 | 101 (0x2f + T(CL) - T(CWL)); 102 } else { 103 unkt3b = 0x16; 104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | 105 max_t(s8, T(CWL) - 2, 1) << 8 | 106 (0x2e + T(CL) - T(CWL)); 107 } 108 109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 111 max_t(u8, T(18), 1) << 16 | 112 (T(WTR) + 1 + T(CWL)) << 8 | 113 (3 + T(CL) - T(CWL)); 114 timing[2] = (T(CWL) - 1) << 24 | 115 (T(RRD) << 16) | 116 (T(RCDWR) << 8) | 117 T(RCDRD); 118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | 119 unkt3b << 16 | 120 (T(CL) - 1) << 8 | 121 (T(CL) - 1); 122 timing[4] = (cur4 & 0xffff0000) | 123 T(13) << 8 | 124 T(13); 125 timing[5] = T(RFC) << 24 | 126 max_t(u8, T(RCDRD), T(RCDWR)) << 16 | 127 T(RP); 128 /* Timing 6 is already done above */ 129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; 130 timing[8] = (cur8 & 0xffffff00); 131 132 /* XXX: P.version == 1 only has DDR2 and GDDR3? */ 133 if (ram->base.type == NVKM_RAM_TYPE_DDR2) { 134 timing[5] |= (T(CL) + 3) << 8; 135 timing[8] |= (T(CL) - 4); 136 } else 137 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { 138 timing[5] |= (T(CL) + 2) << 8; 139 timing[8] |= (T(CL) - 2); 140 } 141 142 nvkm_debug(subdev, " 220: %08x %08x %08x %08x\n", 143 timing[0], timing[1], timing[2], timing[3]); 144 nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n", 145 timing[4], timing[5], timing[6], timing[7]); 146 nvkm_debug(subdev, " 240: %08x\n", timing[8]); 147 return 0; 148 } 149 150 static int 151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) 152 { 153 unsigned int i; 154 struct nvbios_ramcfg *cfg = &ram->base.target.bios; 155 struct nvkm_subdev *subdev = &ram->base.fb->subdev; 156 struct nvkm_device *device = subdev->device; 157 158 for (i = 0; i <= 8; i++) 159 timing[i] = nvkm_rd32(device, 0x100220 + (i * 4)); 160 161 /* Derive the bare minimum for the MR calculation to succeed */ 162 cfg->timing_ver = 0x10; 163 T(CL) = (timing[3] & 0xff) + 1; 164 165 switch (ram->base.type) { 166 case NVKM_RAM_TYPE_DDR2: 167 T(CWL) = T(CL) - 1; 168 break; 169 case NVKM_RAM_TYPE_GDDR3: 170 T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; 171 break; 172 default: 173 return -ENOSYS; 174 break; 175 } 176 177 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); 178 179 return 0; 180 } 181 #undef T 182 183 static void 184 nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) 185 { 186 ram_mask(hwsq, mr[0], 0x100, 0x100); 187 ram_mask(hwsq, mr[0], 0x100, 0x000); 188 ram_nsec(hwsq, 24000); 189 } 190 191 static void 192 nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val) 193 { 194 struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio; 195 struct dcb_gpio_func func; 196 u32 reg, sh, gpio_val; 197 int ret; 198 199 if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) { 200 ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func); 201 if (ret) 202 return; 203 204 reg = func.line >> 3; 205 sh = (func.line & 0x7) << 2; 206 gpio_val = ram_rd32(hwsq, gpio[reg]); 207 208 if (gpio_val & (8 << sh)) 209 val = !val; 210 if (!(func.log[1] & 1)) 211 val = !val; 212 213 ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); 214 ram_nsec(hwsq, 20000); 215 } 216 } 217 218 static int 219 nv50_ram_calc(struct nvkm_ram *base, u32 freq) 220 { 221 struct nv50_ram *ram = nv50_ram(base); 222 struct nv50_ramseq *hwsq = &ram->hwsq; 223 struct nvkm_subdev *subdev = &ram->base.fb->subdev; 224 struct nvkm_bios *bios = subdev->device->bios; 225 struct nvbios_perfE perfE; 226 struct nvbios_pll mpll; 227 struct nvkm_ram_data *next; 228 u8 ver, hdr, cnt, len, strap, size; 229 u32 data; 230 u32 r100da0, r004008, unk710, unk714, unk718, unk71c; 231 int N1, M1, N2, M2, P; 232 int ret, i; 233 u32 timing[9]; 234 235 next = &ram->base.target; 236 next->freq = freq; 237 ram->base.next = next; 238 239 /* lookup closest matching performance table entry for frequency */ 240 i = 0; 241 do { 242 data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, 243 &size, &perfE); 244 if (!data || (ver < 0x25 || ver >= 0x40) || 245 (size < 2)) { 246 nvkm_error(subdev, "invalid/missing perftab entry\n"); 247 return -EINVAL; 248 } 249 } while (perfE.memory < freq); 250 251 nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios); 252 253 /* locate specific data set for the attached memory */ 254 strap = nvbios_ramcfg_index(subdev); 255 if (strap >= cnt) { 256 nvkm_error(subdev, "invalid ramcfg strap\n"); 257 return -EINVAL; 258 } 259 260 data = nvbios_rammapSp_from_perf(bios, data + hdr, size, strap, 261 &next->bios); 262 if (!data) { 263 nvkm_error(subdev, "invalid/missing rammap entry "); 264 return -EINVAL; 265 } 266 267 /* lookup memory timings, if bios says they're present */ 268 if (next->bios.ramcfg_timing != 0xff) { 269 data = nvbios_timingEp(bios, next->bios.ramcfg_timing, 270 &ver, &hdr, &cnt, &len, &next->bios); 271 if (!data || ver != 0x10 || hdr < 0x12) { 272 nvkm_error(subdev, "invalid/missing timing entry " 273 "%02x %04x %02x %02x\n", 274 strap, data, ver, hdr); 275 return -EINVAL; 276 } 277 nv50_ram_timing_calc(ram, timing); 278 } else { 279 nv50_ram_timing_read(ram, timing); 280 } 281 282 ret = ram_init(hwsq, subdev); 283 if (ret) 284 return ret; 285 286 /* Determine ram-specific MR values */ 287 ram->base.mr[0] = ram_rd32(hwsq, mr[0]); 288 ram->base.mr[1] = ram_rd32(hwsq, mr[1]); 289 ram->base.mr[2] = ram_rd32(hwsq, mr[2]); 290 291 switch (ram->base.type) { 292 case NVKM_RAM_TYPE_GDDR3: 293 ret = nvkm_gddr3_calc(&ram->base); 294 break; 295 default: 296 ret = -ENOSYS; 297 break; 298 } 299 300 if (ret) { 301 nvkm_error(subdev, "Could not calculate MR\n"); 302 return ret; 303 } 304 305 if (subdev->device->chipset <= 0x96 && !next->bios.ramcfg_00_03_02) 306 ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000); 307 308 /* Always disable this bit during reclock */ 309 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000); 310 311 ram_wait_vblank(hwsq); 312 ram_wr32(hwsq, 0x611200, 0x00003300); 313 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ 314 ram_nsec(hwsq, 8000); 315 ram_setf(hwsq, 0x10, 0x00); /* disable fb */ 316 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 317 ram_nsec(hwsq, 2000); 318 319 if (next->bios.timing_10_ODT) 320 nv50_ram_gpio(hwsq, 0x2e, 1); 321 322 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ 323 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ 324 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ 325 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */ 326 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */ 327 328 ret = nvbios_pll_parse(bios, 0x004008, &mpll); 329 mpll.vco2.max_freq = 0; 330 if (ret >= 0) { 331 ret = nv04_pll_calc(subdev, &mpll, freq, 332 &N1, &M1, &N2, &M2, &P); 333 if (ret <= 0) 334 ret = -EINVAL; 335 } 336 337 if (ret < 0) 338 return ret; 339 340 /* XXX: 750MHz seems rather arbitrary */ 341 if (freq <= 750000) { 342 r100da0 = 0x00000010; 343 r004008 = 0x90000000; 344 } else { 345 r100da0 = 0x00000000; 346 r004008 = 0x80000000; 347 } 348 349 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); 350 351 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000); 352 /* XXX: Is rammap_00_16_40 the DLL bit we've seen in GT215? Why does 353 * it have a different rammap bit from DLLoff? */ 354 ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 | 355 next->bios.rammap_00_16_40 << 14); 356 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); 357 ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); 358 359 /* XXX: GDDR3 only? */ 360 if (subdev->device->chipset >= 0x92) 361 ram_wr32(hwsq, 0x100da0, r100da0); 362 363 nv50_ram_gpio(hwsq, 0x18, !next->bios.ramcfg_FBVDDQ); 364 ram_nsec(hwsq, 64000); /*XXX*/ 365 ram_nsec(hwsq, 32000); /*XXX*/ 366 367 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000); 368 369 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */ 370 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */ 371 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */ 372 373 ram_nsec(hwsq, 12000); 374 375 switch (ram->base.type) { 376 case NVKM_RAM_TYPE_DDR2: 377 ram_nuke(hwsq, mr[0]); /* force update */ 378 ram_mask(hwsq, mr[0], 0x000, 0x000); 379 break; 380 case NVKM_RAM_TYPE_GDDR3: 381 ram_nuke(hwsq, mr[1]); /* force update */ 382 ram_wr32(hwsq, mr[1], ram->base.mr[1]); 383 ram_nuke(hwsq, mr[0]); /* force update */ 384 ram_wr32(hwsq, mr[0], ram->base.mr[0]); 385 break; 386 default: 387 break; 388 } 389 390 ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); 391 ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); 392 ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); 393 ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); 394 ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); 395 ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); 396 ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); 397 ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); 398 ram_mask(hwsq, timing[5], 0xffffffff, timing[5]); 399 400 if (!next->bios.ramcfg_00_03_02) 401 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000); 402 ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12); 403 404 /* XXX: A lot of this could be "chipset"/"ram type" specific stuff */ 405 unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000100; 406 unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020; 407 unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100; 408 unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100; 409 if (subdev->device->chipset <= 0x96) { 410 unk710 &= ~0x0000006e; 411 unk714 &= ~0x00000100; 412 413 if (!next->bios.ramcfg_00_03_08) 414 unk710 |= 0x00000060; 415 if (!next->bios.ramcfg_FBVDDQ) 416 unk714 |= 0x00000100; 417 if ( next->bios.ramcfg_00_04_04) 418 unk710 |= 0x0000000e; 419 } else { 420 unk710 &= ~0x00000001; 421 422 if (!next->bios.ramcfg_00_03_08) 423 unk710 |= 0x00000001; 424 } 425 426 if ( next->bios.ramcfg_00_03_01) 427 unk71c |= 0x00000100; 428 if ( next->bios.ramcfg_00_03_02) 429 unk710 |= 0x00000100; 430 if (!next->bios.ramcfg_00_03_08) 431 unk714 |= 0x00000020; 432 if ( next->bios.ramcfg_00_04_04) 433 unk714 |= 0x70000000; 434 if ( next->bios.ramcfg_00_04_20) 435 unk718 |= 0x00000100; 436 437 ram_mask(hwsq, 0x100714, 0xffffffff, unk714); 438 ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c); 439 ram_mask(hwsq, 0x100718, 0xffffffff, unk718); 440 ram_mask(hwsq, 0x100710, 0xffffffff, unk710); 441 442 /* XXX: G94 does not even test these regs in trace. Harmless we do it, 443 * but why is it omitted? */ 444 if (next->bios.rammap_00_16_20) { 445 ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 | 446 next->bios.ramcfg_00_06 << 8 | 447 next->bios.ramcfg_00_05); 448 ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 | 449 next->bios.ramcfg_00_08); 450 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000); 451 } else { 452 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000); 453 } 454 ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); 455 456 if (!next->bios.timing_10_ODT) 457 nv50_ram_gpio(hwsq, 0x2e, 0); 458 459 /* Reset DLL */ 460 if (!next->bios.ramcfg_DLLoff) 461 nvkm_sddr2_dll_reset(hwsq); 462 463 ram_setf(hwsq, 0x10, 0x01); /* enable fb */ 464 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 465 ram_wr32(hwsq, 0x611200, 0x00003330); 466 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */ 467 468 if (next->bios.rammap_00_17_02) 469 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800); 470 if (!next->bios.rammap_00_16_40) 471 ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000); 472 if (next->bios.ramcfg_00_03_02) 473 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000); 474 if (subdev->device->chipset <= 0x96 && next->bios.ramcfg_00_03_02) 475 ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200); 476 477 return 0; 478 } 479 480 static int 481 nv50_ram_prog(struct nvkm_ram *base) 482 { 483 struct nv50_ram *ram = nv50_ram(base); 484 struct nvkm_device *device = ram->base.fb->subdev.device; 485 ram_exec(&ram->hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); 486 return 0; 487 } 488 489 static void 490 nv50_ram_tidy(struct nvkm_ram *base) 491 { 492 struct nv50_ram *ram = nv50_ram(base); 493 ram_exec(&ram->hwsq, false); 494 } 495 496 static const struct nvkm_ram_func 497 nv50_ram_func = { 498 .calc = nv50_ram_calc, 499 .prog = nv50_ram_prog, 500 .tidy = nv50_ram_tidy, 501 }; 502 503 static u32 504 nv50_fb_vram_rblock(struct nvkm_ram *ram) 505 { 506 struct nvkm_subdev *subdev = &ram->fb->subdev; 507 struct nvkm_device *device = subdev->device; 508 int colbits, rowbitsa, rowbitsb, banks; 509 u64 rowsize, predicted; 510 u32 r0, r4, rt, rblock_size; 511 512 r0 = nvkm_rd32(device, 0x100200); 513 r4 = nvkm_rd32(device, 0x100204); 514 rt = nvkm_rd32(device, 0x100250); 515 nvkm_debug(subdev, "memcfg %08x %08x %08x %08x\n", 516 r0, r4, rt, nvkm_rd32(device, 0x001540)); 517 518 colbits = (r4 & 0x0000f000) >> 12; 519 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; 520 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; 521 banks = 1 << (((r4 & 0x03000000) >> 24) + 2); 522 523 rowsize = ram->parts * banks * (1 << colbits) * 8; 524 predicted = rowsize << rowbitsa; 525 if (r0 & 0x00000004) 526 predicted += rowsize << rowbitsb; 527 528 if (predicted != ram->size) { 529 nvkm_warn(subdev, "memory controller reports %d MiB VRAM\n", 530 (u32)(ram->size >> 20)); 531 } 532 533 rblock_size = rowsize; 534 if (rt & 1) 535 rblock_size *= 3; 536 537 nvkm_debug(subdev, "rblock %d bytes\n", rblock_size); 538 return rblock_size; 539 } 540 541 int 542 nv50_ram_ctor(const struct nvkm_ram_func *func, 543 struct nvkm_fb *fb, struct nvkm_ram *ram) 544 { 545 struct nvkm_device *device = fb->subdev.device; 546 struct nvkm_bios *bios = device->bios; 547 const u32 rsvd_head = ( 256 * 1024); /* vga memory */ 548 const u32 rsvd_tail = (1024 * 1024); /* vbios etc */ 549 u64 size = nvkm_rd32(device, 0x10020c); 550 enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; 551 int ret; 552 553 switch (nvkm_rd32(device, 0x100714) & 0x00000007) { 554 case 0: type = NVKM_RAM_TYPE_DDR1; break; 555 case 1: 556 if (nvkm_fb_bios_memtype(bios) == NVKM_RAM_TYPE_DDR3) 557 type = NVKM_RAM_TYPE_DDR3; 558 else 559 type = NVKM_RAM_TYPE_DDR2; 560 break; 561 case 2: type = NVKM_RAM_TYPE_GDDR3; break; 562 case 3: type = NVKM_RAM_TYPE_GDDR4; break; 563 case 4: type = NVKM_RAM_TYPE_GDDR5; break; 564 default: 565 break; 566 } 567 568 size = (size & 0x000000ff) << 32 | (size & 0xffffff00); 569 570 ret = nvkm_ram_ctor(func, fb, type, size, ram); 571 if (ret) 572 return ret; 573 574 ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; 575 ram->parts = hweight8(ram->part_mask); 576 ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1; 577 nvkm_mm_fini(&ram->vram); 578 579 return nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL, 580 rsvd_head >> NVKM_RAM_MM_SHIFT, 581 (size - rsvd_head - rsvd_tail) >> NVKM_RAM_MM_SHIFT, 582 nv50_fb_vram_rblock(ram) >> NVKM_RAM_MM_SHIFT); 583 } 584 585 int 586 nv50_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) 587 { 588 struct nv50_ram *ram; 589 int ret, i; 590 591 if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) 592 return -ENOMEM; 593 *pram = &ram->base; 594 595 ret = nv50_ram_ctor(&nv50_ram_func, fb, &ram->base); 596 if (ret) 597 return ret; 598 599 ram->hwsq.r_0x002504 = hwsq_reg(0x002504); 600 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); 601 ram->hwsq.r_0x004008 = hwsq_reg(0x004008); 602 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); 603 ram->hwsq.r_0x100200 = hwsq_reg(0x100200); 604 ram->hwsq.r_0x100210 = hwsq_reg(0x100210); 605 ram->hwsq.r_0x10021c = hwsq_reg(0x10021c); 606 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); 607 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); 608 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); 609 ram->hwsq.r_0x10053c = hwsq_reg(0x10053c); 610 ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0); 611 ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4); 612 ram->hwsq.r_0x100710 = hwsq_reg(0x100710); 613 ram->hwsq.r_0x100714 = hwsq_reg(0x100714); 614 ram->hwsq.r_0x100718 = hwsq_reg(0x100718); 615 ram->hwsq.r_0x10071c = hwsq_reg(0x10071c); 616 ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask); 617 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); 618 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); 619 ram->hwsq.r_0x611200 = hwsq_reg(0x611200); 620 621 for (i = 0; i < 9; i++) 622 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); 623 624 if (ram->base.ranks > 1) { 625 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8); 626 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc); 627 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8); 628 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec); 629 } else { 630 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); 631 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); 632 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); 633 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); 634 } 635 636 ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104); 637 ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108); 638 ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120); 639 ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124); 640 641 return 0; 642 } 643