1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "ramseq.h" 26 27 #include <core/option.h> 28 #include <subdev/bios.h> 29 #include <subdev/bios/perf.h> 30 #include <subdev/bios/pll.h> 31 #include <subdev/bios/rammap.h> 32 #include <subdev/bios/timing.h> 33 #include <subdev/clk/pll.h> 34 35 struct nv50_ramseq { 36 struct hwsq base; 37 struct hwsq_reg r_0x002504; 38 struct hwsq_reg r_0x004008; 39 struct hwsq_reg r_0x00400c; 40 struct hwsq_reg r_0x00c040; 41 struct hwsq_reg r_0x100200; 42 struct hwsq_reg r_0x100210; 43 struct hwsq_reg r_0x10021c; 44 struct hwsq_reg r_0x1002d0; 45 struct hwsq_reg r_0x1002d4; 46 struct hwsq_reg r_0x1002dc; 47 struct hwsq_reg r_0x10053c; 48 struct hwsq_reg r_0x1005a0; 49 struct hwsq_reg r_0x1005a4; 50 struct hwsq_reg r_0x100710; 51 struct hwsq_reg r_0x100714; 52 struct hwsq_reg r_0x100718; 53 struct hwsq_reg r_0x10071c; 54 struct hwsq_reg r_0x100da0; 55 struct hwsq_reg r_0x100e20; 56 struct hwsq_reg r_0x100e24; 57 struct hwsq_reg r_0x611200; 58 struct hwsq_reg r_timing[9]; 59 struct hwsq_reg r_mr[4]; 60 }; 61 62 struct nv50_ram { 63 struct nvkm_ram base; 64 struct nv50_ramseq hwsq; 65 }; 66 67 #define T(t) cfg->timing_10_##t 68 static int 69 nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) 70 { 71 struct nv50_ram *ram = (void *)fb->ram; 72 struct nvbios_ramcfg *cfg = &ram->base.target.bios; 73 struct nvkm_subdev *subdev = &fb->subdev; 74 struct nvkm_device *device = subdev->device; 75 u32 cur2, cur4, cur7, cur8; 76 u8 unkt3b; 77 78 cur2 = nvkm_rd32(device, 0x100228); 79 cur4 = nvkm_rd32(device, 0x100230); 80 cur7 = nvkm_rd32(device, 0x10023c); 81 cur8 = nvkm_rd32(device, 0x100240); 82 83 switch ((!T(CWL)) * ram->base.type) { 84 case NV_MEM_TYPE_DDR2: 85 T(CWL) = T(CL) - 1; 86 break; 87 case NV_MEM_TYPE_GDDR3: 88 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; 89 break; 90 } 91 92 /* XXX: N=1 is not proper statistics */ 93 if (nv_device(fb)->chipset == 0xa0) { 94 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; 95 timing[6] = (0x2d + T(CL) - T(CWL) + 96 ram->base.next->bios.rammap_00_16_40) << 16 | 97 T(CWL) << 8 | 98 (0x2f + T(CL) - T(CWL)); 99 } else { 100 unkt3b = 0x16; 101 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | 102 max_t(s8, T(CWL) - 2, 1) << 8 | 103 (0x2e + T(CL) - T(CWL)); 104 } 105 106 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 107 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 108 max_t(u8, T(18), 1) << 16 | 109 (T(WTR) + 1 + T(CWL)) << 8 | 110 (3 + T(CL) - T(CWL)); 111 timing[2] = (T(CWL) - 1) << 24 | 112 (T(RRD) << 16) | 113 (T(RCDWR) << 8) | 114 T(RCDRD); 115 timing[3] = (unkt3b - 2 + T(CL)) << 24 | 116 unkt3b << 16 | 117 (T(CL) - 1) << 8 | 118 (T(CL) - 1); 119 timing[4] = (cur4 & 0xffff0000) | 120 T(13) << 8 | 121 T(13); 122 timing[5] = T(RFC) << 24 | 123 max_t(u8, T(RCDRD), T(RCDWR)) << 16 | 124 T(RP); 125 /* Timing 6 is already done above */ 126 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; 127 timing[8] = (cur8 & 0xffffff00); 128 129 /* XXX: P.version == 1 only has DDR2 and GDDR3? */ 130 if (fb->ram->type == NV_MEM_TYPE_DDR2) { 131 timing[5] |= (T(CL) + 3) << 8; 132 timing[8] |= (T(CL) - 4); 133 } else if (fb->ram->type == NV_MEM_TYPE_GDDR3) { 134 timing[5] |= (T(CL) + 2) << 8; 135 timing[8] |= (T(CL) - 2); 136 } 137 138 nvkm_debug(subdev, " 220: %08x %08x %08x %08x\n", 139 timing[0], timing[1], timing[2], timing[3]); 140 nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n", 141 timing[4], timing[5], timing[6], timing[7]); 142 nvkm_debug(subdev, " 240: %08x\n", timing[8]); 143 return 0; 144 } 145 #undef T 146 147 static void 148 nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) 149 { 150 ram_mask(hwsq, mr[0], 0x100, 0x100); 151 ram_mask(hwsq, mr[0], 0x100, 0x000); 152 ram_nsec(hwsq, 24000); 153 } 154 155 static int 156 nv50_ram_calc(struct nvkm_fb *fb, u32 freq) 157 { 158 struct nv50_ram *ram = (void *)fb->ram; 159 struct nv50_ramseq *hwsq = &ram->hwsq; 160 struct nvkm_subdev *subdev = &fb->subdev; 161 struct nvkm_bios *bios = subdev->device->bios; 162 struct nvbios_perfE perfE; 163 struct nvbios_pll mpll; 164 struct nvkm_ram_data *next; 165 u8 ver, hdr, cnt, len, strap, size; 166 u32 data; 167 u32 r100da0, r004008, unk710, unk714, unk718, unk71c; 168 int N1, M1, N2, M2, P; 169 int ret, i; 170 u32 timing[9]; 171 172 next = &ram->base.target; 173 next->freq = freq; 174 ram->base.next = next; 175 176 /* lookup closest matching performance table entry for frequency */ 177 i = 0; 178 do { 179 data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, 180 &size, &perfE); 181 if (!data || (ver < 0x25 || ver >= 0x40) || 182 (size < 2)) { 183 nvkm_error(subdev, "invalid/missing perftab entry\n"); 184 return -EINVAL; 185 } 186 } while (perfE.memory < freq); 187 188 nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios); 189 190 /* locate specific data set for the attached memory */ 191 strap = nvbios_ramcfg_index(nv_subdev(fb)); 192 if (strap >= cnt) { 193 nvkm_error(subdev, "invalid ramcfg strap\n"); 194 return -EINVAL; 195 } 196 197 data = nvbios_rammapSp_from_perf(bios, data + hdr, size, strap, 198 &next->bios); 199 if (!data) { 200 nvkm_error(subdev, "invalid/missing rammap entry "); 201 return -EINVAL; 202 } 203 204 /* lookup memory timings, if bios says they're present */ 205 if (next->bios.ramcfg_timing != 0xff) { 206 data = nvbios_timingEp(bios, next->bios.ramcfg_timing, 207 &ver, &hdr, &cnt, &len, &next->bios); 208 if (!data || ver != 0x10 || hdr < 0x12) { 209 nvkm_error(subdev, "invalid/missing timing entry " 210 "%02x %04x %02x %02x\n", 211 strap, data, ver, hdr); 212 return -EINVAL; 213 } 214 } 215 216 nv50_ram_timing_calc(fb, timing); 217 218 ret = ram_init(hwsq, nv_subdev(fb)); 219 if (ret) 220 return ret; 221 222 /* Determine ram-specific MR values */ 223 ram->base.mr[0] = ram_rd32(hwsq, mr[0]); 224 ram->base.mr[1] = ram_rd32(hwsq, mr[1]); 225 ram->base.mr[2] = ram_rd32(hwsq, mr[2]); 226 227 switch (ram->base.type) { 228 case NV_MEM_TYPE_GDDR3: 229 ret = nvkm_gddr3_calc(&ram->base); 230 break; 231 default: 232 ret = -ENOSYS; 233 break; 234 } 235 236 if (ret) 237 return ret; 238 239 /* Always disable this bit during reclock */ 240 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000); 241 242 ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */ 243 ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */ 244 ram_wr32(hwsq, 0x611200, 0x00003300); 245 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ 246 ram_nsec(hwsq, 8000); 247 ram_setf(hwsq, 0x10, 0x00); /* disable fb */ 248 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 249 ram_nsec(hwsq, 2000); 250 251 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ 252 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ 253 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ 254 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */ 255 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */ 256 257 ret = nvbios_pll_parse(bios, 0x004008, &mpll); 258 mpll.vco2.max_freq = 0; 259 if (ret >= 0) { 260 ret = nv04_pll_calc(nv_subdev(fb), &mpll, freq, 261 &N1, &M1, &N2, &M2, &P); 262 if (ret <= 0) 263 ret = -EINVAL; 264 } 265 266 if (ret < 0) 267 return ret; 268 269 /* XXX: 750MHz seems rather arbitrary */ 270 if (freq <= 750000) { 271 r100da0 = 0x00000010; 272 r004008 = 0x90000000; 273 } else { 274 r100da0 = 0x00000000; 275 r004008 = 0x80000000; 276 } 277 278 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); 279 280 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000); 281 /* XXX: Is rammap_00_16_40 the DLL bit we've seen in GT215? Why does 282 * it have a different rammap bit from DLLoff? */ 283 ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 | 284 next->bios.rammap_00_16_40 << 14); 285 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); 286 ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); 287 if (nv_device(fb)->chipset >= 0x96) 288 ram_wr32(hwsq, 0x100da0, r100da0); 289 ram_nsec(hwsq, 64000); /*XXX*/ 290 ram_nsec(hwsq, 32000); /*XXX*/ 291 292 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000); 293 294 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */ 295 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */ 296 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */ 297 298 ram_nsec(hwsq, 12000); 299 300 switch (ram->base.type) { 301 case NV_MEM_TYPE_DDR2: 302 ram_nuke(hwsq, mr[0]); /* force update */ 303 ram_mask(hwsq, mr[0], 0x000, 0x000); 304 break; 305 case NV_MEM_TYPE_GDDR3: 306 ram_nuke(hwsq, mr[1]); /* force update */ 307 ram_wr32(hwsq, mr[1], ram->base.mr[1]); 308 ram_nuke(hwsq, mr[0]); /* force update */ 309 ram_wr32(hwsq, mr[0], ram->base.mr[0]); 310 break; 311 default: 312 break; 313 } 314 315 ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); 316 ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); 317 ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); 318 ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); 319 ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); 320 ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); 321 ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); 322 ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); 323 ram_mask(hwsq, timing[5], 0xffffffff, timing[5]); 324 325 if (!next->bios.ramcfg_00_03_02) 326 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000); 327 ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12); 328 329 /* XXX: A lot of this could be "chipset"/"ram type" specific stuff */ 330 unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000101; 331 unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020; 332 unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100; 333 unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100; 334 335 if ( next->bios.ramcfg_00_03_01) 336 unk71c |= 0x00000100; 337 if ( next->bios.ramcfg_00_03_02) 338 unk710 |= 0x00000100; 339 if (!next->bios.ramcfg_00_03_08) { 340 unk710 |= 0x1; 341 unk714 |= 0x20; 342 } 343 if ( next->bios.ramcfg_00_04_04) 344 unk714 |= 0x70000000; 345 if ( next->bios.ramcfg_00_04_20) 346 unk718 |= 0x00000100; 347 348 ram_mask(hwsq, 0x100714, 0xffffffff, unk714); 349 ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c); 350 ram_mask(hwsq, 0x100718, 0xffffffff, unk718); 351 ram_mask(hwsq, 0x100710, 0xffffffff, unk710); 352 353 if (next->bios.rammap_00_16_20) { 354 ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 | 355 next->bios.ramcfg_00_06 << 8 | 356 next->bios.ramcfg_00_05); 357 ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 | 358 next->bios.ramcfg_00_08); 359 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000); 360 } else { 361 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000); 362 } 363 ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); 364 365 /* Reset DLL */ 366 if (!next->bios.ramcfg_DLLoff) 367 nvkm_sddr2_dll_reset(hwsq); 368 369 ram_setf(hwsq, 0x10, 0x01); /* enable fb */ 370 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 371 ram_wr32(hwsq, 0x611200, 0x00003330); 372 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */ 373 374 if (next->bios.rammap_00_17_02) 375 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800); 376 if (!next->bios.rammap_00_16_40) 377 ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000); 378 if (next->bios.ramcfg_00_03_02) 379 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000); 380 381 return 0; 382 } 383 384 static int 385 nv50_ram_prog(struct nvkm_fb *fb) 386 { 387 struct nvkm_device *device = nv_device(fb); 388 struct nv50_ram *ram = (void *)fb->ram; 389 struct nv50_ramseq *hwsq = &ram->hwsq; 390 391 ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); 392 return 0; 393 } 394 395 static void 396 nv50_ram_tidy(struct nvkm_fb *fb) 397 { 398 struct nv50_ram *ram = (void *)fb->ram; 399 struct nv50_ramseq *hwsq = &ram->hwsq; 400 ram_exec(hwsq, false); 401 } 402 403 void 404 __nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem *mem) 405 { 406 struct nvkm_mm_node *this; 407 408 while (!list_empty(&mem->regions)) { 409 this = list_first_entry(&mem->regions, typeof(*this), rl_entry); 410 411 list_del(&this->rl_entry); 412 nvkm_mm_free(&fb->vram, &this); 413 } 414 415 nvkm_mm_free(&fb->tags, &mem->tag); 416 } 417 418 void 419 nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) 420 { 421 struct nvkm_mem *mem = *pmem; 422 423 *pmem = NULL; 424 if (unlikely(mem == NULL)) 425 return; 426 427 mutex_lock(&fb->subdev.mutex); 428 __nv50_ram_put(fb, mem); 429 mutex_unlock(&fb->subdev.mutex); 430 431 kfree(mem); 432 } 433 434 int 435 nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, 436 u32 memtype, struct nvkm_mem **pmem) 437 { 438 struct nvkm_mm *heap = &fb->vram; 439 struct nvkm_mm *tags = &fb->tags; 440 struct nvkm_mm_node *r; 441 struct nvkm_mem *mem; 442 int comp = (memtype & 0x300) >> 8; 443 int type = (memtype & 0x07f); 444 int back = (memtype & 0x800); 445 int min, max, ret; 446 447 max = (size >> 12); 448 min = ncmin ? (ncmin >> 12) : max; 449 align >>= 12; 450 451 mem = kzalloc(sizeof(*mem), GFP_KERNEL); 452 if (!mem) 453 return -ENOMEM; 454 455 mutex_lock(&fb->subdev.mutex); 456 if (comp) { 457 if (align == 16) { 458 int n = (max >> 4) * comp; 459 460 ret = nvkm_mm_head(tags, 0, 1, n, n, 1, &mem->tag); 461 if (ret) 462 mem->tag = NULL; 463 } 464 465 if (unlikely(!mem->tag)) 466 comp = 0; 467 } 468 469 INIT_LIST_HEAD(&mem->regions); 470 mem->memtype = (comp << 7) | type; 471 mem->size = max; 472 473 type = nv50_fb_memtype[type]; 474 do { 475 if (back) 476 ret = nvkm_mm_tail(heap, 0, type, max, min, align, &r); 477 else 478 ret = nvkm_mm_head(heap, 0, type, max, min, align, &r); 479 if (ret) { 480 mutex_unlock(&fb->subdev.mutex); 481 fb->ram->put(fb, &mem); 482 return ret; 483 } 484 485 list_add_tail(&r->rl_entry, &mem->regions); 486 max -= r->length; 487 } while (max); 488 mutex_unlock(&fb->subdev.mutex); 489 490 r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); 491 mem->offset = (u64)r->offset << 12; 492 *pmem = mem; 493 return 0; 494 } 495 496 static u32 497 nv50_fb_vram_rblock(struct nvkm_fb *fb, struct nvkm_ram *ram) 498 { 499 struct nvkm_subdev *subdev = &fb->subdev; 500 struct nvkm_device *device = subdev->device; 501 int colbits, rowbitsa, rowbitsb, banks; 502 u64 rowsize, predicted; 503 u32 r0, r4, rt, rblock_size; 504 505 r0 = nvkm_rd32(device, 0x100200); 506 r4 = nvkm_rd32(device, 0x100204); 507 rt = nvkm_rd32(device, 0x100250); 508 nvkm_debug(subdev, "memcfg %08x %08x %08x %08x\n", 509 r0, r4, rt, nvkm_rd32(device, 0x001540)); 510 511 colbits = (r4 & 0x0000f000) >> 12; 512 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; 513 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; 514 banks = 1 << (((r4 & 0x03000000) >> 24) + 2); 515 516 rowsize = ram->parts * banks * (1 << colbits) * 8; 517 predicted = rowsize << rowbitsa; 518 if (r0 & 0x00000004) 519 predicted += rowsize << rowbitsb; 520 521 if (predicted != ram->size) { 522 nvkm_warn(subdev, "memory controller reports %d MiB VRAM\n", 523 (u32)(ram->size >> 20)); 524 } 525 526 rblock_size = rowsize; 527 if (rt & 1) 528 rblock_size *= 3; 529 530 nvkm_debug(subdev, "rblock %d bytes\n", rblock_size); 531 return rblock_size; 532 } 533 534 int 535 nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, 536 struct nvkm_oclass *oclass, int length, void **pobject) 537 { 538 const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ 539 const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ 540 struct nvkm_fb *fb = nvkm_fb(parent); 541 struct nvkm_device *device = fb->subdev.device; 542 struct nvkm_bios *bios = device->bios; 543 struct nvkm_ram *ram; 544 int ret; 545 546 ret = nvkm_ram_create_(parent, engine, oclass, length, pobject); 547 ram = *pobject; 548 if (ret) 549 return ret; 550 551 ram->size = nvkm_rd32(device, 0x10020c); 552 ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); 553 554 ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; 555 ram->parts = hweight8(ram->part_mask); 556 557 switch (nvkm_rd32(device, 0x100714) & 0x00000007) { 558 case 0: ram->type = NV_MEM_TYPE_DDR1; break; 559 case 1: 560 if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) 561 ram->type = NV_MEM_TYPE_DDR3; 562 else 563 ram->type = NV_MEM_TYPE_DDR2; 564 break; 565 case 2: ram->type = NV_MEM_TYPE_GDDR3; break; 566 case 3: ram->type = NV_MEM_TYPE_GDDR4; break; 567 case 4: ram->type = NV_MEM_TYPE_GDDR5; break; 568 default: 569 break; 570 } 571 572 ret = nvkm_mm_init(&fb->vram, rsvd_head, (ram->size >> 12) - 573 (rsvd_head + rsvd_tail), 574 nv50_fb_vram_rblock(fb, ram) >> 12); 575 if (ret) 576 return ret; 577 578 ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1; 579 ram->tags = nvkm_rd32(device, 0x100320); 580 ram->get = nv50_ram_get; 581 ram->put = nv50_ram_put; 582 return 0; 583 } 584 585 static int 586 nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 587 struct nvkm_oclass *oclass, void *data, u32 datasize, 588 struct nvkm_object **pobject) 589 { 590 struct nvkm_fb *fb = nvkm_fb(parent); 591 struct nvkm_subdev *subdev = &fb->subdev; 592 struct nv50_ram *ram; 593 int ret, i; 594 595 ret = nv50_ram_create(parent, engine, oclass, &ram); 596 *pobject = nv_object(ram); 597 if (ret) 598 return ret; 599 600 switch (ram->base.type) { 601 case NV_MEM_TYPE_GDDR3: 602 ram->base.calc = nv50_ram_calc; 603 ram->base.prog = nv50_ram_prog; 604 ram->base.tidy = nv50_ram_tidy; 605 break; 606 case NV_MEM_TYPE_DDR2: 607 default: 608 nvkm_warn(subdev, "reclocking of this ram type unsupported\n"); 609 return 0; 610 } 611 612 ram->hwsq.r_0x002504 = hwsq_reg(0x002504); 613 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); 614 ram->hwsq.r_0x004008 = hwsq_reg(0x004008); 615 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); 616 ram->hwsq.r_0x100200 = hwsq_reg(0x100200); 617 ram->hwsq.r_0x100210 = hwsq_reg(0x100210); 618 ram->hwsq.r_0x10021c = hwsq_reg(0x10021c); 619 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); 620 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); 621 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); 622 ram->hwsq.r_0x10053c = hwsq_reg(0x10053c); 623 ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0); 624 ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4); 625 ram->hwsq.r_0x100710 = hwsq_reg(0x100710); 626 ram->hwsq.r_0x100714 = hwsq_reg(0x100714); 627 ram->hwsq.r_0x100718 = hwsq_reg(0x100718); 628 ram->hwsq.r_0x10071c = hwsq_reg(0x10071c); 629 ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask); 630 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); 631 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); 632 ram->hwsq.r_0x611200 = hwsq_reg(0x611200); 633 634 for (i = 0; i < 9; i++) 635 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); 636 637 if (ram->base.ranks > 1) { 638 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8); 639 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc); 640 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8); 641 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec); 642 } else { 643 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); 644 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); 645 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); 646 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); 647 } 648 649 return 0; 650 } 651 652 struct nvkm_oclass 653 nv50_ram_oclass = { 654 .ofuncs = &(struct nvkm_ofuncs) { 655 .ctor = nv50_ram_ctor, 656 .dtor = _nvkm_ram_dtor, 657 .init = _nvkm_ram_init, 658 .fini = _nvkm_ram_fini, 659 } 660 }; 661