1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv40.h" 25 26 #include <subdev/bios.h> 27 #include <subdev/bios/bit.h> 28 #include <subdev/bios/init.h> 29 #include <subdev/bios/pll.h> 30 #include <subdev/clk/pll.h> 31 #include <subdev/timer.h> 32 33 int 34 nv40_ram_calc(struct nvkm_fb *fb, u32 freq) 35 { 36 struct nvkm_bios *bios = nvkm_bios(fb); 37 struct nv40_ram *ram = (void *)fb->ram; 38 struct nvbios_pll pll; 39 int N1, M1, N2, M2; 40 int log2P, ret; 41 42 ret = nvbios_pll_parse(bios, 0x04, &pll); 43 if (ret) { 44 nv_error(fb, "mclk pll data not found\n"); 45 return ret; 46 } 47 48 ret = nv04_pll_calc(nv_subdev(fb), &pll, freq, 49 &N1, &M1, &N2, &M2, &log2P); 50 if (ret < 0) 51 return ret; 52 53 ram->ctrl = 0x80000000 | (log2P << 16); 54 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; 55 if (N2 == M2) { 56 ram->ctrl |= 0x00000100; 57 ram->coef = (N1 << 8) | M1; 58 } else { 59 ram->ctrl |= 0x40000000; 60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; 61 } 62 63 return 0; 64 } 65 66 int 67 nv40_ram_prog(struct nvkm_fb *fb) 68 { 69 struct nvkm_device *device = fb->subdev.device; 70 struct nvkm_bios *bios = device->bios; 71 struct nv40_ram *ram = (void *)fb->ram; 72 struct bit_entry M; 73 u32 crtc_mask = 0; 74 u8 sr1[2]; 75 int i; 76 77 /* determine which CRTCs are active, fetch VGA_SR1 for each */ 78 for (i = 0; i < 2; i++) { 79 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); 80 u32 cnt = 0; 81 do { 82 if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) { 83 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); 84 sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000)); 85 if (!(sr1[i] & 0x20)) 86 crtc_mask |= (1 << i); 87 break; 88 } 89 udelay(1); 90 } while (cnt++ < 32); 91 } 92 93 /* wait for vblank start on active crtcs, disable memory access */ 94 for (i = 0; i < 2; i++) { 95 if (!(crtc_mask & (1 << i))) 96 continue; 97 nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000); 98 nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); 99 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); 100 nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); 101 } 102 103 /* prepare ram for reclocking */ 104 nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */ 105 nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */ 106 nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */ 107 nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ 108 nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */ 109 110 /* change the PLL of each memory partition */ 111 nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000); 112 switch (device->chipset) { 113 case 0x40: 114 case 0x45: 115 case 0x41: 116 case 0x42: 117 case 0x47: 118 nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl); 119 nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); 120 nvkm_wr32(device, 0x004048, ram->coef); 121 nvkm_wr32(device, 0x004030, ram->coef); 122 case 0x43: 123 case 0x49: 124 case 0x4b: 125 nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); 126 nvkm_wr32(device, 0x00403c, ram->coef); 127 default: 128 nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); 129 nvkm_wr32(device, 0x004024, ram->coef); 130 break; 131 } 132 udelay(100); 133 nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000); 134 135 /* re-enable normal operation of memory controller */ 136 nvkm_wr32(device, 0x1002dc, 0x00000000); 137 nvkm_mask(device, 0x100210, 0x80000000, 0x80000000); 138 udelay(100); 139 140 /* execute memory reset script from vbios */ 141 if (!bit_entry(bios, 'M', &M)) { 142 struct nvbios_init init = { 143 .subdev = nv_subdev(fb), 144 .bios = bios, 145 .offset = nv_ro16(bios, M.offset + 0x00), 146 .execute = 1, 147 }; 148 149 nvbios_exec(&init); 150 } 151 152 /* make sure we're in vblank (hopefully the same one as before), and 153 * then re-enable crtc memory access 154 */ 155 for (i = 0; i < 2; i++) { 156 if (!(crtc_mask & (1 << i))) 157 continue; 158 nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); 159 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); 160 nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]); 161 } 162 163 return 0; 164 } 165 166 void 167 nv40_ram_tidy(struct nvkm_fb *fb) 168 { 169 } 170 171 static int 172 nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, 173 struct nvkm_oclass *oclass, void *data, u32 size, 174 struct nvkm_object **pobject) 175 { 176 struct nvkm_fb *fb = nvkm_fb(parent); 177 struct nv40_ram *ram; 178 struct nvkm_device *device = fb->subdev.device; 179 u32 pbus1218 = nvkm_rd32(device, 0x001218); 180 int ret; 181 182 ret = nvkm_ram_create(parent, engine, oclass, &ram); 183 *pobject = nv_object(ram); 184 if (ret) 185 return ret; 186 187 switch (pbus1218 & 0x00000300) { 188 case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break; 189 case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break; 190 case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break; 191 case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break; 192 } 193 194 ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000; 195 ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; 196 ram->base.tags = nvkm_rd32(device, 0x100320); 197 ram->base.calc = nv40_ram_calc; 198 ram->base.prog = nv40_ram_prog; 199 ram->base.tidy = nv40_ram_tidy; 200 return 0; 201 } 202 203 204 struct nvkm_oclass 205 nv40_ram_oclass = { 206 .handle = 0, 207 .ofuncs = &(struct nvkm_ofuncs) { 208 .ctor = nv40_ram_create, 209 .dtor = _nvkm_ram_dtor, 210 .init = _nvkm_ram_init, 211 .fini = _nvkm_ram_fini, 212 } 213 }; 214