1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv40.h" 25 26 #include <subdev/bios.h> 27 #include <subdev/bios/bit.h> 28 #include <subdev/bios/init.h> 29 #include <subdev/bios/pll.h> 30 #include <subdev/clk/pll.h> 31 #include <subdev/timer.h> 32 33 int 34 nv40_ram_calc(struct nvkm_fb *fb, u32 freq) 35 { 36 struct nvkm_subdev *subdev = &fb->subdev; 37 struct nvkm_bios *bios = subdev->device->bios; 38 struct nv40_ram *ram = (void *)fb->ram; 39 struct nvbios_pll pll; 40 int N1, M1, N2, M2; 41 int log2P, ret; 42 43 ret = nvbios_pll_parse(bios, 0x04, &pll); 44 if (ret) { 45 nvkm_error(subdev, "mclk pll data not found\n"); 46 return ret; 47 } 48 49 ret = nv04_pll_calc(nv_subdev(fb), &pll, freq, 50 &N1, &M1, &N2, &M2, &log2P); 51 if (ret < 0) 52 return ret; 53 54 ram->ctrl = 0x80000000 | (log2P << 16); 55 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; 56 if (N2 == M2) { 57 ram->ctrl |= 0x00000100; 58 ram->coef = (N1 << 8) | M1; 59 } else { 60 ram->ctrl |= 0x40000000; 61 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; 62 } 63 64 return 0; 65 } 66 67 int 68 nv40_ram_prog(struct nvkm_fb *fb) 69 { 70 struct nvkm_device *device = fb->subdev.device; 71 struct nvkm_bios *bios = device->bios; 72 struct nv40_ram *ram = (void *)fb->ram; 73 struct bit_entry M; 74 u32 crtc_mask = 0; 75 u8 sr1[2]; 76 int i; 77 78 /* determine which CRTCs are active, fetch VGA_SR1 for each */ 79 for (i = 0; i < 2; i++) { 80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); 81 u32 cnt = 0; 82 do { 83 if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) { 84 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); 85 sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000)); 86 if (!(sr1[i] & 0x20)) 87 crtc_mask |= (1 << i); 88 break; 89 } 90 udelay(1); 91 } while (cnt++ < 32); 92 } 93 94 /* wait for vblank start on active crtcs, disable memory access */ 95 for (i = 0; i < 2; i++) { 96 if (!(crtc_mask & (1 << i))) 97 continue; 98 99 nvkm_msec(device, 2000, 100 u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); 101 if (!(tmp & 0x00010000)) 102 break; 103 ); 104 105 nvkm_msec(device, 2000, 106 u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); 107 if ( (tmp & 0x00010000)) 108 break; 109 ); 110 111 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); 112 nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); 113 } 114 115 /* prepare ram for reclocking */ 116 nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */ 117 nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */ 118 nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */ 119 nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ 120 nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */ 121 122 /* change the PLL of each memory partition */ 123 nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000); 124 switch (device->chipset) { 125 case 0x40: 126 case 0x45: 127 case 0x41: 128 case 0x42: 129 case 0x47: 130 nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl); 131 nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); 132 nvkm_wr32(device, 0x004048, ram->coef); 133 nvkm_wr32(device, 0x004030, ram->coef); 134 case 0x43: 135 case 0x49: 136 case 0x4b: 137 nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); 138 nvkm_wr32(device, 0x00403c, ram->coef); 139 default: 140 nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); 141 nvkm_wr32(device, 0x004024, ram->coef); 142 break; 143 } 144 udelay(100); 145 nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000); 146 147 /* re-enable normal operation of memory controller */ 148 nvkm_wr32(device, 0x1002dc, 0x00000000); 149 nvkm_mask(device, 0x100210, 0x80000000, 0x80000000); 150 udelay(100); 151 152 /* execute memory reset script from vbios */ 153 if (!bit_entry(bios, 'M', &M)) { 154 struct nvbios_init init = { 155 .subdev = nv_subdev(fb), 156 .bios = bios, 157 .offset = nv_ro16(bios, M.offset + 0x00), 158 .execute = 1, 159 }; 160 161 nvbios_exec(&init); 162 } 163 164 /* make sure we're in vblank (hopefully the same one as before), and 165 * then re-enable crtc memory access 166 */ 167 for (i = 0; i < 2; i++) { 168 if (!(crtc_mask & (1 << i))) 169 continue; 170 171 nvkm_msec(device, 2000, 172 u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); 173 if ( (tmp & 0x00010000)) 174 break; 175 ); 176 177 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); 178 nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]); 179 } 180 181 return 0; 182 } 183 184 void 185 nv40_ram_tidy(struct nvkm_fb *fb) 186 { 187 } 188 189 static int 190 nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, 191 struct nvkm_oclass *oclass, void *data, u32 size, 192 struct nvkm_object **pobject) 193 { 194 struct nvkm_fb *fb = nvkm_fb(parent); 195 struct nv40_ram *ram; 196 struct nvkm_device *device = fb->subdev.device; 197 u32 pbus1218 = nvkm_rd32(device, 0x001218); 198 int ret; 199 200 ret = nvkm_ram_create(parent, engine, oclass, &ram); 201 *pobject = nv_object(ram); 202 if (ret) 203 return ret; 204 205 switch (pbus1218 & 0x00000300) { 206 case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break; 207 case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break; 208 case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break; 209 case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break; 210 } 211 212 ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000; 213 ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; 214 ram->base.tags = nvkm_rd32(device, 0x100320); 215 ram->base.calc = nv40_ram_calc; 216 ram->base.prog = nv40_ram_prog; 217 ram->base.tidy = nv40_ram_tidy; 218 return 0; 219 } 220 221 222 struct nvkm_oclass 223 nv40_ram_oclass = { 224 .handle = 0, 225 .ofuncs = &(struct nvkm_ofuncs) { 226 .ctor = nv40_ram_create, 227 .dtor = _nvkm_ram_dtor, 228 .init = _nvkm_ram_init, 229 .fini = _nvkm_ram_fini, 230 } 231 }; 232