1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * Roy Spliet <rspliet@eclipso.eu> 24 */ 25 26 #include "ramfuc.h" 27 #include "nv50.h" 28 29 #include <core/option.h> 30 #include <subdev/bios.h> 31 #include <subdev/bios/M0205.h> 32 #include <subdev/bios/rammap.h> 33 #include <subdev/bios/timing.h> 34 #include <subdev/clk/gt215.h> 35 #include <subdev/gpio.h> 36 37 /* XXX: Remove when memx gains GPIO support */ 38 extern int nv50_gpio_location(int line, u32 *reg, u32 *shift); 39 40 struct gt215_ramfuc { 41 struct ramfuc base; 42 struct ramfuc_reg r_0x001610; 43 struct ramfuc_reg r_0x001700; 44 struct ramfuc_reg r_0x002504; 45 struct ramfuc_reg r_0x004000; 46 struct ramfuc_reg r_0x004004; 47 struct ramfuc_reg r_0x004018; 48 struct ramfuc_reg r_0x004128; 49 struct ramfuc_reg r_0x004168; 50 struct ramfuc_reg r_0x100080; 51 struct ramfuc_reg r_0x100200; 52 struct ramfuc_reg r_0x100210; 53 struct ramfuc_reg r_0x100220[9]; 54 struct ramfuc_reg r_0x100264; 55 struct ramfuc_reg r_0x1002d0; 56 struct ramfuc_reg r_0x1002d4; 57 struct ramfuc_reg r_0x1002dc; 58 struct ramfuc_reg r_0x10053c; 59 struct ramfuc_reg r_0x1005a0; 60 struct ramfuc_reg r_0x1005a4; 61 struct ramfuc_reg r_0x100700; 62 struct ramfuc_reg r_0x100714; 63 struct ramfuc_reg r_0x100718; 64 struct ramfuc_reg r_0x10071c; 65 struct ramfuc_reg r_0x100720; 66 struct ramfuc_reg r_0x100760; 67 struct ramfuc_reg r_0x1007a0; 68 struct ramfuc_reg r_0x1007e0; 69 struct ramfuc_reg r_0x100da0; 70 struct ramfuc_reg r_0x10f804; 71 struct ramfuc_reg r_0x1110e0; 72 struct ramfuc_reg r_0x111100; 73 struct ramfuc_reg r_0x111104; 74 struct ramfuc_reg r_0x1111e0; 75 struct ramfuc_reg r_0x111400; 76 struct ramfuc_reg r_0x611200; 77 struct ramfuc_reg r_mr[4]; 78 struct ramfuc_reg r_gpioFBVREF; 79 }; 80 81 struct gt215_ltrain { 82 enum { 83 NVA3_TRAIN_UNKNOWN, 84 NVA3_TRAIN_UNSUPPORTED, 85 NVA3_TRAIN_ONCE, 86 NVA3_TRAIN_EXEC, 87 NVA3_TRAIN_DONE 88 } state; 89 u32 r_100720; 90 u32 r_1111e0; 91 u32 r_111400; 92 struct nvkm_mem *mem; 93 }; 94 95 struct gt215_ram { 96 struct nvkm_ram base; 97 struct gt215_ramfuc fuc; 98 struct gt215_ltrain ltrain; 99 }; 100 101 void 102 gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) 103 { 104 int i, lo, hi; 105 u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; 106 107 for (i = 0; i < 8; i++) { 108 for (lo = 0; lo < 0x40; lo++) { 109 if (!(vals[lo] & 0x80000000)) 110 continue; 111 if (vals[lo] & (0x101 << i)) 112 break; 113 } 114 115 if (lo == 0x40) 116 return; 117 118 for (hi = lo + 1; hi < 0x40; hi++) { 119 if (!(vals[lo] & 0x80000000)) 120 continue; 121 if (!(vals[hi] & (0x101 << i))) { 122 hi--; 123 break; 124 } 125 } 126 127 median[i] = ((hi - lo) >> 1) + lo; 128 bins[(median[i] & 0xf0) >> 4]++; 129 median[i] += 0x30; 130 } 131 132 /* Find the best value for 0x1111e0 */ 133 for (i = 0; i < 4; i++) { 134 if (bins[i] > qty) { 135 bin = i + 3; 136 qty = bins[i]; 137 } 138 } 139 140 train->r_100720 = 0; 141 for (i = 0; i < 8; i++) { 142 median[i] = max(median[i], (u8) (bin << 4)); 143 median[i] = min(median[i], (u8) ((bin << 4) | 0xf)); 144 145 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); 146 } 147 148 train->r_1111e0 = 0x02000000 | (bin * 0x101); 149 train->r_111400 = 0x0; 150 } 151 152 /* 153 * Link training for (at least) DDR3 154 */ 155 int 156 gt215_link_train(struct nvkm_fb *fb) 157 { 158 struct gt215_ram *ram = (void *)fb->ram; 159 struct gt215_ltrain *train = &ram->ltrain; 160 struct gt215_ramfuc *fuc = &ram->fuc; 161 struct nvkm_subdev *subdev = &fb->subdev; 162 struct nvkm_device *device = subdev->device; 163 struct nvkm_bios *bios = device->bios; 164 struct nvkm_clk *clk = device->clk; 165 u32 *result, r1700; 166 int ret, i; 167 struct nvbios_M0205T M0205T = { 0 }; 168 u8 ver, hdr, cnt, len, snr, ssz; 169 unsigned int clk_current; 170 unsigned long flags; 171 unsigned long *f = &flags; 172 173 if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true) 174 return -ENOSYS; 175 176 /* XXX: Multiple partitions? */ 177 result = kmalloc(64 * sizeof(u32), GFP_KERNEL); 178 if (!result) 179 return -ENOMEM; 180 181 train->state = NVA3_TRAIN_EXEC; 182 183 /* Clock speeds for training and back */ 184 nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T); 185 if (M0205T.freq == 0) { 186 kfree(result); 187 return -ENOENT; 188 } 189 190 clk_current = clk->read(clk, nv_clk_src_mem); 191 192 ret = gt215_clk_pre(clk, f); 193 if (ret) 194 goto out; 195 196 /* First: clock up/down */ 197 ret = ram->base.calc(fb, (u32) M0205T.freq * 1000); 198 if (ret) 199 goto out; 200 201 /* Do this *after* calc, eliminates write in script */ 202 nvkm_wr32(device, 0x111400, 0x00000000); 203 /* XXX: Magic writes that improve train reliability? */ 204 nvkm_mask(device, 0x100674, 0x0000ffff, 0x00000000); 205 nvkm_mask(device, 0x1005e4, 0x0000ffff, 0x00000000); 206 nvkm_mask(device, 0x100b0c, 0x000000ff, 0x00000000); 207 nvkm_wr32(device, 0x100c04, 0x00000400); 208 209 /* Now the training script */ 210 r1700 = ram_rd32(fuc, 0x001700); 211 212 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000); 213 ram_wr32(fuc, 0x611200, 0x3300); 214 ram_wait_vblank(fuc); 215 ram_wait(fuc, 0x611200, 0x00000003, 0x00000000, 500000); 216 ram_mask(fuc, 0x001610, 0x00000083, 0x00000003); 217 ram_mask(fuc, 0x100080, 0x00000020, 0x00000000); 218 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000); 219 ram_wr32(fuc, 0x001700, 0x00000000); 220 221 ram_train(fuc); 222 223 /* Reset */ 224 ram_mask(fuc, 0x10f804, 0x80000000, 0x80000000); 225 ram_wr32(fuc, 0x10053c, 0x0); 226 ram_wr32(fuc, 0x100720, train->r_100720); 227 ram_wr32(fuc, 0x1111e0, train->r_1111e0); 228 ram_wr32(fuc, 0x111400, train->r_111400); 229 ram_nuke(fuc, 0x100080); 230 ram_mask(fuc, 0x100080, 0x00000020, 0x00000020); 231 ram_nsec(fuc, 1000); 232 233 ram_wr32(fuc, 0x001700, r1700); 234 ram_mask(fuc, 0x001610, 0x00000083, 0x00000080); 235 ram_wr32(fuc, 0x611200, 0x3330); 236 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800); 237 238 ram_exec(fuc, true); 239 240 ram->base.calc(fb, clk_current); 241 ram_exec(fuc, true); 242 243 /* Post-processing, avoids flicker */ 244 nvkm_mask(device, 0x616308, 0x10, 0x10); 245 nvkm_mask(device, 0x616b08, 0x10, 0x10); 246 247 gt215_clk_post(clk, f); 248 249 ram_train_result(fb, result, 64); 250 for (i = 0; i < 64; i++) 251 nvkm_debug(subdev, "Train: %08x", result[i]); 252 gt215_link_train_calc(result, train); 253 254 nvkm_debug(subdev, "Train: %08x %08x %08x", train->r_100720, 255 train->r_1111e0, train->r_111400); 256 257 kfree(result); 258 259 train->state = NVA3_TRAIN_DONE; 260 261 return ret; 262 263 out: 264 if(ret == -EBUSY) 265 f = NULL; 266 267 train->state = NVA3_TRAIN_UNSUPPORTED; 268 269 gt215_clk_post(clk, f); 270 kfree(result); 271 return ret; 272 } 273 274 int 275 gt215_link_train_init(struct nvkm_fb *fb) 276 { 277 static const u32 pattern[16] = { 278 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, 279 0x00000000, 0x11111111, 0x44444444, 0xdddddddd, 280 0x33333333, 0x55555555, 0x77777777, 0x66666666, 281 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, 282 }; 283 struct nvkm_device *device = fb->subdev.device; 284 struct nvkm_bios *bios = device->bios; 285 struct gt215_ram *ram = (void *)fb->ram; 286 struct gt215_ltrain *train = &ram->ltrain; 287 struct nvkm_mem *mem; 288 struct nvbios_M0205E M0205E; 289 u8 ver, hdr, cnt, len; 290 u32 r001700; 291 int ret, i = 0; 292 293 train->state = NVA3_TRAIN_UNSUPPORTED; 294 295 /* We support type "5" 296 * XXX: training pattern table appears to be unused for this routine */ 297 if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)) 298 return -ENOENT; 299 300 if (M0205E.type != 5) 301 return 0; 302 303 train->state = NVA3_TRAIN_ONCE; 304 305 ret = fb->ram->get(fb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem); 306 if (ret) 307 return ret; 308 309 mem = ram->ltrain.mem; 310 311 nvkm_wr32(device, 0x100538, 0x10000000 | (mem->offset >> 16)); 312 nvkm_wr32(device, 0x1005a8, 0x0000ffff); 313 nvkm_mask(device, 0x10f800, 0x00000001, 0x00000001); 314 315 for (i = 0; i < 0x30; i++) { 316 nvkm_wr32(device, 0x10f8c0, (i << 8) | i); 317 nvkm_wr32(device, 0x10f900, pattern[i % 16]); 318 } 319 320 for (i = 0; i < 0x30; i++) { 321 nvkm_wr32(device, 0x10f8e0, (i << 8) | i); 322 nvkm_wr32(device, 0x10f920, pattern[i % 16]); 323 } 324 325 /* And upload the pattern */ 326 r001700 = nvkm_rd32(device, 0x1700); 327 nvkm_wr32(device, 0x1700, mem->offset >> 16); 328 for (i = 0; i < 16; i++) 329 nvkm_wr32(device, 0x700000 + (i << 2), pattern[i]); 330 for (i = 0; i < 16; i++) 331 nvkm_wr32(device, 0x700100 + (i << 2), pattern[i]); 332 nvkm_wr32(device, 0x1700, r001700); 333 334 train->r_100720 = nvkm_rd32(device, 0x100720); 335 train->r_1111e0 = nvkm_rd32(device, 0x1111e0); 336 train->r_111400 = nvkm_rd32(device, 0x111400); 337 return 0; 338 } 339 340 void 341 gt215_link_train_fini(struct nvkm_fb *fb) 342 { 343 struct gt215_ram *ram = (void *)fb->ram; 344 345 if (ram->ltrain.mem) 346 fb->ram->put(fb, &ram->ltrain.mem); 347 } 348 349 /* 350 * RAM reclocking 351 */ 352 #define T(t) cfg->timing_10_##t 353 static int 354 gt215_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) 355 { 356 struct gt215_ram *ram = (void *)fb->ram; 357 struct nvbios_ramcfg *cfg = &ram->base.target.bios; 358 struct nvkm_subdev *subdev = &fb->subdev; 359 struct nvkm_device *device = subdev->device; 360 int tUNK_base, tUNK_40_0, prevCL; 361 u32 cur2, cur3, cur7, cur8; 362 363 cur2 = nvkm_rd32(device, 0x100228); 364 cur3 = nvkm_rd32(device, 0x10022c); 365 cur7 = nvkm_rd32(device, 0x10023c); 366 cur8 = nvkm_rd32(device, 0x100240); 367 368 369 switch ((!T(CWL)) * ram->base.type) { 370 case NV_MEM_TYPE_DDR2: 371 T(CWL) = T(CL) - 1; 372 break; 373 case NV_MEM_TYPE_GDDR3: 374 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; 375 break; 376 } 377 378 prevCL = (cur3 & 0x000000ff) + 1; 379 tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL; 380 381 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 382 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 383 max_t(u8,T(18), 1) << 16 | 384 (T(WTR) + 1 + T(CWL)) << 8 | 385 (5 + T(CL) - T(CWL)); 386 timing[2] = (T(CWL) - 1) << 24 | 387 (T(RRD) << 16) | 388 (T(RCDWR) << 8) | 389 T(RCDRD); 390 timing[3] = (cur3 & 0x00ff0000) | 391 (0x30 + T(CL)) << 24 | 392 (0xb + T(CL)) << 8 | 393 (T(CL) - 1); 394 timing[4] = T(20) << 24 | 395 T(21) << 16 | 396 T(13) << 8 | 397 T(13); 398 timing[5] = T(RFC) << 24 | 399 max_t(u8,T(RCDRD), T(RCDWR)) << 16 | 400 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | 401 T(RP); 402 timing[6] = (0x5a + T(CL)) << 16 | 403 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | 404 (0x50 + T(CL) - T(CWL)); 405 timing[7] = (cur7 & 0xff000000) | 406 ((tUNK_base + T(CL)) << 16) | 407 0x202; 408 timing[8] = cur8 & 0xffffff00; 409 410 switch (ram->base.type) { 411 case NV_MEM_TYPE_DDR2: 412 case NV_MEM_TYPE_GDDR3: 413 tUNK_40_0 = prevCL - (cur8 & 0xff); 414 if (tUNK_40_0 > 0) 415 timing[8] |= T(CL); 416 break; 417 default: 418 break; 419 } 420 421 nvkm_debug(subdev, "Entry: 220: %08x %08x %08x %08x\n", 422 timing[0], timing[1], timing[2], timing[3]); 423 nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n", 424 timing[4], timing[5], timing[6], timing[7]); 425 nvkm_debug(subdev, " 240: %08x\n", timing[8]); 426 return 0; 427 } 428 #undef T 429 430 static void 431 nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc) 432 { 433 ram_mask(fuc, mr[0], 0x100, 0x100); 434 ram_nsec(fuc, 1000); 435 ram_mask(fuc, mr[0], 0x100, 0x000); 436 ram_nsec(fuc, 1000); 437 } 438 439 static void 440 nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr) 441 { 442 u32 mr1_old = ram_rd32(fuc, mr[1]); 443 444 if (!(mr1_old & 0x1)) { 445 ram_wr32(fuc, 0x1002d4, 0x00000001); 446 ram_wr32(fuc, mr[1], mr[1]); 447 ram_nsec(fuc, 1000); 448 } 449 } 450 451 static void 452 nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr) 453 { 454 u32 mr1_old = ram_rd32(fuc, mr[1]); 455 456 if (!(mr1_old & 0x40)) { 457 ram_wr32(fuc, mr[1], mr[1]); 458 ram_nsec(fuc, 1000); 459 } 460 } 461 462 static void 463 gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk) 464 { 465 ram_wr32(fuc, 0x004004, mclk->pll); 466 ram_mask(fuc, 0x004000, 0x00000001, 0x00000001); 467 ram_mask(fuc, 0x004000, 0x00000010, 0x00000000); 468 ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000); 469 ram_mask(fuc, 0x004000, 0x00000010, 0x00000010); 470 } 471 472 static void 473 gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) 474 { 475 struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.fb); 476 struct dcb_gpio_func func; 477 u32 reg, sh, gpio_val; 478 int ret; 479 480 if (gpio->get(gpio, 0, 0x2e, DCB_GPIO_UNUSED) != val) { 481 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); 482 if (ret) 483 return; 484 485 nv50_gpio_location(func.line, ®, &sh); 486 gpio_val = ram_rd32(fuc, gpioFBVREF); 487 if (gpio_val & (8 << sh)) 488 val = !val; 489 490 ram_mask(fuc, gpioFBVREF, (0x3 << sh), ((val | 0x2) << sh)); 491 ram_nsec(fuc, 20000); 492 } 493 } 494 495 static int 496 gt215_ram_calc(struct nvkm_fb *fb, u32 freq) 497 { 498 struct gt215_ram *ram = (void *)fb->ram; 499 struct gt215_ramfuc *fuc = &ram->fuc; 500 struct gt215_ltrain *train = &ram->ltrain; 501 struct nvkm_subdev *subdev = &fb->subdev; 502 struct nvkm_device *device = subdev->device; 503 struct nvkm_bios *bios = device->bios; 504 struct gt215_clk_info mclk; 505 struct nvkm_ram_data *next; 506 u8 ver, hdr, cnt, len, strap; 507 u32 data; 508 u32 r004018, r100760, r100da0, r111100, ctrl; 509 u32 unk714, unk718, unk71c; 510 int ret, i; 511 u32 timing[9]; 512 bool pll2pll; 513 514 next = &ram->base.target; 515 next->freq = freq; 516 ram->base.next = next; 517 518 if (ram->ltrain.state == NVA3_TRAIN_ONCE) 519 gt215_link_train(fb); 520 521 /* lookup memory config data relevant to the target frequency */ 522 data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len, 523 &next->bios); 524 if (!data || ver != 0x10 || hdr < 0x05) { 525 nvkm_error(subdev, "invalid/missing rammap entry\n"); 526 return -EINVAL; 527 } 528 529 /* locate specific data set for the attached memory */ 530 strap = nvbios_ramcfg_index(nv_subdev(fb)); 531 if (strap >= cnt) { 532 nvkm_error(subdev, "invalid ramcfg strap\n"); 533 return -EINVAL; 534 } 535 536 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap, 537 &ver, &hdr, &next->bios); 538 if (!data || ver != 0x10 || hdr < 0x09) { 539 nvkm_error(subdev, "invalid/missing ramcfg entry\n"); 540 return -EINVAL; 541 } 542 543 /* lookup memory timings, if bios says they're present */ 544 if (next->bios.ramcfg_timing != 0xff) { 545 data = nvbios_timingEp(bios, next->bios.ramcfg_timing, 546 &ver, &hdr, &cnt, &len, 547 &next->bios); 548 if (!data || ver != 0x10 || hdr < 0x17) { 549 nvkm_error(subdev, "invalid/missing timing entry\n"); 550 return -EINVAL; 551 } 552 } 553 554 ret = gt215_pll_info(nvkm_clk(fb), 0x12, 0x4000, freq, &mclk); 555 if (ret < 0) { 556 nvkm_error(subdev, "failed mclk calculation\n"); 557 return ret; 558 } 559 560 gt215_ram_timing_calc(fb, timing); 561 562 ret = ram_init(fuc, fb); 563 if (ret) 564 return ret; 565 566 /* Determine ram-specific MR values */ 567 ram->base.mr[0] = ram_rd32(fuc, mr[0]); 568 ram->base.mr[1] = ram_rd32(fuc, mr[1]); 569 ram->base.mr[2] = ram_rd32(fuc, mr[2]); 570 571 switch (ram->base.type) { 572 case NV_MEM_TYPE_DDR2: 573 ret = nvkm_sddr2_calc(&ram->base); 574 break; 575 case NV_MEM_TYPE_DDR3: 576 ret = nvkm_sddr3_calc(&ram->base); 577 break; 578 case NV_MEM_TYPE_GDDR3: 579 ret = nvkm_gddr3_calc(&ram->base); 580 break; 581 default: 582 ret = -ENOSYS; 583 break; 584 } 585 586 if (ret) 587 return ret; 588 589 /* XXX: 750MHz seems rather arbitrary */ 590 if (freq <= 750000) { 591 r004018 = 0x10000000; 592 r100760 = 0x22222222; 593 r100da0 = 0x00000010; 594 } else { 595 r004018 = 0x00000000; 596 r100760 = 0x00000000; 597 r100da0 = 0x00000000; 598 } 599 600 if (!next->bios.ramcfg_DLLoff) 601 r004018 |= 0x00004000; 602 603 /* pll2pll requires to switch to a safe clock first */ 604 ctrl = ram_rd32(fuc, 0x004000); 605 pll2pll = (!(ctrl & 0x00000008)) && mclk.pll; 606 607 /* Pre, NVIDIA does this outside the script */ 608 if (next->bios.ramcfg_10_02_10) { 609 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000); 610 } else { 611 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000); 612 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000); 613 } 614 /* Always disable this bit during reclock */ 615 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000); 616 617 /* If switching from non-pll to pll, lock before disabling FB */ 618 if (mclk.pll && !pll2pll) { 619 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101); 620 gt215_ram_lock_pll(fuc, &mclk); 621 } 622 623 /* Start with disabling some CRTCs and PFIFO? */ 624 ram_wait_vblank(fuc); 625 ram_wr32(fuc, 0x611200, 0x3300); 626 ram_mask(fuc, 0x002504, 0x1, 0x1); 627 ram_nsec(fuc, 10000); 628 ram_wait(fuc, 0x002504, 0x10, 0x10, 20000); /* XXX: or longer? */ 629 ram_block(fuc); 630 ram_nsec(fuc, 2000); 631 632 if (!next->bios.ramcfg_10_02_10) { 633 if (ram->base.type == NV_MEM_TYPE_GDDR3) 634 ram_mask(fuc, 0x111100, 0x04020000, 0x00020000); 635 else 636 ram_mask(fuc, 0x111100, 0x04020000, 0x04020000); 637 } 638 639 /* If we're disabling the DLL, do it now */ 640 switch (next->bios.ramcfg_DLLoff * ram->base.type) { 641 case NV_MEM_TYPE_DDR3: 642 nvkm_sddr3_dll_disable(fuc, ram->base.mr); 643 break; 644 case NV_MEM_TYPE_GDDR3: 645 nvkm_gddr3_dll_disable(fuc, ram->base.mr); 646 break; 647 } 648 649 if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT) 650 gt215_ram_fbvref(fuc, 0); 651 652 /* Brace RAM for impact */ 653 ram_wr32(fuc, 0x1002d4, 0x00000001); 654 ram_wr32(fuc, 0x1002d0, 0x00000001); 655 ram_wr32(fuc, 0x1002d0, 0x00000001); 656 ram_wr32(fuc, 0x100210, 0x00000000); 657 ram_wr32(fuc, 0x1002dc, 0x00000001); 658 ram_nsec(fuc, 2000); 659 660 if (nv_device(fb)->chipset == 0xa3 && freq <= 500000) 661 ram_mask(fuc, 0x100700, 0x00000006, 0x00000006); 662 663 /* Fiddle with clocks */ 664 /* There's 4 scenario's 665 * pll->pll: first switch to a 324MHz clock, set up new PLL, switch 666 * clk->pll: Set up new PLL, switch 667 * pll->clk: Set up clock, switch 668 * clk->clk: Overwrite ctrl and other bits, switch */ 669 670 /* Switch to regular clock - 324MHz */ 671 if (pll2pll) { 672 ram_mask(fuc, 0x004000, 0x00000004, 0x00000004); 673 ram_mask(fuc, 0x004168, 0x003f3141, 0x00083101); 674 ram_mask(fuc, 0x004000, 0x00000008, 0x00000008); 675 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); 676 ram_wr32(fuc, 0x004018, 0x00001000); 677 gt215_ram_lock_pll(fuc, &mclk); 678 } 679 680 if (mclk.pll) { 681 ram_mask(fuc, 0x004000, 0x00000105, 0x00000105); 682 ram_wr32(fuc, 0x004018, 0x00001000 | r004018); 683 ram_wr32(fuc, 0x100da0, r100da0); 684 } else { 685 ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101); 686 ram_mask(fuc, 0x004000, 0x00000108, 0x00000008); 687 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); 688 ram_wr32(fuc, 0x004018, 0x00009000 | r004018); 689 ram_wr32(fuc, 0x100da0, r100da0); 690 } 691 ram_nsec(fuc, 20000); 692 693 if (next->bios.rammap_10_04_08) { 694 ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 | 695 next->bios.ramcfg_10_05 << 8 | 696 next->bios.ramcfg_10_05); 697 ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 | 698 next->bios.ramcfg_10_07); 699 ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 | 700 next->bios.ramcfg_10_03_0f << 16 | 701 next->bios.ramcfg_10_09_0f | 702 0x80000000); 703 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000); 704 } else { 705 if (train->state == NVA3_TRAIN_DONE) { 706 ram_wr32(fuc, 0x100080, 0x1020); 707 ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400); 708 ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0); 709 ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720); 710 } 711 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000); 712 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000); 713 ram_mask(fuc, 0x100760, 0x22222222, r100760); 714 ram_mask(fuc, 0x1007a0, 0x22222222, r100760); 715 ram_mask(fuc, 0x1007e0, 0x22222222, r100760); 716 } 717 718 if (nv_device(fb)->chipset == 0xa3 && freq > 500000) { 719 ram_mask(fuc, 0x100700, 0x00000006, 0x00000000); 720 } 721 722 /* Final switch */ 723 if (mclk.pll) { 724 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000); 725 ram_mask(fuc, 0x004000, 0x00000008, 0x00000000); 726 } 727 728 ram_wr32(fuc, 0x1002dc, 0x00000000); 729 ram_wr32(fuc, 0x1002d4, 0x00000001); 730 ram_wr32(fuc, 0x100210, 0x80000000); 731 ram_nsec(fuc, 2000); 732 733 /* Set RAM MR parameters and timings */ 734 for (i = 2; i >= 0; i--) { 735 if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) { 736 ram_wr32(fuc, mr[i], ram->base.mr[i]); 737 ram_nsec(fuc, 1000); 738 } 739 } 740 741 ram_wr32(fuc, 0x100220[3], timing[3]); 742 ram_wr32(fuc, 0x100220[1], timing[1]); 743 ram_wr32(fuc, 0x100220[6], timing[6]); 744 ram_wr32(fuc, 0x100220[7], timing[7]); 745 ram_wr32(fuc, 0x100220[2], timing[2]); 746 ram_wr32(fuc, 0x100220[4], timing[4]); 747 ram_wr32(fuc, 0x100220[5], timing[5]); 748 ram_wr32(fuc, 0x100220[0], timing[0]); 749 ram_wr32(fuc, 0x100220[8], timing[8]); 750 751 /* Misc */ 752 ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12); 753 754 /* XXX: A lot of "chipset"/"ram type" specific stuff...? */ 755 unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000130; 756 unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100; 757 unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100; 758 r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000; 759 760 if (next->bios.ramcfg_10_02_04) { 761 switch (ram->base.type) { 762 case NV_MEM_TYPE_DDR3: 763 if (nv_device(fb)->chipset != 0xa8) 764 r111100 |= 0x00000004; 765 /* no break */ 766 case NV_MEM_TYPE_DDR2: 767 r111100 |= 0x08000000; 768 break; 769 default: 770 break; 771 } 772 } else { 773 switch (ram->base.type) { 774 case NV_MEM_TYPE_DDR2: 775 r111100 |= 0x1a800000; 776 unk714 |= 0x00000010; 777 break; 778 case NV_MEM_TYPE_DDR3: 779 if (nv_device(fb)->chipset == 0xa8) { 780 r111100 |= 0x08000000; 781 } else { 782 r111100 &= ~0x00000004; 783 r111100 |= 0x12800000; 784 } 785 unk714 |= 0x00000010; 786 break; 787 case NV_MEM_TYPE_GDDR3: 788 r111100 |= 0x30000000; 789 unk714 |= 0x00000020; 790 break; 791 default: 792 break; 793 } 794 } 795 796 unk714 |= (next->bios.ramcfg_10_04_01) << 8; 797 798 if (next->bios.ramcfg_10_02_20) 799 unk714 |= 0xf0000000; 800 if (next->bios.ramcfg_10_02_02) 801 unk718 |= 0x00000100; 802 if (next->bios.ramcfg_10_02_01) 803 unk71c |= 0x00000100; 804 if (next->bios.timing_10_24 != 0xff) { 805 unk718 &= ~0xf0000000; 806 unk718 |= next->bios.timing_10_24 << 28; 807 } 808 if (next->bios.ramcfg_10_02_10) 809 r111100 &= ~0x04020000; 810 811 ram_mask(fuc, 0x100714, 0xffffffff, unk714); 812 ram_mask(fuc, 0x10071c, 0xffffffff, unk71c); 813 ram_mask(fuc, 0x100718, 0xffffffff, unk718); 814 ram_mask(fuc, 0x111100, 0xffffffff, r111100); 815 816 if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT) 817 gt215_ram_fbvref(fuc, 1); 818 819 /* Reset DLL */ 820 if (!next->bios.ramcfg_DLLoff) 821 nvkm_sddr2_dll_reset(fuc); 822 823 if (ram->base.type == NV_MEM_TYPE_GDDR3) { 824 ram_nsec(fuc, 31000); 825 } else { 826 ram_nsec(fuc, 14000); 827 } 828 829 if (ram->base.type == NV_MEM_TYPE_DDR3) { 830 ram_wr32(fuc, 0x100264, 0x1); 831 ram_nsec(fuc, 2000); 832 } 833 834 ram_nuke(fuc, 0x100700); 835 ram_mask(fuc, 0x100700, 0x01000000, 0x01000000); 836 ram_mask(fuc, 0x100700, 0x01000000, 0x00000000); 837 838 /* Re-enable FB */ 839 ram_unblock(fuc); 840 ram_wr32(fuc, 0x611200, 0x3330); 841 842 /* Post fiddlings */ 843 if (next->bios.rammap_10_04_02) 844 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800); 845 if (next->bios.ramcfg_10_02_10) { 846 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180); 847 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000); 848 } else { 849 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600); 850 } 851 852 if (mclk.pll) { 853 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000); 854 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000); 855 } else { 856 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000); 857 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000); 858 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000); 859 } 860 861 return 0; 862 } 863 864 static int 865 gt215_ram_prog(struct nvkm_fb *fb) 866 { 867 struct nvkm_device *device = nv_device(fb); 868 struct gt215_ram *ram = (void *)fb->ram; 869 struct gt215_ramfuc *fuc = &ram->fuc; 870 bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true); 871 872 if (exec) { 873 nvkm_mask(device, 0x001534, 0x2, 0x2); 874 875 ram_exec(fuc, true); 876 877 /* Post-processing, avoids flicker */ 878 nvkm_mask(device, 0x002504, 0x1, 0x0); 879 nvkm_mask(device, 0x001534, 0x2, 0x0); 880 881 nvkm_mask(device, 0x616308, 0x10, 0x10); 882 nvkm_mask(device, 0x616b08, 0x10, 0x10); 883 } else { 884 ram_exec(fuc, false); 885 } 886 return 0; 887 } 888 889 static void 890 gt215_ram_tidy(struct nvkm_fb *fb) 891 { 892 struct gt215_ram *ram = (void *)fb->ram; 893 struct gt215_ramfuc *fuc = &ram->fuc; 894 ram_exec(fuc, false); 895 } 896 897 static int 898 gt215_ram_init(struct nvkm_object *object) 899 { 900 struct nvkm_fb *fb = (void *)object->parent; 901 struct gt215_ram *ram = (void *)object; 902 int ret; 903 904 ret = nvkm_ram_init(&ram->base); 905 if (ret) 906 return ret; 907 908 gt215_link_train_init(fb); 909 return 0; 910 } 911 912 static int 913 gt215_ram_fini(struct nvkm_object *object, bool suspend) 914 { 915 struct nvkm_fb *fb = (void *)object->parent; 916 917 if (!suspend) 918 gt215_link_train_fini(fb); 919 920 return 0; 921 } 922 923 static int 924 gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 925 struct nvkm_oclass *oclass, void *data, u32 datasize, 926 struct nvkm_object **pobject) 927 { 928 struct nvkm_fb *fb = nvkm_fb(parent); 929 struct nvkm_subdev *subdev = &fb->subdev; 930 struct nvkm_gpio *gpio = subdev->device->gpio; 931 struct dcb_gpio_func func; 932 struct gt215_ram *ram; 933 int ret, i; 934 u32 reg, shift; 935 936 ret = nv50_ram_create(parent, engine, oclass, &ram); 937 *pobject = nv_object(ram); 938 if (ret) 939 return ret; 940 941 switch (ram->base.type) { 942 case NV_MEM_TYPE_DDR2: 943 case NV_MEM_TYPE_DDR3: 944 case NV_MEM_TYPE_GDDR3: 945 ram->base.calc = gt215_ram_calc; 946 ram->base.prog = gt215_ram_prog; 947 ram->base.tidy = gt215_ram_tidy; 948 break; 949 default: 950 nvkm_warn(subdev, "reclocking of this ram type unsupported\n"); 951 return 0; 952 } 953 954 ram->fuc.r_0x001610 = ramfuc_reg(0x001610); 955 ram->fuc.r_0x001700 = ramfuc_reg(0x001700); 956 ram->fuc.r_0x002504 = ramfuc_reg(0x002504); 957 ram->fuc.r_0x004000 = ramfuc_reg(0x004000); 958 ram->fuc.r_0x004004 = ramfuc_reg(0x004004); 959 ram->fuc.r_0x004018 = ramfuc_reg(0x004018); 960 ram->fuc.r_0x004128 = ramfuc_reg(0x004128); 961 ram->fuc.r_0x004168 = ramfuc_reg(0x004168); 962 ram->fuc.r_0x100080 = ramfuc_reg(0x100080); 963 ram->fuc.r_0x100200 = ramfuc_reg(0x100200); 964 ram->fuc.r_0x100210 = ramfuc_reg(0x100210); 965 for (i = 0; i < 9; i++) 966 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4)); 967 ram->fuc.r_0x100264 = ramfuc_reg(0x100264); 968 ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0); 969 ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4); 970 ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc); 971 ram->fuc.r_0x10053c = ramfuc_reg(0x10053c); 972 ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0); 973 ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4); 974 ram->fuc.r_0x100700 = ramfuc_reg(0x100700); 975 ram->fuc.r_0x100714 = ramfuc_reg(0x100714); 976 ram->fuc.r_0x100718 = ramfuc_reg(0x100718); 977 ram->fuc.r_0x10071c = ramfuc_reg(0x10071c); 978 ram->fuc.r_0x100720 = ramfuc_reg(0x100720); 979 ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask); 980 ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask); 981 ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask); 982 ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask); 983 ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804); 984 ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask); 985 ram->fuc.r_0x111100 = ramfuc_reg(0x111100); 986 ram->fuc.r_0x111104 = ramfuc_reg(0x111104); 987 ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0); 988 ram->fuc.r_0x111400 = ramfuc_reg(0x111400); 989 ram->fuc.r_0x611200 = ramfuc_reg(0x611200); 990 991 if (ram->base.ranks > 1) { 992 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8); 993 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc); 994 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8); 995 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec); 996 } else { 997 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0); 998 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4); 999 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0); 1000 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4); 1001 } 1002 1003 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); 1004 if (ret == 0) { 1005 nv50_gpio_location(func.line, ®, &shift); 1006 ram->fuc.r_gpioFBVREF = ramfuc_reg(reg); 1007 } 1008 1009 return 0; 1010 } 1011 1012 struct nvkm_oclass 1013 gt215_ram_oclass = { 1014 .ofuncs = &(struct nvkm_ofuncs) { 1015 .ctor = gt215_ram_ctor, 1016 .dtor = _nvkm_ram_dtor, 1017 .init = gt215_ram_init, 1018 .fini = gt215_ram_fini, 1019 }, 1020 }; 1021