1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "ramfuc.h" 25 #include "gf100.h" 26 27 #include <core/option.h> 28 #include <subdev/bios.h> 29 #include <subdev/bios/init.h> 30 #include <subdev/bios/M0205.h> 31 #include <subdev/bios/M0209.h> 32 #include <subdev/bios/pll.h> 33 #include <subdev/bios/rammap.h> 34 #include <subdev/bios/timing.h> 35 #include <subdev/clk.h> 36 #include <subdev/clk/pll.h> 37 #include <subdev/gpio.h> 38 39 struct gk104_ramfuc { 40 struct ramfuc base; 41 42 struct nvbios_pll refpll; 43 struct nvbios_pll mempll; 44 45 struct ramfuc_reg r_gpioMV; 46 u32 r_funcMV[2]; 47 struct ramfuc_reg r_gpio2E; 48 u32 r_func2E[2]; 49 struct ramfuc_reg r_gpiotrig; 50 51 struct ramfuc_reg r_0x132020; 52 struct ramfuc_reg r_0x132028; 53 struct ramfuc_reg r_0x132024; 54 struct ramfuc_reg r_0x132030; 55 struct ramfuc_reg r_0x132034; 56 struct ramfuc_reg r_0x132000; 57 struct ramfuc_reg r_0x132004; 58 struct ramfuc_reg r_0x132040; 59 60 struct ramfuc_reg r_0x10f248; 61 struct ramfuc_reg r_0x10f290; 62 struct ramfuc_reg r_0x10f294; 63 struct ramfuc_reg r_0x10f298; 64 struct ramfuc_reg r_0x10f29c; 65 struct ramfuc_reg r_0x10f2a0; 66 struct ramfuc_reg r_0x10f2a4; 67 struct ramfuc_reg r_0x10f2a8; 68 struct ramfuc_reg r_0x10f2ac; 69 struct ramfuc_reg r_0x10f2cc; 70 struct ramfuc_reg r_0x10f2e8; 71 struct ramfuc_reg r_0x10f250; 72 struct ramfuc_reg r_0x10f24c; 73 struct ramfuc_reg r_0x10fec4; 74 struct ramfuc_reg r_0x10fec8; 75 struct ramfuc_reg r_0x10f604; 76 struct ramfuc_reg r_0x10f614; 77 struct ramfuc_reg r_0x10f610; 78 struct ramfuc_reg r_0x100770; 79 struct ramfuc_reg r_0x100778; 80 struct ramfuc_reg r_0x10f224; 81 82 struct ramfuc_reg r_0x10f870; 83 struct ramfuc_reg r_0x10f698; 84 struct ramfuc_reg r_0x10f694; 85 struct ramfuc_reg r_0x10f6b8; 86 struct ramfuc_reg r_0x10f808; 87 struct ramfuc_reg r_0x10f670; 88 struct ramfuc_reg r_0x10f60c; 89 struct ramfuc_reg r_0x10f830; 90 struct ramfuc_reg r_0x1373ec; 91 struct ramfuc_reg r_0x10f800; 92 struct ramfuc_reg r_0x10f82c; 93 94 struct ramfuc_reg r_0x10f978; 95 struct ramfuc_reg r_0x10f910; 96 struct ramfuc_reg r_0x10f914; 97 98 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ 99 100 struct ramfuc_reg r_0x62c000; 101 102 struct ramfuc_reg r_0x10f200; 103 104 struct ramfuc_reg r_0x10f210; 105 struct ramfuc_reg r_0x10f310; 106 struct ramfuc_reg r_0x10f314; 107 struct ramfuc_reg r_0x10f318; 108 struct ramfuc_reg r_0x10f090; 109 struct ramfuc_reg r_0x10f69c; 110 struct ramfuc_reg r_0x10f824; 111 struct ramfuc_reg r_0x1373f0; 112 struct ramfuc_reg r_0x1373f4; 113 struct ramfuc_reg r_0x137320; 114 struct ramfuc_reg r_0x10f65c; 115 struct ramfuc_reg r_0x10f6bc; 116 struct ramfuc_reg r_0x100710; 117 struct ramfuc_reg r_0x100750; 118 }; 119 120 struct gk104_ram { 121 struct nvkm_ram base; 122 struct gk104_ramfuc fuc; 123 124 struct list_head cfg; 125 u32 parts; 126 u32 pmask; 127 u32 pnuts; 128 129 struct nvbios_ramcfg diff; 130 int from; 131 int mode; 132 int N1, fN1, M1, P1; 133 int N2, M2, P2; 134 }; 135 136 /******************************************************************************* 137 * GDDR5 138 ******************************************************************************/ 139 static void 140 gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data) 141 { 142 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 143 u32 addr = 0x110974, i; 144 145 ram_mask(fuc, 0x10f910, mask, data); 146 ram_mask(fuc, 0x10f914, mask, data); 147 148 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { 149 if (ram->pmask & (1 << i)) 150 continue; 151 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); 152 } 153 } 154 155 static void 156 r1373f4_init(struct gk104_ramfuc *fuc) 157 { 158 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 159 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); 160 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 161 const u32 runk0 = ram->fN1 << 16; 162 const u32 runk1 = ram->fN1; 163 164 if (ram->from == 2) { 165 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); 166 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); 167 } else { 168 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 169 } 170 171 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 172 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 173 174 /* (re)program refpll, if required */ 175 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || 176 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { 177 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 178 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); 179 ram_wr32(fuc, 0x137320, 0x00000000); 180 ram_mask(fuc, 0x132030, 0xffff0000, runk0); 181 ram_mask(fuc, 0x132034, 0x0000ffff, runk1); 182 ram_wr32(fuc, 0x132024, rcoef); 183 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); 184 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); 185 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); 186 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); 187 } 188 189 /* (re)program mempll, if required */ 190 if (ram->mode == 2) { 191 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 192 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000); 193 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 194 ram_mask(fuc, 0x132004, 0x103fffff, mcoef); 195 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); 196 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000); 197 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); 198 } else { 199 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100); 200 } 201 202 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); 203 } 204 205 static void 206 r1373f4_fini(struct gk104_ramfuc *fuc) 207 { 208 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 209 struct nvkm_ram_data *next = ram->base.next; 210 u8 v0 = next->bios.ramcfg_11_03_c0; 211 u8 v1 = next->bios.ramcfg_11_03_30; 212 u32 tmp; 213 214 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 215 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16)); 216 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000); 217 if (ram->mode == 2) { 218 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002); 219 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000); 220 } else { 221 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001); 222 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000); 223 } 224 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); 225 } 226 227 static void 228 gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, 229 u32 _mask, u32 _data, u32 _copy) 230 { 231 struct gk104_fb_priv *priv = (void *)nvkm_fb(ram); 232 struct ramfuc *fuc = &ram->fuc.base; 233 u32 addr = 0x110000 + (reg->addr & 0xfff); 234 u32 mask = _mask | _copy; 235 u32 data = (_data & _mask) | (reg->data & _copy); 236 u32 i; 237 238 for (i = 0; i < 16; i++, addr += 0x1000) { 239 if (ram->pnuts & (1 << i)) { 240 u32 prev = nv_rd32(priv, addr); 241 u32 next = (prev & ~mask) | data; 242 nvkm_memx_wr32(fuc->memx, addr, next); 243 } 244 } 245 } 246 #define ram_nuts(s,r,m,d,c) \ 247 gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) 248 249 static int 250 gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq) 251 { 252 struct gk104_ram *ram = (void *)pfb->ram; 253 struct gk104_ramfuc *fuc = &ram->fuc; 254 struct nvkm_ram_data *next = ram->base.next; 255 int vc = !next->bios.ramcfg_11_02_08; 256 int mv = !next->bios.ramcfg_11_02_04; 257 u32 mask, data; 258 259 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 260 ram_block(fuc); 261 ram_wr32(fuc, 0x62c000, 0x0f0f0000); 262 263 /* MR1: turn termination on early, for some reason.. */ 264 if ((ram->base.mr[1] & 0x03c) != 0x030) { 265 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); 266 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); 267 } 268 269 if (vc == 1 && ram_have(fuc, gpio2E)) { 270 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); 271 if (temp != ram_rd32(fuc, gpio2E)) { 272 ram_wr32(fuc, gpiotrig, 1); 273 ram_nsec(fuc, 20000); 274 } 275 } 276 277 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 278 279 gk104_ram_train(fuc, 0x01020000, 0x000c0000); 280 281 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ 282 ram_nsec(fuc, 1000); 283 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 284 ram_nsec(fuc, 1000); 285 286 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 287 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 288 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 289 ram_wr32(fuc, 0x10f090, 0x00000061); 290 ram_wr32(fuc, 0x10f090, 0xc000007f); 291 ram_nsec(fuc, 1000); 292 293 ram_wr32(fuc, 0x10f698, 0x00000000); 294 ram_wr32(fuc, 0x10f69c, 0x00000000); 295 296 /*XXX: there does appear to be some kind of condition here, simply 297 * modifying these bits in the vbios from the default pl0 298 * entries shows no change. however, the data does appear to 299 * be correct and may be required for the transition back 300 */ 301 mask = 0x800f07e0; 302 data = 0x00030000; 303 if (ram_rd32(fuc, 0x10f978) & 0x00800000) 304 data |= 0x00040000; 305 306 if (1) { 307 data |= 0x800807e0; 308 switch (next->bios.ramcfg_11_03_c0) { 309 case 3: data &= ~0x00000040; break; 310 case 2: data &= ~0x00000100; break; 311 case 1: data &= ~0x80000000; break; 312 case 0: data &= ~0x00000400; break; 313 } 314 315 switch (next->bios.ramcfg_11_03_30) { 316 case 3: data &= ~0x00000020; break; 317 case 2: data &= ~0x00000080; break; 318 case 1: data &= ~0x00080000; break; 319 case 0: data &= ~0x00000200; break; 320 } 321 } 322 323 if (next->bios.ramcfg_11_02_80) 324 mask |= 0x03000000; 325 if (next->bios.ramcfg_11_02_40) 326 mask |= 0x00002000; 327 if (next->bios.ramcfg_11_07_10) 328 mask |= 0x00004000; 329 if (next->bios.ramcfg_11_07_08) 330 mask |= 0x00000003; 331 else { 332 mask |= 0x34000000; 333 if (ram_rd32(fuc, 0x10f978) & 0x00800000) 334 mask |= 0x40000000; 335 } 336 ram_mask(fuc, 0x10f824, mask, data); 337 338 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); 339 340 if (ram->from == 2 && ram->mode != 2) { 341 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); 342 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); 343 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); 344 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); 345 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 346 r1373f4_init(fuc); 347 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); 348 r1373f4_fini(fuc); 349 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); 350 } else 351 if (ram->from != 2 && ram->mode != 2) { 352 r1373f4_init(fuc); 353 r1373f4_fini(fuc); 354 } 355 356 if (ram_have(fuc, gpioMV)) { 357 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); 358 if (temp != ram_rd32(fuc, gpioMV)) { 359 ram_wr32(fuc, gpiotrig, 1); 360 ram_nsec(fuc, 64000); 361 } 362 } 363 364 if (next->bios.ramcfg_11_02_40 || 365 next->bios.ramcfg_11_07_10) { 366 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 367 ram_nsec(fuc, 20000); 368 } 369 370 if (ram->from != 2 && ram->mode == 2) { 371 if (0 /*XXX: Titan */) 372 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); 373 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 374 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); 375 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); 376 r1373f4_init(fuc); 377 r1373f4_fini(fuc); 378 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); 379 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); 380 } else 381 if (ram->from == 2 && ram->mode == 2) { 382 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 383 r1373f4_init(fuc); 384 r1373f4_fini(fuc); 385 } 386 387 if (ram->mode != 2) /*XXX*/ { 388 if (next->bios.ramcfg_11_07_40) 389 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 390 } 391 392 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); 393 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); 394 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); 395 396 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { 397 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); 398 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); 399 } else 400 if (!next->bios.ramcfg_11_07_08) { 401 ram_wr32(fuc, 0x10f698, 0x00000000); 402 ram_wr32(fuc, 0x10f69c, 0x00000000); 403 } 404 405 if (ram->mode != 2) { 406 u32 data = 0x01000100 * next->bios.ramcfg_11_04; 407 ram_nuke(fuc, 0x10f694); 408 ram_mask(fuc, 0x10f694, 0xff00ff00, data); 409 } 410 411 if (ram->mode == 2 && next->bios.ramcfg_11_08_10) 412 data = 0x00000080; 413 else 414 data = 0x00000000; 415 ram_mask(fuc, 0x10f60c, 0x00000080, data); 416 417 mask = 0x00070000; 418 data = 0x00000000; 419 if (!next->bios.ramcfg_11_02_80) 420 data |= 0x03000000; 421 if (!next->bios.ramcfg_11_02_40) 422 data |= 0x00002000; 423 if (!next->bios.ramcfg_11_07_10) 424 data |= 0x00004000; 425 if (!next->bios.ramcfg_11_07_08) 426 data |= 0x00000003; 427 else 428 data |= 0x74000000; 429 ram_mask(fuc, 0x10f824, mask, data); 430 431 if (next->bios.ramcfg_11_01_08) 432 data = 0x00000000; 433 else 434 data = 0x00001000; 435 ram_mask(fuc, 0x10f200, 0x00001000, data); 436 437 if (ram_rd32(fuc, 0x10f670) & 0x80000000) { 438 ram_nsec(fuc, 10000); 439 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); 440 } 441 442 if (next->bios.ramcfg_11_08_01) 443 data = 0x00100000; 444 else 445 data = 0x00000000; 446 ram_mask(fuc, 0x10f82c, 0x00100000, data); 447 448 data = 0x00000000; 449 if (next->bios.ramcfg_11_08_08) 450 data |= 0x00002000; 451 if (next->bios.ramcfg_11_08_04) 452 data |= 0x00001000; 453 if (next->bios.ramcfg_11_08_02) 454 data |= 0x00004000; 455 ram_mask(fuc, 0x10f830, 0x00007000, data); 456 457 /* PFB timing */ 458 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); 459 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); 460 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); 461 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); 462 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); 463 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); 464 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); 465 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); 466 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); 467 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); 468 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); 469 470 data = mask = 0x00000000; 471 if (ram->diff.ramcfg_11_08_20) { 472 if (next->bios.ramcfg_11_08_20) 473 data |= 0x01000000; 474 mask |= 0x01000000; 475 } 476 ram_mask(fuc, 0x10f200, mask, data); 477 478 data = mask = 0x00000000; 479 if (ram->diff.ramcfg_11_02_03) { 480 data |= next->bios.ramcfg_11_02_03 << 8; 481 mask |= 0x00000300; 482 } 483 if (ram->diff.ramcfg_11_01_10) { 484 if (next->bios.ramcfg_11_01_10) 485 data |= 0x70000000; 486 mask |= 0x70000000; 487 } 488 ram_mask(fuc, 0x10f604, mask, data); 489 490 data = mask = 0x00000000; 491 if (ram->diff.timing_20_30_07) { 492 data |= next->bios.timing_20_30_07 << 28; 493 mask |= 0x70000000; 494 } 495 if (ram->diff.ramcfg_11_01_01) { 496 if (next->bios.ramcfg_11_01_01) 497 data |= 0x00000100; 498 mask |= 0x00000100; 499 } 500 ram_mask(fuc, 0x10f614, mask, data); 501 502 data = mask = 0x00000000; 503 if (ram->diff.timing_20_30_07) { 504 data |= next->bios.timing_20_30_07 << 28; 505 mask |= 0x70000000; 506 } 507 if (ram->diff.ramcfg_11_01_02) { 508 if (next->bios.ramcfg_11_01_02) 509 data |= 0x00000100; 510 mask |= 0x00000100; 511 } 512 ram_mask(fuc, 0x10f610, mask, data); 513 514 mask = 0x33f00000; 515 data = 0x00000000; 516 if (!next->bios.ramcfg_11_01_04) 517 data |= 0x20200000; 518 if (!next->bios.ramcfg_11_07_80) 519 data |= 0x12800000; 520 /*XXX: see note above about there probably being some condition 521 * for the 10f824 stuff that uses ramcfg 3... 522 */ 523 if (next->bios.ramcfg_11_03_f0) { 524 if (next->bios.rammap_11_08_0c) { 525 if (!next->bios.ramcfg_11_07_80) 526 mask |= 0x00000020; 527 else 528 data |= 0x00000020; 529 mask |= 0x00000004; 530 } 531 } else { 532 mask |= 0x40000020; 533 data |= 0x00000004; 534 } 535 536 ram_mask(fuc, 0x10f808, mask, data); 537 538 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); 539 540 data = mask = 0x00000000; 541 if (ram->diff.ramcfg_11_02_03) { 542 data |= next->bios.ramcfg_11_02_03; 543 mask |= 0x00000003; 544 } 545 if (ram->diff.ramcfg_11_01_10) { 546 if (next->bios.ramcfg_11_01_10) 547 data |= 0x00000004; 548 mask |= 0x00000004; 549 } 550 551 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { 552 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); 553 ram_wr32(fuc, 0x100710, 0x00000000); 554 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 555 } 556 557 data = next->bios.timing_20_30_07 << 8; 558 if (next->bios.ramcfg_11_01_01) 559 data |= 0x80000000; 560 ram_mask(fuc, 0x100778, 0x00000700, data); 561 562 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); 563 data = (next->bios.timing[10] & 0x7f000000) >> 24; 564 if (data < next->bios.timing_20_2c_1fc0) 565 data = next->bios.timing_20_2c_1fc0; 566 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 567 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 568 569 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | 570 next->bios.timing_20_31_0780 << 17 | 571 next->bios.timing_20_31_0078 << 8 | 572 next->bios.timing_20_31_0007); 573 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | 574 next->bios.timing_20_31_7000); 575 576 ram_wr32(fuc, 0x10f090, 0x4000007e); 577 ram_nsec(fuc, 2000); 578 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 579 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 580 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 581 582 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { 583 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 584 gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ 585 ram_nsec(fuc, 1000); 586 ram_wr32(fuc, 0x10f294, temp); 587 } 588 589 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]); 590 ram_wr32(fuc, mr[0], ram->base.mr[0]); 591 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); 592 ram_nsec(fuc, 1000); 593 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); 594 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ 595 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); 596 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); 597 598 if (vc == 0 && ram_have(fuc, gpio2E)) { 599 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); 600 if (temp != ram_rd32(fuc, gpio2E)) { 601 ram_wr32(fuc, gpiotrig, 1); 602 ram_nsec(fuc, 20000); 603 } 604 } 605 606 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 607 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 608 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 609 ram_nsec(fuc, 1000); 610 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); 611 612 data = ram_rd32(fuc, 0x10f978); 613 data &= ~0x00046144; 614 data |= 0x0000000b; 615 if (!next->bios.ramcfg_11_07_08) { 616 if (!next->bios.ramcfg_11_07_04) 617 data |= 0x0000200c; 618 else 619 data |= 0x00000000; 620 } else { 621 data |= 0x00040044; 622 } 623 ram_wr32(fuc, 0x10f978, data); 624 625 if (ram->mode == 1) { 626 data = ram_rd32(fuc, 0x10f830) | 0x00000001; 627 ram_wr32(fuc, 0x10f830, data); 628 } 629 630 if (!next->bios.ramcfg_11_07_08) { 631 data = 0x88020000; 632 if ( next->bios.ramcfg_11_07_04) 633 data |= 0x10000000; 634 if (!next->bios.rammap_11_08_10) 635 data |= 0x00080000; 636 } else { 637 data = 0xa40e0000; 638 } 639 gk104_ram_train(fuc, 0xbc0f0000, data); 640 if (1) /* XXX: not always? */ 641 ram_nsec(fuc, 1000); 642 643 if (ram->mode == 2) { /*XXX*/ 644 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); 645 } 646 647 /* LP3 */ 648 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) 649 ram_nsec(fuc, 1000); 650 651 if (ram->mode != 2) { 652 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); 653 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 654 } 655 656 if (next->bios.ramcfg_11_07_02) 657 gk104_ram_train(fuc, 0x80020000, 0x01000000); 658 659 ram_unblock(fuc); 660 ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 661 662 if (next->bios.rammap_11_08_01) 663 data = 0x00000800; 664 else 665 data = 0x00000000; 666 ram_mask(fuc, 0x10f200, 0x00000800, data); 667 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); 668 return 0; 669 } 670 671 /******************************************************************************* 672 * DDR3 673 ******************************************************************************/ 674 675 static int 676 gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq) 677 { 678 struct gk104_ram *ram = (void *)pfb->ram; 679 struct gk104_ramfuc *fuc = &ram->fuc; 680 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 681 const u32 runk0 = ram->fN1 << 16; 682 const u32 runk1 = ram->fN1; 683 struct nvkm_ram_data *next = ram->base.next; 684 int vc = !next->bios.ramcfg_11_02_08; 685 int mv = !next->bios.ramcfg_11_02_04; 686 u32 mask, data; 687 688 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 689 ram_block(fuc); 690 ram_wr32(fuc, 0x62c000, 0x0f0f0000); 691 692 if (vc == 1 && ram_have(fuc, gpio2E)) { 693 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); 694 if (temp != ram_rd32(fuc, gpio2E)) { 695 ram_wr32(fuc, gpiotrig, 1); 696 ram_nsec(fuc, 20000); 697 } 698 } 699 700 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 701 if (next->bios.ramcfg_11_03_f0) 702 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); 703 704 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 705 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ 706 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 707 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 708 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 709 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 710 ram_nsec(fuc, 1000); 711 712 ram_wr32(fuc, 0x10f090, 0x00000060); 713 ram_wr32(fuc, 0x10f090, 0xc000007e); 714 715 /*XXX: there does appear to be some kind of condition here, simply 716 * modifying these bits in the vbios from the default pl0 717 * entries shows no change. however, the data does appear to 718 * be correct and may be required for the transition back 719 */ 720 mask = 0x00010000; 721 data = 0x00010000; 722 723 if (1) { 724 mask |= 0x800807e0; 725 data |= 0x800807e0; 726 switch (next->bios.ramcfg_11_03_c0) { 727 case 3: data &= ~0x00000040; break; 728 case 2: data &= ~0x00000100; break; 729 case 1: data &= ~0x80000000; break; 730 case 0: data &= ~0x00000400; break; 731 } 732 733 switch (next->bios.ramcfg_11_03_30) { 734 case 3: data &= ~0x00000020; break; 735 case 2: data &= ~0x00000080; break; 736 case 1: data &= ~0x00080000; break; 737 case 0: data &= ~0x00000200; break; 738 } 739 } 740 741 if (next->bios.ramcfg_11_02_80) 742 mask |= 0x03000000; 743 if (next->bios.ramcfg_11_02_40) 744 mask |= 0x00002000; 745 if (next->bios.ramcfg_11_07_10) 746 mask |= 0x00004000; 747 if (next->bios.ramcfg_11_07_08) 748 mask |= 0x00000003; 749 else 750 mask |= 0x14000000; 751 ram_mask(fuc, 0x10f824, mask, data); 752 753 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); 754 755 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 756 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 757 data |= next->bios.ramcfg_11_03_30 << 16; 758 ram_wr32(fuc, 0x1373ec, data); 759 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 760 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 761 762 /* (re)program refpll, if required */ 763 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || 764 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { 765 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 766 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); 767 ram_wr32(fuc, 0x137320, 0x00000000); 768 ram_mask(fuc, 0x132030, 0xffff0000, runk0); 769 ram_mask(fuc, 0x132034, 0x0000ffff, runk1); 770 ram_wr32(fuc, 0x132024, rcoef); 771 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); 772 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); 773 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); 774 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); 775 } 776 777 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010); 778 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); 779 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 780 781 if (ram_have(fuc, gpioMV)) { 782 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); 783 if (temp != ram_rd32(fuc, gpioMV)) { 784 ram_wr32(fuc, gpiotrig, 1); 785 ram_nsec(fuc, 64000); 786 } 787 } 788 789 if (next->bios.ramcfg_11_02_40 || 790 next->bios.ramcfg_11_07_10) { 791 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 792 ram_nsec(fuc, 20000); 793 } 794 795 if (ram->mode != 2) /*XXX*/ { 796 if (next->bios.ramcfg_11_07_40) 797 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 798 } 799 800 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); 801 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); 802 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); 803 804 mask = 0x00010000; 805 data = 0x00000000; 806 if (!next->bios.ramcfg_11_02_80) 807 data |= 0x03000000; 808 if (!next->bios.ramcfg_11_02_40) 809 data |= 0x00002000; 810 if (!next->bios.ramcfg_11_07_10) 811 data |= 0x00004000; 812 if (!next->bios.ramcfg_11_07_08) 813 data |= 0x00000003; 814 else 815 data |= 0x14000000; 816 ram_mask(fuc, 0x10f824, mask, data); 817 ram_nsec(fuc, 1000); 818 819 if (next->bios.ramcfg_11_08_01) 820 data = 0x00100000; 821 else 822 data = 0x00000000; 823 ram_mask(fuc, 0x10f82c, 0x00100000, data); 824 825 /* PFB timing */ 826 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); 827 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); 828 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); 829 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); 830 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); 831 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); 832 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); 833 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); 834 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); 835 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); 836 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); 837 838 mask = 0x33f00000; 839 data = 0x00000000; 840 if (!next->bios.ramcfg_11_01_04) 841 data |= 0x20200000; 842 if (!next->bios.ramcfg_11_07_80) 843 data |= 0x12800000; 844 /*XXX: see note above about there probably being some condition 845 * for the 10f824 stuff that uses ramcfg 3... 846 */ 847 if (next->bios.ramcfg_11_03_f0) { 848 if (next->bios.rammap_11_08_0c) { 849 if (!next->bios.ramcfg_11_07_80) 850 mask |= 0x00000020; 851 else 852 data |= 0x00000020; 853 mask |= 0x08000004; 854 } 855 data |= 0x04000000; 856 } else { 857 mask |= 0x44000020; 858 data |= 0x08000004; 859 } 860 861 ram_mask(fuc, 0x10f808, mask, data); 862 863 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); 864 865 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); 866 867 data = (next->bios.timing[10] & 0x7f000000) >> 24; 868 if (data < next->bios.timing_20_2c_1fc0) 869 data = next->bios.timing_20_2c_1fc0; 870 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 871 872 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 873 874 ram_wr32(fuc, 0x10f090, 0x4000007f); 875 ram_nsec(fuc, 1000); 876 877 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 878 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 879 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 880 ram_nsec(fuc, 1000); 881 882 ram_nuke(fuc, mr[0]); 883 ram_mask(fuc, mr[0], 0x100, 0x100); 884 ram_mask(fuc, mr[0], 0x100, 0x000); 885 886 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]); 887 ram_wr32(fuc, mr[0], ram->base.mr[0]); 888 ram_nsec(fuc, 1000); 889 890 ram_nuke(fuc, mr[0]); 891 ram_mask(fuc, mr[0], 0x100, 0x100); 892 ram_mask(fuc, mr[0], 0x100, 0x000); 893 894 if (vc == 0 && ram_have(fuc, gpio2E)) { 895 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); 896 if (temp != ram_rd32(fuc, gpio2E)) { 897 ram_wr32(fuc, gpiotrig, 1); 898 ram_nsec(fuc, 20000); 899 } 900 } 901 902 if (ram->mode != 2) { 903 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); 904 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 905 } 906 907 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 908 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 909 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 910 ram_nsec(fuc, 1000); 911 912 ram_unblock(fuc); 913 ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 914 915 if (next->bios.rammap_11_08_01) 916 data = 0x00000800; 917 else 918 data = 0x00000000; 919 ram_mask(fuc, 0x10f200, 0x00000800, data); 920 return 0; 921 } 922 923 /******************************************************************************* 924 * main hooks 925 ******************************************************************************/ 926 927 static int 928 gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data) 929 { 930 struct gk104_ram *ram = (void *)pfb->ram; 931 struct nvkm_ram_data *cfg; 932 u32 mhz = khz / 1000; 933 934 list_for_each_entry(cfg, &ram->cfg, head) { 935 if (mhz >= cfg->bios.rammap_min && 936 mhz <= cfg->bios.rammap_max) { 937 *data = *cfg; 938 data->freq = khz; 939 return 0; 940 } 941 } 942 943 nv_error(ram, "ramcfg data for %dMHz not found\n", mhz); 944 return -EINVAL; 945 } 946 947 static int 948 gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) 949 { 950 struct gk104_ram *ram = (void *)pfb->ram; 951 struct gk104_ramfuc *fuc = &ram->fuc; 952 int refclk, i; 953 int ret; 954 955 ret = ram_init(fuc, pfb); 956 if (ret) 957 return ret; 958 959 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; 960 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; 961 962 /* XXX: this is *not* what nvidia do. on fermi nvidia generally 963 * select, based on some unknown condition, one of the two possible 964 * reference frequencies listed in the vbios table for mempll and 965 * program refpll to that frequency. 966 * 967 * so far, i've seen very weird values being chosen by nvidia on 968 * kepler boards, no idea how/why they're chosen. 969 */ 970 refclk = next->freq; 971 if (ram->mode == 2) 972 refclk = fuc->mempll.refclk; 973 974 /* calculate refpll coefficients */ 975 ret = gt215_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, 976 &ram->fN1, &ram->M1, &ram->P1); 977 fuc->mempll.refclk = ret; 978 if (ret <= 0) { 979 nv_error(pfb, "unable to calc refpll\n"); 980 return -EINVAL; 981 } 982 983 /* calculate mempll coefficients, if we're using it */ 984 if (ram->mode == 2) { 985 /* post-divider doesn't work... the reg takes the values but 986 * appears to completely ignore it. there *is* a bit at 987 * bit 28 that appears to divide the clock by 2 if set. 988 */ 989 fuc->mempll.min_p = 1; 990 fuc->mempll.max_p = 2; 991 992 ret = gt215_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, 993 &ram->N2, NULL, &ram->M2, &ram->P2); 994 if (ret <= 0) { 995 nv_error(pfb, "unable to calc mempll\n"); 996 return -EINVAL; 997 } 998 } 999 1000 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) { 1001 if (ram_have(fuc, mr[i])) 1002 ram->base.mr[i] = ram_rd32(fuc, mr[i]); 1003 } 1004 ram->base.freq = next->freq; 1005 1006 switch (ram->base.type) { 1007 case NV_MEM_TYPE_DDR3: 1008 ret = nvkm_sddr3_calc(&ram->base); 1009 if (ret == 0) 1010 ret = gk104_ram_calc_sddr3(pfb, next->freq); 1011 break; 1012 case NV_MEM_TYPE_GDDR5: 1013 ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); 1014 if (ret == 0) 1015 ret = gk104_ram_calc_gddr5(pfb, next->freq); 1016 break; 1017 default: 1018 ret = -ENOSYS; 1019 break; 1020 } 1021 1022 return ret; 1023 } 1024 1025 static int 1026 gk104_ram_calc(struct nvkm_fb *pfb, u32 freq) 1027 { 1028 struct nvkm_clk *clk = nvkm_clk(pfb); 1029 struct gk104_ram *ram = (void *)pfb->ram; 1030 struct nvkm_ram_data *xits = &ram->base.xition; 1031 struct nvkm_ram_data *copy; 1032 int ret; 1033 1034 if (ram->base.next == NULL) { 1035 ret = gk104_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), 1036 &ram->base.former); 1037 if (ret) 1038 return ret; 1039 1040 ret = gk104_ram_calc_data(pfb, freq, &ram->base.target); 1041 if (ret) 1042 return ret; 1043 1044 if (ram->base.target.freq < ram->base.former.freq) { 1045 *xits = ram->base.target; 1046 copy = &ram->base.former; 1047 } else { 1048 *xits = ram->base.former; 1049 copy = &ram->base.target; 1050 } 1051 1052 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; 1053 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; 1054 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; 1055 1056 ram->base.next = &ram->base.target; 1057 if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) 1058 ram->base.next = &ram->base.xition; 1059 } else { 1060 BUG_ON(ram->base.next != &ram->base.xition); 1061 ram->base.next = &ram->base.target; 1062 } 1063 1064 return gk104_ram_calc_xits(pfb, ram->base.next); 1065 } 1066 1067 static void 1068 gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) 1069 { 1070 struct gk104_ram *ram = (void *)pfb->ram; 1071 struct nvkm_ram_data *cfg; 1072 u32 mhz = freq / 1000; 1073 u32 mask, data; 1074 1075 list_for_each_entry(cfg, &ram->cfg, head) { 1076 if (mhz >= cfg->bios.rammap_min && 1077 mhz <= cfg->bios.rammap_max) 1078 break; 1079 } 1080 1081 if (&cfg->head == &ram->cfg) 1082 return; 1083 1084 if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { 1085 data |= cfg->bios.rammap_11_0a_03fe << 12; 1086 mask |= 0x001ff000; 1087 } 1088 if (ram->diff.rammap_11_09_01ff) { 1089 data |= cfg->bios.rammap_11_09_01ff; 1090 mask |= 0x000001ff; 1091 } 1092 nv_mask(pfb, 0x10f468, mask, data); 1093 1094 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { 1095 data |= cfg->bios.rammap_11_0a_0400; 1096 mask |= 0x00000001; 1097 } 1098 nv_mask(pfb, 0x10f420, mask, data); 1099 1100 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { 1101 data |= cfg->bios.rammap_11_0a_0800; 1102 mask |= 0x00000001; 1103 } 1104 nv_mask(pfb, 0x10f430, mask, data); 1105 1106 if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { 1107 data |= cfg->bios.rammap_11_0b_01f0; 1108 mask |= 0x0000001f; 1109 } 1110 nv_mask(pfb, 0x10f400, mask, data); 1111 1112 if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { 1113 data |= cfg->bios.rammap_11_0b_0200 << 9; 1114 mask |= 0x00000200; 1115 } 1116 nv_mask(pfb, 0x10f410, mask, data); 1117 1118 if (mask = 0, data = 0, ram->diff.rammap_11_0d) { 1119 data |= cfg->bios.rammap_11_0d << 16; 1120 mask |= 0x00ff0000; 1121 } 1122 if (ram->diff.rammap_11_0f) { 1123 data |= cfg->bios.rammap_11_0f << 8; 1124 mask |= 0x0000ff00; 1125 } 1126 nv_mask(pfb, 0x10f440, mask, data); 1127 1128 if (mask = 0, data = 0, ram->diff.rammap_11_0e) { 1129 data |= cfg->bios.rammap_11_0e << 8; 1130 mask |= 0x0000ff00; 1131 } 1132 if (ram->diff.rammap_11_0b_0800) { 1133 data |= cfg->bios.rammap_11_0b_0800 << 7; 1134 mask |= 0x00000080; 1135 } 1136 if (ram->diff.rammap_11_0b_0400) { 1137 data |= cfg->bios.rammap_11_0b_0400 << 5; 1138 mask |= 0x00000020; 1139 } 1140 nv_mask(pfb, 0x10f444, mask, data); 1141 } 1142 1143 static int 1144 gk104_ram_prog(struct nvkm_fb *pfb) 1145 { 1146 struct nvkm_device *device = nv_device(pfb); 1147 struct gk104_ram *ram = (void *)pfb->ram; 1148 struct gk104_ramfuc *fuc = &ram->fuc; 1149 struct nvkm_ram_data *next = ram->base.next; 1150 1151 if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) { 1152 ram_exec(fuc, false); 1153 return (ram->base.next == &ram->base.xition); 1154 } 1155 1156 gk104_ram_prog_0(pfb, 1000); 1157 ram_exec(fuc, true); 1158 gk104_ram_prog_0(pfb, next->freq); 1159 1160 return (ram->base.next == &ram->base.xition); 1161 } 1162 1163 static void 1164 gk104_ram_tidy(struct nvkm_fb *pfb) 1165 { 1166 struct gk104_ram *ram = (void *)pfb->ram; 1167 struct gk104_ramfuc *fuc = &ram->fuc; 1168 ram->base.next = NULL; 1169 ram_exec(fuc, false); 1170 } 1171 1172 struct gk104_ram_train { 1173 u16 mask; 1174 struct nvbios_M0209S remap; 1175 struct nvbios_M0209S type00; 1176 struct nvbios_M0209S type01; 1177 struct nvbios_M0209S type04; 1178 struct nvbios_M0209S type06; 1179 struct nvbios_M0209S type07; 1180 struct nvbios_M0209S type08; 1181 struct nvbios_M0209S type09; 1182 }; 1183 1184 static int 1185 gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg, 1186 struct gk104_ram_train *train) 1187 { 1188 struct nvkm_bios *bios = nvkm_bios(pfb); 1189 struct nvbios_M0205E M0205E; 1190 struct nvbios_M0205S M0205S; 1191 struct nvbios_M0209E M0209E; 1192 struct nvbios_M0209S *remap = &train->remap; 1193 struct nvbios_M0209S *value; 1194 u8 ver, hdr, cnt, len; 1195 u32 data; 1196 1197 /* determine type of data for this index */ 1198 if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))) 1199 return -ENOENT; 1200 1201 switch (M0205E.type) { 1202 case 0x00: value = &train->type00; break; 1203 case 0x01: value = &train->type01; break; 1204 case 0x04: value = &train->type04; break; 1205 case 0x06: value = &train->type06; break; 1206 case 0x07: value = &train->type07; break; 1207 case 0x08: value = &train->type08; break; 1208 case 0x09: value = &train->type09; break; 1209 default: 1210 return 0; 1211 } 1212 1213 /* training data index determined by ramcfg strap */ 1214 if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S))) 1215 return -EINVAL; 1216 i = M0205S.data; 1217 1218 /* training data format information */ 1219 if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E))) 1220 return -EINVAL; 1221 1222 /* ... and the raw data */ 1223 if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value))) 1224 return -EINVAL; 1225 1226 if (M0209E.v02_07 == 2) { 1227 /* of course! why wouldn't we have a pointer to another entry 1228 * in the same table, and use the first one as an array of 1229 * remap indices... 1230 */ 1231 if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr, 1232 remap))) 1233 return -EINVAL; 1234 1235 for (i = 0; i < ARRAY_SIZE(value->data); i++) 1236 value->data[i] = remap->data[value->data[i]]; 1237 } else 1238 if (M0209E.v02_07 != 1) 1239 return -EINVAL; 1240 1241 train->mask |= 1 << M0205E.type; 1242 return 0; 1243 } 1244 1245 static int 1246 gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train) 1247 { 1248 int i, j; 1249 1250 if ((train->mask & 0x03d3) != 0x03d3) { 1251 nv_warn(pfb, "missing link training data\n"); 1252 return -EINVAL; 1253 } 1254 1255 for (i = 0; i < 0x30; i++) { 1256 for (j = 0; j < 8; j += 4) { 1257 nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8)); 1258 nv_wr32(pfb, 0x10f920 + j, 0x00000000 | 1259 train->type08.data[i] << 4 | 1260 train->type06.data[i]); 1261 nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]); 1262 nv_wr32(pfb, 0x10f920 + j, 0x00000100 | 1263 train->type09.data[i] << 4 | 1264 train->type07.data[i]); 1265 nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]); 1266 } 1267 } 1268 1269 for (j = 0; j < 8; j += 4) { 1270 for (i = 0; i < 0x100; i++) { 1271 nv_wr32(pfb, 0x10f968 + j, i); 1272 nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]); 1273 } 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int 1280 gk104_ram_train_init(struct nvkm_fb *pfb) 1281 { 1282 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); 1283 struct gk104_ram_train *train; 1284 int ret = -ENOMEM, i; 1285 1286 if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) { 1287 for (i = 0; i < 0x100; i++) { 1288 ret = gk104_ram_train_type(pfb, i, ramcfg, train); 1289 if (ret && ret != -ENOENT) 1290 break; 1291 } 1292 } 1293 1294 switch (pfb->ram->type) { 1295 case NV_MEM_TYPE_GDDR5: 1296 ret = gk104_ram_train_init_0(pfb, train); 1297 break; 1298 default: 1299 ret = 0; 1300 break; 1301 } 1302 1303 kfree(train); 1304 return ret; 1305 } 1306 1307 int 1308 gk104_ram_init(struct nvkm_object *object) 1309 { 1310 struct nvkm_fb *pfb = (void *)object->parent; 1311 struct gk104_ram *ram = (void *)object; 1312 struct nvkm_bios *bios = nvkm_bios(pfb); 1313 u8 ver, hdr, cnt, len, snr, ssz; 1314 u32 data, save; 1315 int ret, i; 1316 1317 ret = nvkm_ram_init(&ram->base); 1318 if (ret) 1319 return ret; 1320 1321 /* run a bunch of tables from rammap table. there's actually 1322 * individual pointers for each rammap entry too, but, nvidia 1323 * seem to just run the last two entries' scripts early on in 1324 * their init, and never again.. we'll just run 'em all once 1325 * for now. 1326 * 1327 * i strongly suspect that each script is for a separate mode 1328 * (likely selected by 0x10f65c's lower bits?), and the 1329 * binary driver skips the one that's already been setup by 1330 * the init tables. 1331 */ 1332 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); 1333 if (!data || hdr < 0x15) 1334 return -EINVAL; 1335 1336 cnt = nv_ro08(bios, data + 0x14); /* guess at count */ 1337 data = nv_ro32(bios, data + 0x10); /* guess u32... */ 1338 save = nv_rd32(pfb, 0x10f65c) & 0x000000f0; 1339 for (i = 0; i < cnt; i++, data += 4) { 1340 if (i != save >> 4) { 1341 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); 1342 nvbios_exec(&(struct nvbios_init) { 1343 .subdev = nv_subdev(pfb), 1344 .bios = bios, 1345 .offset = nv_ro32(bios, data), 1346 .execute = 1, 1347 }); 1348 } 1349 } 1350 nv_mask(pfb, 0x10f65c, 0x000000f0, save); 1351 nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); 1352 nv_wr32(pfb, 0x10ecc0, 0xffffffff); 1353 nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010); 1354 1355 return gk104_ram_train_init(pfb); 1356 } 1357 1358 static int 1359 gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) 1360 { 1361 struct nvkm_fb *pfb = (void *)nv_object(ram)->parent; 1362 struct nvkm_bios *bios = nvkm_bios(pfb); 1363 struct nvkm_ram_data *cfg; 1364 struct nvbios_ramcfg *d = &ram->diff; 1365 struct nvbios_ramcfg *p, *n; 1366 u8 ver, hdr, cnt, len; 1367 u32 data; 1368 int ret; 1369 1370 if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL))) 1371 return -ENOMEM; 1372 p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios; 1373 n = &cfg->bios; 1374 1375 /* memory config data for a range of target frequencies */ 1376 data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios); 1377 if (ret = -ENOENT, !data) 1378 goto done; 1379 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12) 1380 goto done; 1381 1382 /* ... and a portion specific to the attached memory */ 1383 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg, 1384 &ver, &hdr, &cfg->bios); 1385 if (ret = -EINVAL, !data) 1386 goto done; 1387 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a) 1388 goto done; 1389 1390 /* lookup memory timings, if bios says they're present */ 1391 if (cfg->bios.ramcfg_timing != 0xff) { 1392 data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing, 1393 &ver, &hdr, &cnt, &len, 1394 &cfg->bios); 1395 if (ret = -EINVAL, !data) 1396 goto done; 1397 if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33) 1398 goto done; 1399 } 1400 1401 list_add_tail(&cfg->head, &ram->cfg); 1402 if (ret = 0, i == 0) 1403 goto done; 1404 1405 d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe; 1406 d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff; 1407 d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400; 1408 d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800; 1409 d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0; 1410 d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200; 1411 d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d; 1412 d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f; 1413 d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e; 1414 d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800; 1415 d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400; 1416 d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01; 1417 d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02; 1418 d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10; 1419 d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03; 1420 d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20; 1421 d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07; 1422 done: 1423 if (ret) 1424 kfree(cfg); 1425 return ret; 1426 } 1427 1428 static void 1429 gk104_ram_dtor(struct nvkm_object *object) 1430 { 1431 struct gk104_ram *ram = (void *)object; 1432 struct nvkm_ram_data *cfg, *tmp; 1433 1434 list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { 1435 kfree(cfg); 1436 } 1437 1438 nvkm_ram_destroy(&ram->base); 1439 } 1440 1441 static int 1442 gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1443 struct nvkm_oclass *oclass, void *data, u32 size, 1444 struct nvkm_object **pobject) 1445 { 1446 struct nvkm_fb *pfb = nvkm_fb(parent); 1447 struct nvkm_bios *bios = nvkm_bios(pfb); 1448 struct nvkm_gpio *gpio = nvkm_gpio(pfb); 1449 struct dcb_gpio_func func; 1450 struct gk104_ram *ram; 1451 int ret, i; 1452 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); 1453 u32 tmp; 1454 1455 ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); 1456 *pobject = nv_object(ram); 1457 if (ret) 1458 return ret; 1459 1460 INIT_LIST_HEAD(&ram->cfg); 1461 1462 switch (ram->base.type) { 1463 case NV_MEM_TYPE_DDR3: 1464 case NV_MEM_TYPE_GDDR5: 1465 ram->base.calc = gk104_ram_calc; 1466 ram->base.prog = gk104_ram_prog; 1467 ram->base.tidy = gk104_ram_tidy; 1468 break; 1469 default: 1470 nv_warn(pfb, "reclocking of this RAM type is unsupported\n"); 1471 break; 1472 } 1473 1474 /* calculate a mask of differently configured memory partitions, 1475 * because, of course reclocking wasn't complicated enough 1476 * already without having to treat some of them differently to 1477 * the others.... 1478 */ 1479 ram->parts = nv_rd32(pfb, 0x022438); 1480 ram->pmask = nv_rd32(pfb, 0x022554); 1481 ram->pnuts = 0; 1482 for (i = 0, tmp = 0; i < ram->parts; i++) { 1483 if (!(ram->pmask & (1 << i))) { 1484 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); 1485 if (tmp && tmp != cfg1) { 1486 ram->pnuts |= (1 << i); 1487 continue; 1488 } 1489 tmp = cfg1; 1490 } 1491 } 1492 1493 /* parse bios data for all rammap table entries up-front, and 1494 * build information on whether certain fields differ between 1495 * any of the entries. 1496 * 1497 * the binary driver appears to completely ignore some fields 1498 * when all entries contain the same value. at first, it was 1499 * hoped that these were mere optimisations and the bios init 1500 * tables had configured as per the values here, but there is 1501 * evidence now to suggest that this isn't the case and we do 1502 * need to treat this condition as a "don't touch" indicator. 1503 */ 1504 for (i = 0; !ret; i++) { 1505 ret = gk104_ram_ctor_data(ram, ramcfg, i); 1506 if (ret && ret != -ENOENT) { 1507 nv_error(pfb, "failed to parse ramcfg data\n"); 1508 return ret; 1509 } 1510 } 1511 1512 /* parse bios data for both pll's */ 1513 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); 1514 if (ret) { 1515 nv_error(pfb, "mclk refpll data not found\n"); 1516 return ret; 1517 } 1518 1519 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll); 1520 if (ret) { 1521 nv_error(pfb, "mclk pll data not found\n"); 1522 return ret; 1523 } 1524 1525 /* lookup memory voltage gpios */ 1526 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func); 1527 if (ret == 0) { 1528 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04)); 1529 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12; 1530 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12; 1531 } 1532 1533 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); 1534 if (ret == 0) { 1535 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04)); 1536 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12; 1537 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12; 1538 } 1539 1540 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604); 1541 1542 ram->fuc.r_0x132020 = ramfuc_reg(0x132020); 1543 ram->fuc.r_0x132028 = ramfuc_reg(0x132028); 1544 ram->fuc.r_0x132024 = ramfuc_reg(0x132024); 1545 ram->fuc.r_0x132030 = ramfuc_reg(0x132030); 1546 ram->fuc.r_0x132034 = ramfuc_reg(0x132034); 1547 ram->fuc.r_0x132000 = ramfuc_reg(0x132000); 1548 ram->fuc.r_0x132004 = ramfuc_reg(0x132004); 1549 ram->fuc.r_0x132040 = ramfuc_reg(0x132040); 1550 1551 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248); 1552 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290); 1553 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294); 1554 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298); 1555 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c); 1556 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0); 1557 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4); 1558 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8); 1559 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac); 1560 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc); 1561 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8); 1562 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250); 1563 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c); 1564 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4); 1565 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8); 1566 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604); 1567 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614); 1568 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610); 1569 ram->fuc.r_0x100770 = ramfuc_reg(0x100770); 1570 ram->fuc.r_0x100778 = ramfuc_reg(0x100778); 1571 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224); 1572 1573 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870); 1574 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698); 1575 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694); 1576 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8); 1577 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808); 1578 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670); 1579 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c); 1580 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830); 1581 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec); 1582 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800); 1583 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c); 1584 1585 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978); 1586 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910); 1587 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); 1588 1589 switch (ram->base.type) { 1590 case NV_MEM_TYPE_GDDR5: 1591 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); 1592 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330); 1593 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334); 1594 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338); 1595 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c); 1596 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340); 1597 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344); 1598 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348); 1599 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354); 1600 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c); 1601 break; 1602 case NV_MEM_TYPE_DDR3: 1603 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); 1604 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); 1605 break; 1606 default: 1607 break; 1608 } 1609 1610 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000); 1611 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200); 1612 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210); 1613 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310); 1614 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314); 1615 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318); 1616 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090); 1617 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c); 1618 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824); 1619 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0); 1620 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4); 1621 ram->fuc.r_0x137320 = ramfuc_reg(0x137320); 1622 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); 1623 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); 1624 ram->fuc.r_0x100710 = ramfuc_reg(0x100710); 1625 ram->fuc.r_0x100750 = ramfuc_reg(0x100750); 1626 return 0; 1627 } 1628 1629 struct nvkm_oclass 1630 gk104_ram_oclass = { 1631 .handle = 0, 1632 .ofuncs = &(struct nvkm_ofuncs) { 1633 .ctor = gk104_ram_ctor, 1634 .dtor = gk104_ram_dtor, 1635 .init = gk104_ram_init, 1636 .fini = _nvkm_ram_fini, 1637 } 1638 }; 1639