1639c308eSBen Skeggs /* 2639c308eSBen Skeggs * Copyright 2013 Red Hat Inc. 3639c308eSBen Skeggs * 4639c308eSBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining a 5639c308eSBen Skeggs * copy of this software and associated documentation files (the "Software"), 6639c308eSBen Skeggs * to deal in the Software without restriction, including without limitation 7639c308eSBen Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8639c308eSBen Skeggs * and/or sell copies of the Software, and to permit persons to whom the 9639c308eSBen Skeggs * Software is furnished to do so, subject to the following conditions: 10639c308eSBen Skeggs * 11639c308eSBen Skeggs * The above copyright notice and this permission notice shall be included in 12639c308eSBen Skeggs * all copies or substantial portions of the Software. 13639c308eSBen Skeggs * 14639c308eSBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15639c308eSBen Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16639c308eSBen Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17639c308eSBen Skeggs * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18639c308eSBen Skeggs * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19639c308eSBen Skeggs * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20639c308eSBen Skeggs * OTHER DEALINGS IN THE SOFTWARE. 21639c308eSBen Skeggs * 22639c308eSBen Skeggs * Authors: Ben Skeggs 23639c308eSBen Skeggs */ 24d36a99d2SBen Skeggs #define gk104_ram(p) container_of((p), struct gk104_ram, base) 25d36a99d2SBen Skeggs #include "ram.h" 26639c308eSBen Skeggs #include "ramfuc.h" 27639c308eSBen Skeggs 28639c308eSBen Skeggs #include <core/option.h> 29639c308eSBen Skeggs #include <subdev/bios.h> 30639c308eSBen Skeggs #include <subdev/bios/init.h> 31639c308eSBen Skeggs #include <subdev/bios/M0205.h> 32639c308eSBen Skeggs #include <subdev/bios/M0209.h> 33639c308eSBen Skeggs #include <subdev/bios/pll.h> 34639c308eSBen Skeggs #include <subdev/bios/rammap.h> 35639c308eSBen Skeggs #include <subdev/bios/timing.h> 36639c308eSBen Skeggs #include <subdev/clk.h> 37639c308eSBen Skeggs #include <subdev/clk/pll.h> 38639c308eSBen Skeggs #include <subdev/gpio.h> 39639c308eSBen Skeggs 40639c308eSBen Skeggs struct gk104_ramfuc { 41639c308eSBen Skeggs struct ramfuc base; 42639c308eSBen Skeggs 43639c308eSBen Skeggs struct nvbios_pll refpll; 44639c308eSBen Skeggs struct nvbios_pll mempll; 45639c308eSBen Skeggs 46639c308eSBen Skeggs struct ramfuc_reg r_gpioMV; 47639c308eSBen Skeggs u32 r_funcMV[2]; 48639c308eSBen Skeggs struct ramfuc_reg r_gpio2E; 49639c308eSBen Skeggs u32 r_func2E[2]; 50639c308eSBen Skeggs struct ramfuc_reg r_gpiotrig; 51639c308eSBen Skeggs 52639c308eSBen Skeggs struct ramfuc_reg r_0x132020; 53639c308eSBen Skeggs struct ramfuc_reg r_0x132028; 54639c308eSBen Skeggs struct ramfuc_reg r_0x132024; 55639c308eSBen Skeggs struct ramfuc_reg r_0x132030; 56639c308eSBen Skeggs struct ramfuc_reg r_0x132034; 57639c308eSBen Skeggs struct ramfuc_reg r_0x132000; 58639c308eSBen Skeggs struct ramfuc_reg r_0x132004; 59639c308eSBen Skeggs struct ramfuc_reg r_0x132040; 60639c308eSBen Skeggs 61639c308eSBen Skeggs struct ramfuc_reg r_0x10f248; 62639c308eSBen Skeggs struct ramfuc_reg r_0x10f290; 63639c308eSBen Skeggs struct ramfuc_reg r_0x10f294; 64639c308eSBen Skeggs struct ramfuc_reg r_0x10f298; 65639c308eSBen Skeggs struct ramfuc_reg r_0x10f29c; 66639c308eSBen Skeggs struct ramfuc_reg r_0x10f2a0; 67639c308eSBen Skeggs struct ramfuc_reg r_0x10f2a4; 68639c308eSBen Skeggs struct ramfuc_reg r_0x10f2a8; 69639c308eSBen Skeggs struct ramfuc_reg r_0x10f2ac; 70639c308eSBen Skeggs struct ramfuc_reg r_0x10f2cc; 71639c308eSBen Skeggs struct ramfuc_reg r_0x10f2e8; 72639c308eSBen Skeggs struct ramfuc_reg r_0x10f250; 73639c308eSBen Skeggs struct ramfuc_reg r_0x10f24c; 74639c308eSBen Skeggs struct ramfuc_reg r_0x10fec4; 75639c308eSBen Skeggs struct ramfuc_reg r_0x10fec8; 76639c308eSBen Skeggs struct ramfuc_reg r_0x10f604; 77639c308eSBen Skeggs struct ramfuc_reg r_0x10f614; 78639c308eSBen Skeggs struct ramfuc_reg r_0x10f610; 79639c308eSBen Skeggs struct ramfuc_reg r_0x100770; 80639c308eSBen Skeggs struct ramfuc_reg r_0x100778; 81639c308eSBen Skeggs struct ramfuc_reg r_0x10f224; 82639c308eSBen Skeggs 83639c308eSBen Skeggs struct ramfuc_reg r_0x10f870; 84639c308eSBen Skeggs struct ramfuc_reg r_0x10f698; 85639c308eSBen Skeggs struct ramfuc_reg r_0x10f694; 86639c308eSBen Skeggs struct ramfuc_reg r_0x10f6b8; 87639c308eSBen Skeggs struct ramfuc_reg r_0x10f808; 88639c308eSBen Skeggs struct ramfuc_reg r_0x10f670; 89639c308eSBen Skeggs struct ramfuc_reg r_0x10f60c; 90639c308eSBen Skeggs struct ramfuc_reg r_0x10f830; 91639c308eSBen Skeggs struct ramfuc_reg r_0x1373ec; 92639c308eSBen Skeggs struct ramfuc_reg r_0x10f800; 93639c308eSBen Skeggs struct ramfuc_reg r_0x10f82c; 94639c308eSBen Skeggs 95639c308eSBen Skeggs struct ramfuc_reg r_0x10f978; 96639c308eSBen Skeggs struct ramfuc_reg r_0x10f910; 97639c308eSBen Skeggs struct ramfuc_reg r_0x10f914; 98639c308eSBen Skeggs 99639c308eSBen Skeggs struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ 100639c308eSBen Skeggs 101639c308eSBen Skeggs struct ramfuc_reg r_0x62c000; 102639c308eSBen Skeggs 103639c308eSBen Skeggs struct ramfuc_reg r_0x10f200; 104639c308eSBen Skeggs 105639c308eSBen Skeggs struct ramfuc_reg r_0x10f210; 106639c308eSBen Skeggs struct ramfuc_reg r_0x10f310; 107639c308eSBen Skeggs struct ramfuc_reg r_0x10f314; 108639c308eSBen Skeggs struct ramfuc_reg r_0x10f318; 109639c308eSBen Skeggs struct ramfuc_reg r_0x10f090; 110639c308eSBen Skeggs struct ramfuc_reg r_0x10f69c; 111639c308eSBen Skeggs struct ramfuc_reg r_0x10f824; 112639c308eSBen Skeggs struct ramfuc_reg r_0x1373f0; 113639c308eSBen Skeggs struct ramfuc_reg r_0x1373f4; 114639c308eSBen Skeggs struct ramfuc_reg r_0x137320; 115639c308eSBen Skeggs struct ramfuc_reg r_0x10f65c; 116639c308eSBen Skeggs struct ramfuc_reg r_0x10f6bc; 117639c308eSBen Skeggs struct ramfuc_reg r_0x100710; 118639c308eSBen Skeggs struct ramfuc_reg r_0x100750; 119639c308eSBen Skeggs }; 120639c308eSBen Skeggs 121639c308eSBen Skeggs struct gk104_ram { 122639c308eSBen Skeggs struct nvkm_ram base; 123639c308eSBen Skeggs struct gk104_ramfuc fuc; 124639c308eSBen Skeggs 125639c308eSBen Skeggs struct list_head cfg; 126639c308eSBen Skeggs u32 parts; 127639c308eSBen Skeggs u32 pmask; 128639c308eSBen Skeggs u32 pnuts; 129639c308eSBen Skeggs 130639c308eSBen Skeggs struct nvbios_ramcfg diff; 131639c308eSBen Skeggs int from; 132639c308eSBen Skeggs int mode; 133639c308eSBen Skeggs int N1, fN1, M1, P1; 134639c308eSBen Skeggs int N2, M2, P2; 135639c308eSBen Skeggs }; 136639c308eSBen Skeggs 137639c308eSBen Skeggs /******************************************************************************* 138639c308eSBen Skeggs * GDDR5 139639c308eSBen Skeggs ******************************************************************************/ 140639c308eSBen Skeggs static void 141639c308eSBen Skeggs gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data) 142639c308eSBen Skeggs { 143639c308eSBen Skeggs struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 144639c308eSBen Skeggs u32 addr = 0x110974, i; 145639c308eSBen Skeggs 146639c308eSBen Skeggs ram_mask(fuc, 0x10f910, mask, data); 147639c308eSBen Skeggs ram_mask(fuc, 0x10f914, mask, data); 148639c308eSBen Skeggs 149639c308eSBen Skeggs for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { 150639c308eSBen Skeggs if (ram->pmask & (1 << i)) 151639c308eSBen Skeggs continue; 152639c308eSBen Skeggs ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); 153639c308eSBen Skeggs } 154639c308eSBen Skeggs } 155639c308eSBen Skeggs 156639c308eSBen Skeggs static void 157639c308eSBen Skeggs r1373f4_init(struct gk104_ramfuc *fuc) 158639c308eSBen Skeggs { 159639c308eSBen Skeggs struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 160639c308eSBen Skeggs const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); 161639c308eSBen Skeggs const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 162639c308eSBen Skeggs const u32 runk0 = ram->fN1 << 16; 163639c308eSBen Skeggs const u32 runk1 = ram->fN1; 164639c308eSBen Skeggs 165639c308eSBen Skeggs if (ram->from == 2) { 166639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); 167639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); 168639c308eSBen Skeggs } else { 169639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 170639c308eSBen Skeggs } 171639c308eSBen Skeggs 172639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 173639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 174639c308eSBen Skeggs 175639c308eSBen Skeggs /* (re)program refpll, if required */ 176639c308eSBen Skeggs if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || 177639c308eSBen Skeggs (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { 178639c308eSBen Skeggs ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 179639c308eSBen Skeggs ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); 180639c308eSBen Skeggs ram_wr32(fuc, 0x137320, 0x00000000); 181639c308eSBen Skeggs ram_mask(fuc, 0x132030, 0xffff0000, runk0); 182639c308eSBen Skeggs ram_mask(fuc, 0x132034, 0x0000ffff, runk1); 183639c308eSBen Skeggs ram_wr32(fuc, 0x132024, rcoef); 184639c308eSBen Skeggs ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); 185639c308eSBen Skeggs ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); 186639c308eSBen Skeggs ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); 187639c308eSBen Skeggs ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); 188639c308eSBen Skeggs } 189639c308eSBen Skeggs 190639c308eSBen Skeggs /* (re)program mempll, if required */ 191639c308eSBen Skeggs if (ram->mode == 2) { 192639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 193639c308eSBen Skeggs ram_mask(fuc, 0x132000, 0x80000000, 0x80000000); 194639c308eSBen Skeggs ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 195639c308eSBen Skeggs ram_mask(fuc, 0x132004, 0x103fffff, mcoef); 196639c308eSBen Skeggs ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); 197639c308eSBen Skeggs ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000); 198639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); 199639c308eSBen Skeggs } else { 200639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100); 201639c308eSBen Skeggs } 202639c308eSBen Skeggs 203639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); 204639c308eSBen Skeggs } 205639c308eSBen Skeggs 206639c308eSBen Skeggs static void 207639c308eSBen Skeggs r1373f4_fini(struct gk104_ramfuc *fuc) 208639c308eSBen Skeggs { 209639c308eSBen Skeggs struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); 210639c308eSBen Skeggs struct nvkm_ram_data *next = ram->base.next; 211639c308eSBen Skeggs u8 v0 = next->bios.ramcfg_11_03_c0; 212639c308eSBen Skeggs u8 v1 = next->bios.ramcfg_11_03_30; 213639c308eSBen Skeggs u32 tmp; 214639c308eSBen Skeggs 215639c308eSBen Skeggs tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 216639c308eSBen Skeggs ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16)); 217639c308eSBen Skeggs ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000); 218639c308eSBen Skeggs if (ram->mode == 2) { 219cfb4f929SIlia Mirkin ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002); 220cfb4f929SIlia Mirkin ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000); 221639c308eSBen Skeggs } else { 222cfb4f929SIlia Mirkin ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); 223cfb4f929SIlia Mirkin ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 224639c308eSBen Skeggs } 225639c308eSBen Skeggs ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); 226639c308eSBen Skeggs } 227639c308eSBen Skeggs 228639c308eSBen Skeggs static void 229639c308eSBen Skeggs gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, 230639c308eSBen Skeggs u32 _mask, u32 _data, u32 _copy) 231639c308eSBen Skeggs { 232d36a99d2SBen Skeggs struct nvkm_fb *fb = ram->base.fb; 233639c308eSBen Skeggs struct ramfuc *fuc = &ram->fuc.base; 2346758745bSBen Skeggs struct nvkm_device *device = fb->subdev.device; 235639c308eSBen Skeggs u32 addr = 0x110000 + (reg->addr & 0xfff); 236639c308eSBen Skeggs u32 mask = _mask | _copy; 237639c308eSBen Skeggs u32 data = (_data & _mask) | (reg->data & _copy); 238639c308eSBen Skeggs u32 i; 239639c308eSBen Skeggs 240639c308eSBen Skeggs for (i = 0; i < 16; i++, addr += 0x1000) { 241639c308eSBen Skeggs if (ram->pnuts & (1 << i)) { 2426758745bSBen Skeggs u32 prev = nvkm_rd32(device, addr); 243639c308eSBen Skeggs u32 next = (prev & ~mask) | data; 244639c308eSBen Skeggs nvkm_memx_wr32(fuc->memx, addr, next); 245639c308eSBen Skeggs } 246639c308eSBen Skeggs } 247639c308eSBen Skeggs } 248639c308eSBen Skeggs #define ram_nuts(s,r,m,d,c) \ 249639c308eSBen Skeggs gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) 250639c308eSBen Skeggs 251639c308eSBen Skeggs static int 252d36a99d2SBen Skeggs gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) 253639c308eSBen Skeggs { 254639c308eSBen Skeggs struct gk104_ramfuc *fuc = &ram->fuc; 255639c308eSBen Skeggs struct nvkm_ram_data *next = ram->base.next; 256639c308eSBen Skeggs int vc = !next->bios.ramcfg_11_02_08; 257639c308eSBen Skeggs int mv = !next->bios.ramcfg_11_02_04; 258639c308eSBen Skeggs u32 mask, data; 259639c308eSBen Skeggs 260639c308eSBen Skeggs ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 261639c308eSBen Skeggs ram_block(fuc); 262380b1cadSKarol Herbst 263380b1cadSKarol Herbst if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 264639c308eSBen Skeggs ram_wr32(fuc, 0x62c000, 0x0f0f0000); 265639c308eSBen Skeggs 266639c308eSBen Skeggs /* MR1: turn termination on early, for some reason.. */ 267639c308eSBen Skeggs if ((ram->base.mr[1] & 0x03c) != 0x030) { 268639c308eSBen Skeggs ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); 269639c308eSBen Skeggs ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); 270639c308eSBen Skeggs } 271639c308eSBen Skeggs 272639c308eSBen Skeggs if (vc == 1 && ram_have(fuc, gpio2E)) { 273639c308eSBen Skeggs u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); 274639c308eSBen Skeggs if (temp != ram_rd32(fuc, gpio2E)) { 275639c308eSBen Skeggs ram_wr32(fuc, gpiotrig, 1); 276639c308eSBen Skeggs ram_nsec(fuc, 20000); 277639c308eSBen Skeggs } 278639c308eSBen Skeggs } 279639c308eSBen Skeggs 280639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 281639c308eSBen Skeggs 282639c308eSBen Skeggs gk104_ram_train(fuc, 0x01020000, 0x000c0000); 283639c308eSBen Skeggs 284639c308eSBen Skeggs ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ 285639c308eSBen Skeggs ram_nsec(fuc, 1000); 286639c308eSBen Skeggs ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 287639c308eSBen Skeggs ram_nsec(fuc, 1000); 288639c308eSBen Skeggs 289639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 290639c308eSBen Skeggs ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 291639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 292639c308eSBen Skeggs ram_wr32(fuc, 0x10f090, 0x00000061); 293639c308eSBen Skeggs ram_wr32(fuc, 0x10f090, 0xc000007f); 294639c308eSBen Skeggs ram_nsec(fuc, 1000); 295639c308eSBen Skeggs 296639c308eSBen Skeggs ram_wr32(fuc, 0x10f698, 0x00000000); 297639c308eSBen Skeggs ram_wr32(fuc, 0x10f69c, 0x00000000); 298639c308eSBen Skeggs 299639c308eSBen Skeggs /*XXX: there does appear to be some kind of condition here, simply 300639c308eSBen Skeggs * modifying these bits in the vbios from the default pl0 301639c308eSBen Skeggs * entries shows no change. however, the data does appear to 302639c308eSBen Skeggs * be correct and may be required for the transition back 303639c308eSBen Skeggs */ 304639c308eSBen Skeggs mask = 0x800f07e0; 305639c308eSBen Skeggs data = 0x00030000; 306639c308eSBen Skeggs if (ram_rd32(fuc, 0x10f978) & 0x00800000) 307639c308eSBen Skeggs data |= 0x00040000; 308639c308eSBen Skeggs 309639c308eSBen Skeggs if (1) { 310639c308eSBen Skeggs data |= 0x800807e0; 311639c308eSBen Skeggs switch (next->bios.ramcfg_11_03_c0) { 312639c308eSBen Skeggs case 3: data &= ~0x00000040; break; 313639c308eSBen Skeggs case 2: data &= ~0x00000100; break; 314639c308eSBen Skeggs case 1: data &= ~0x80000000; break; 315639c308eSBen Skeggs case 0: data &= ~0x00000400; break; 316639c308eSBen Skeggs } 317639c308eSBen Skeggs 318639c308eSBen Skeggs switch (next->bios.ramcfg_11_03_30) { 319639c308eSBen Skeggs case 3: data &= ~0x00000020; break; 320639c308eSBen Skeggs case 2: data &= ~0x00000080; break; 321639c308eSBen Skeggs case 1: data &= ~0x00080000; break; 322639c308eSBen Skeggs case 0: data &= ~0x00000200; break; 323639c308eSBen Skeggs } 324639c308eSBen Skeggs } 325639c308eSBen Skeggs 326639c308eSBen Skeggs if (next->bios.ramcfg_11_02_80) 327639c308eSBen Skeggs mask |= 0x03000000; 328639c308eSBen Skeggs if (next->bios.ramcfg_11_02_40) 329639c308eSBen Skeggs mask |= 0x00002000; 330639c308eSBen Skeggs if (next->bios.ramcfg_11_07_10) 331639c308eSBen Skeggs mask |= 0x00004000; 332639c308eSBen Skeggs if (next->bios.ramcfg_11_07_08) 333639c308eSBen Skeggs mask |= 0x00000003; 334639c308eSBen Skeggs else { 335639c308eSBen Skeggs mask |= 0x34000000; 336639c308eSBen Skeggs if (ram_rd32(fuc, 0x10f978) & 0x00800000) 337639c308eSBen Skeggs mask |= 0x40000000; 338639c308eSBen Skeggs } 339639c308eSBen Skeggs ram_mask(fuc, 0x10f824, mask, data); 340639c308eSBen Skeggs 341639c308eSBen Skeggs ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); 342639c308eSBen Skeggs 343639c308eSBen Skeggs if (ram->from == 2 && ram->mode != 2) { 344639c308eSBen Skeggs ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); 345639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); 346639c308eSBen Skeggs ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); 347639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); 348639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 349639c308eSBen Skeggs r1373f4_init(fuc); 350639c308eSBen Skeggs ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); 351639c308eSBen Skeggs r1373f4_fini(fuc); 352639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); 353639c308eSBen Skeggs } else 354639c308eSBen Skeggs if (ram->from != 2 && ram->mode != 2) { 355639c308eSBen Skeggs r1373f4_init(fuc); 356639c308eSBen Skeggs r1373f4_fini(fuc); 357639c308eSBen Skeggs } 358639c308eSBen Skeggs 359639c308eSBen Skeggs if (ram_have(fuc, gpioMV)) { 360639c308eSBen Skeggs u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); 361639c308eSBen Skeggs if (temp != ram_rd32(fuc, gpioMV)) { 362639c308eSBen Skeggs ram_wr32(fuc, gpiotrig, 1); 363639c308eSBen Skeggs ram_nsec(fuc, 64000); 364639c308eSBen Skeggs } 365639c308eSBen Skeggs } 366639c308eSBen Skeggs 367639c308eSBen Skeggs if (next->bios.ramcfg_11_02_40 || 368639c308eSBen Skeggs next->bios.ramcfg_11_07_10) { 369639c308eSBen Skeggs ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 370639c308eSBen Skeggs ram_nsec(fuc, 20000); 371639c308eSBen Skeggs } 372639c308eSBen Skeggs 373639c308eSBen Skeggs if (ram->from != 2 && ram->mode == 2) { 374639c308eSBen Skeggs if (0 /*XXX: Titan */) 375639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); 376639c308eSBen Skeggs ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 377639c308eSBen Skeggs ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); 378639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); 379639c308eSBen Skeggs r1373f4_init(fuc); 380639c308eSBen Skeggs r1373f4_fini(fuc); 381639c308eSBen Skeggs ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); 382639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); 383639c308eSBen Skeggs } else 384639c308eSBen Skeggs if (ram->from == 2 && ram->mode == 2) { 385639c308eSBen Skeggs ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 386639c308eSBen Skeggs r1373f4_init(fuc); 387639c308eSBen Skeggs r1373f4_fini(fuc); 388639c308eSBen Skeggs } 389639c308eSBen Skeggs 390639c308eSBen Skeggs if (ram->mode != 2) /*XXX*/ { 391639c308eSBen Skeggs if (next->bios.ramcfg_11_07_40) 392639c308eSBen Skeggs ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 393639c308eSBen Skeggs } 394639c308eSBen Skeggs 395639c308eSBen Skeggs ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); 396639c308eSBen Skeggs ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); 397639c308eSBen Skeggs ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); 398639c308eSBen Skeggs 399639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { 400639c308eSBen Skeggs ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); 401639c308eSBen Skeggs ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); 402639c308eSBen Skeggs } else 403639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_08) { 404639c308eSBen Skeggs ram_wr32(fuc, 0x10f698, 0x00000000); 405639c308eSBen Skeggs ram_wr32(fuc, 0x10f69c, 0x00000000); 406639c308eSBen Skeggs } 407639c308eSBen Skeggs 408639c308eSBen Skeggs if (ram->mode != 2) { 409639c308eSBen Skeggs u32 data = 0x01000100 * next->bios.ramcfg_11_04; 410639c308eSBen Skeggs ram_nuke(fuc, 0x10f694); 411639c308eSBen Skeggs ram_mask(fuc, 0x10f694, 0xff00ff00, data); 412639c308eSBen Skeggs } 413639c308eSBen Skeggs 414639c308eSBen Skeggs if (ram->mode == 2 && next->bios.ramcfg_11_08_10) 415639c308eSBen Skeggs data = 0x00000080; 416639c308eSBen Skeggs else 417639c308eSBen Skeggs data = 0x00000000; 418639c308eSBen Skeggs ram_mask(fuc, 0x10f60c, 0x00000080, data); 419639c308eSBen Skeggs 420639c308eSBen Skeggs mask = 0x00070000; 421639c308eSBen Skeggs data = 0x00000000; 422639c308eSBen Skeggs if (!next->bios.ramcfg_11_02_80) 423639c308eSBen Skeggs data |= 0x03000000; 424639c308eSBen Skeggs if (!next->bios.ramcfg_11_02_40) 425639c308eSBen Skeggs data |= 0x00002000; 426639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_10) 427639c308eSBen Skeggs data |= 0x00004000; 428639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_08) 429639c308eSBen Skeggs data |= 0x00000003; 430639c308eSBen Skeggs else 431639c308eSBen Skeggs data |= 0x74000000; 432639c308eSBen Skeggs ram_mask(fuc, 0x10f824, mask, data); 433639c308eSBen Skeggs 434639c308eSBen Skeggs if (next->bios.ramcfg_11_01_08) 435639c308eSBen Skeggs data = 0x00000000; 436639c308eSBen Skeggs else 437639c308eSBen Skeggs data = 0x00001000; 438639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x00001000, data); 439639c308eSBen Skeggs 440639c308eSBen Skeggs if (ram_rd32(fuc, 0x10f670) & 0x80000000) { 441639c308eSBen Skeggs ram_nsec(fuc, 10000); 442639c308eSBen Skeggs ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); 443639c308eSBen Skeggs } 444639c308eSBen Skeggs 445639c308eSBen Skeggs if (next->bios.ramcfg_11_08_01) 446639c308eSBen Skeggs data = 0x00100000; 447639c308eSBen Skeggs else 448639c308eSBen Skeggs data = 0x00000000; 449639c308eSBen Skeggs ram_mask(fuc, 0x10f82c, 0x00100000, data); 450639c308eSBen Skeggs 451639c308eSBen Skeggs data = 0x00000000; 452639c308eSBen Skeggs if (next->bios.ramcfg_11_08_08) 453639c308eSBen Skeggs data |= 0x00002000; 454639c308eSBen Skeggs if (next->bios.ramcfg_11_08_04) 455639c308eSBen Skeggs data |= 0x00001000; 456639c308eSBen Skeggs if (next->bios.ramcfg_11_08_02) 457639c308eSBen Skeggs data |= 0x00004000; 458639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x00007000, data); 459639c308eSBen Skeggs 460639c308eSBen Skeggs /* PFB timing */ 461639c308eSBen Skeggs ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); 462639c308eSBen Skeggs ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); 463639c308eSBen Skeggs ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); 464639c308eSBen Skeggs ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); 465639c308eSBen Skeggs ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); 466639c308eSBen Skeggs ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); 467639c308eSBen Skeggs ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); 468639c308eSBen Skeggs ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); 469639c308eSBen Skeggs ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); 470639c308eSBen Skeggs ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); 471639c308eSBen Skeggs ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); 472639c308eSBen Skeggs 473639c308eSBen Skeggs data = mask = 0x00000000; 474639c308eSBen Skeggs if (ram->diff.ramcfg_11_08_20) { 475639c308eSBen Skeggs if (next->bios.ramcfg_11_08_20) 476639c308eSBen Skeggs data |= 0x01000000; 477639c308eSBen Skeggs mask |= 0x01000000; 478639c308eSBen Skeggs } 479639c308eSBen Skeggs ram_mask(fuc, 0x10f200, mask, data); 480639c308eSBen Skeggs 481639c308eSBen Skeggs data = mask = 0x00000000; 482639c308eSBen Skeggs if (ram->diff.ramcfg_11_02_03) { 483639c308eSBen Skeggs data |= next->bios.ramcfg_11_02_03 << 8; 484639c308eSBen Skeggs mask |= 0x00000300; 485639c308eSBen Skeggs } 486639c308eSBen Skeggs if (ram->diff.ramcfg_11_01_10) { 487639c308eSBen Skeggs if (next->bios.ramcfg_11_01_10) 488639c308eSBen Skeggs data |= 0x70000000; 489639c308eSBen Skeggs mask |= 0x70000000; 490639c308eSBen Skeggs } 491639c308eSBen Skeggs ram_mask(fuc, 0x10f604, mask, data); 492639c308eSBen Skeggs 493639c308eSBen Skeggs data = mask = 0x00000000; 494639c308eSBen Skeggs if (ram->diff.timing_20_30_07) { 495639c308eSBen Skeggs data |= next->bios.timing_20_30_07 << 28; 496639c308eSBen Skeggs mask |= 0x70000000; 497639c308eSBen Skeggs } 498639c308eSBen Skeggs if (ram->diff.ramcfg_11_01_01) { 499639c308eSBen Skeggs if (next->bios.ramcfg_11_01_01) 500639c308eSBen Skeggs data |= 0x00000100; 501639c308eSBen Skeggs mask |= 0x00000100; 502639c308eSBen Skeggs } 503639c308eSBen Skeggs ram_mask(fuc, 0x10f614, mask, data); 504639c308eSBen Skeggs 505639c308eSBen Skeggs data = mask = 0x00000000; 506639c308eSBen Skeggs if (ram->diff.timing_20_30_07) { 507639c308eSBen Skeggs data |= next->bios.timing_20_30_07 << 28; 508639c308eSBen Skeggs mask |= 0x70000000; 509639c308eSBen Skeggs } 510639c308eSBen Skeggs if (ram->diff.ramcfg_11_01_02) { 511639c308eSBen Skeggs if (next->bios.ramcfg_11_01_02) 512639c308eSBen Skeggs data |= 0x00000100; 513639c308eSBen Skeggs mask |= 0x00000100; 514639c308eSBen Skeggs } 515639c308eSBen Skeggs ram_mask(fuc, 0x10f610, mask, data); 516639c308eSBen Skeggs 517639c308eSBen Skeggs mask = 0x33f00000; 518639c308eSBen Skeggs data = 0x00000000; 519639c308eSBen Skeggs if (!next->bios.ramcfg_11_01_04) 520639c308eSBen Skeggs data |= 0x20200000; 521639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_80) 522639c308eSBen Skeggs data |= 0x12800000; 523639c308eSBen Skeggs /*XXX: see note above about there probably being some condition 524639c308eSBen Skeggs * for the 10f824 stuff that uses ramcfg 3... 525639c308eSBen Skeggs */ 526639c308eSBen Skeggs if (next->bios.ramcfg_11_03_f0) { 527639c308eSBen Skeggs if (next->bios.rammap_11_08_0c) { 528639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_80) 529639c308eSBen Skeggs mask |= 0x00000020; 530639c308eSBen Skeggs else 531639c308eSBen Skeggs data |= 0x00000020; 532639c308eSBen Skeggs mask |= 0x00000004; 533639c308eSBen Skeggs } 534639c308eSBen Skeggs } else { 535639c308eSBen Skeggs mask |= 0x40000020; 536639c308eSBen Skeggs data |= 0x00000004; 537639c308eSBen Skeggs } 538639c308eSBen Skeggs 539639c308eSBen Skeggs ram_mask(fuc, 0x10f808, mask, data); 540639c308eSBen Skeggs 541639c308eSBen Skeggs ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); 542639c308eSBen Skeggs 543639c308eSBen Skeggs data = mask = 0x00000000; 544639c308eSBen Skeggs if (ram->diff.ramcfg_11_02_03) { 545639c308eSBen Skeggs data |= next->bios.ramcfg_11_02_03; 546639c308eSBen Skeggs mask |= 0x00000003; 547639c308eSBen Skeggs } 548639c308eSBen Skeggs if (ram->diff.ramcfg_11_01_10) { 549639c308eSBen Skeggs if (next->bios.ramcfg_11_01_10) 550639c308eSBen Skeggs data |= 0x00000004; 551639c308eSBen Skeggs mask |= 0x00000004; 552639c308eSBen Skeggs } 553639c308eSBen Skeggs 554639c308eSBen Skeggs if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { 555639c308eSBen Skeggs ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); 556639c308eSBen Skeggs ram_wr32(fuc, 0x100710, 0x00000000); 557639c308eSBen Skeggs ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 558639c308eSBen Skeggs } 559639c308eSBen Skeggs 560639c308eSBen Skeggs data = next->bios.timing_20_30_07 << 8; 561639c308eSBen Skeggs if (next->bios.ramcfg_11_01_01) 562639c308eSBen Skeggs data |= 0x80000000; 563639c308eSBen Skeggs ram_mask(fuc, 0x100778, 0x00000700, data); 564639c308eSBen Skeggs 565639c308eSBen Skeggs ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); 566639c308eSBen Skeggs data = (next->bios.timing[10] & 0x7f000000) >> 24; 567639c308eSBen Skeggs if (data < next->bios.timing_20_2c_1fc0) 568639c308eSBen Skeggs data = next->bios.timing_20_2c_1fc0; 569639c308eSBen Skeggs ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 570639c308eSBen Skeggs ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 571639c308eSBen Skeggs 572639c308eSBen Skeggs ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | 573639c308eSBen Skeggs next->bios.timing_20_31_0780 << 17 | 574639c308eSBen Skeggs next->bios.timing_20_31_0078 << 8 | 575639c308eSBen Skeggs next->bios.timing_20_31_0007); 576639c308eSBen Skeggs ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | 577639c308eSBen Skeggs next->bios.timing_20_31_7000); 578639c308eSBen Skeggs 579639c308eSBen Skeggs ram_wr32(fuc, 0x10f090, 0x4000007e); 580639c308eSBen Skeggs ram_nsec(fuc, 2000); 581639c308eSBen Skeggs ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 582639c308eSBen Skeggs ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 583639c308eSBen Skeggs ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 584639c308eSBen Skeggs 585639c308eSBen Skeggs if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { 586639c308eSBen Skeggs u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 587639c308eSBen Skeggs gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ 588639c308eSBen Skeggs ram_nsec(fuc, 1000); 589639c308eSBen Skeggs ram_wr32(fuc, 0x10f294, temp); 590639c308eSBen Skeggs } 591639c308eSBen Skeggs 592639c308eSBen Skeggs ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]); 593639c308eSBen Skeggs ram_wr32(fuc, mr[0], ram->base.mr[0]); 594639c308eSBen Skeggs ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); 595639c308eSBen Skeggs ram_nsec(fuc, 1000); 596639c308eSBen Skeggs ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); 597639c308eSBen Skeggs ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ 598639c308eSBen Skeggs ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); 599639c308eSBen Skeggs ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); 600639c308eSBen Skeggs 601639c308eSBen Skeggs if (vc == 0 && ram_have(fuc, gpio2E)) { 602639c308eSBen Skeggs u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); 603639c308eSBen Skeggs if (temp != ram_rd32(fuc, gpio2E)) { 604639c308eSBen Skeggs ram_wr32(fuc, gpiotrig, 1); 605639c308eSBen Skeggs ram_nsec(fuc, 20000); 606639c308eSBen Skeggs } 607639c308eSBen Skeggs } 608639c308eSBen Skeggs 609639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 610639c308eSBen Skeggs ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 611639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 612639c308eSBen Skeggs ram_nsec(fuc, 1000); 613639c308eSBen Skeggs ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); 614639c308eSBen Skeggs 615639c308eSBen Skeggs data = ram_rd32(fuc, 0x10f978); 616639c308eSBen Skeggs data &= ~0x00046144; 617639c308eSBen Skeggs data |= 0x0000000b; 618639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_08) { 619639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_04) 620639c308eSBen Skeggs data |= 0x0000200c; 621639c308eSBen Skeggs else 622639c308eSBen Skeggs data |= 0x00000000; 623639c308eSBen Skeggs } else { 624639c308eSBen Skeggs data |= 0x00040044; 625639c308eSBen Skeggs } 626639c308eSBen Skeggs ram_wr32(fuc, 0x10f978, data); 627639c308eSBen Skeggs 628639c308eSBen Skeggs if (ram->mode == 1) { 629639c308eSBen Skeggs data = ram_rd32(fuc, 0x10f830) | 0x00000001; 630639c308eSBen Skeggs ram_wr32(fuc, 0x10f830, data); 631639c308eSBen Skeggs } 632639c308eSBen Skeggs 633639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_08) { 634639c308eSBen Skeggs data = 0x88020000; 635639c308eSBen Skeggs if ( next->bios.ramcfg_11_07_04) 636639c308eSBen Skeggs data |= 0x10000000; 637639c308eSBen Skeggs if (!next->bios.rammap_11_08_10) 638639c308eSBen Skeggs data |= 0x00080000; 639639c308eSBen Skeggs } else { 640639c308eSBen Skeggs data = 0xa40e0000; 641639c308eSBen Skeggs } 642639c308eSBen Skeggs gk104_ram_train(fuc, 0xbc0f0000, data); 643639c308eSBen Skeggs if (1) /* XXX: not always? */ 644639c308eSBen Skeggs ram_nsec(fuc, 1000); 645639c308eSBen Skeggs 646639c308eSBen Skeggs if (ram->mode == 2) { /*XXX*/ 647639c308eSBen Skeggs ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); 648639c308eSBen Skeggs } 649639c308eSBen Skeggs 650639c308eSBen Skeggs /* LP3 */ 651639c308eSBen Skeggs if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) 652639c308eSBen Skeggs ram_nsec(fuc, 1000); 653639c308eSBen Skeggs 654639c308eSBen Skeggs if (ram->mode != 2) { 655639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); 656639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 657639c308eSBen Skeggs } 658639c308eSBen Skeggs 659639c308eSBen Skeggs if (next->bios.ramcfg_11_07_02) 660639c308eSBen Skeggs gk104_ram_train(fuc, 0x80020000, 0x01000000); 661639c308eSBen Skeggs 662639c308eSBen Skeggs ram_unblock(fuc); 663380b1cadSKarol Herbst 664380b1cadSKarol Herbst if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 665639c308eSBen Skeggs ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 666639c308eSBen Skeggs 667639c308eSBen Skeggs if (next->bios.rammap_11_08_01) 668639c308eSBen Skeggs data = 0x00000800; 669639c308eSBen Skeggs else 670639c308eSBen Skeggs data = 0x00000000; 671639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x00000800, data); 672639c308eSBen Skeggs ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); 673639c308eSBen Skeggs return 0; 674639c308eSBen Skeggs } 675639c308eSBen Skeggs 676639c308eSBen Skeggs /******************************************************************************* 677639c308eSBen Skeggs * DDR3 678639c308eSBen Skeggs ******************************************************************************/ 679639c308eSBen Skeggs 680b4f2bf33SRoy Spliet static void 681b4f2bf33SRoy Spliet nvkm_sddr3_dll_reset(struct gk104_ramfuc *fuc) 682b4f2bf33SRoy Spliet { 683b4f2bf33SRoy Spliet ram_nuke(fuc, mr[0]); 684b4f2bf33SRoy Spliet ram_mask(fuc, mr[0], 0x100, 0x100); 685b4f2bf33SRoy Spliet ram_mask(fuc, mr[0], 0x100, 0x000); 686b4f2bf33SRoy Spliet } 687b4f2bf33SRoy Spliet 688b4f2bf33SRoy Spliet static void 689b4f2bf33SRoy Spliet nvkm_sddr3_dll_disable(struct gk104_ramfuc *fuc) 690b4f2bf33SRoy Spliet { 691b4f2bf33SRoy Spliet u32 mr1_old = ram_rd32(fuc, mr[1]); 692b4f2bf33SRoy Spliet 693b4f2bf33SRoy Spliet if (!(mr1_old & 0x1)) { 694b4f2bf33SRoy Spliet ram_mask(fuc, mr[1], 0x1, 0x1); 695b4f2bf33SRoy Spliet ram_nsec(fuc, 1000); 696b4f2bf33SRoy Spliet } 697b4f2bf33SRoy Spliet } 698b4f2bf33SRoy Spliet 699639c308eSBen Skeggs static int 700d36a99d2SBen Skeggs gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) 701639c308eSBen Skeggs { 702639c308eSBen Skeggs struct gk104_ramfuc *fuc = &ram->fuc; 703639c308eSBen Skeggs const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 704639c308eSBen Skeggs const u32 runk0 = ram->fN1 << 16; 705639c308eSBen Skeggs const u32 runk1 = ram->fN1; 706639c308eSBen Skeggs struct nvkm_ram_data *next = ram->base.next; 707639c308eSBen Skeggs int vc = !next->bios.ramcfg_11_02_08; 708639c308eSBen Skeggs int mv = !next->bios.ramcfg_11_02_04; 709639c308eSBen Skeggs u32 mask, data; 710639c308eSBen Skeggs 711639c308eSBen Skeggs ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 712639c308eSBen Skeggs ram_block(fuc); 713380b1cadSKarol Herbst 714380b1cadSKarol Herbst if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 715639c308eSBen Skeggs ram_wr32(fuc, 0x62c000, 0x0f0f0000); 716639c308eSBen Skeggs 717639c308eSBen Skeggs if (vc == 1 && ram_have(fuc, gpio2E)) { 718639c308eSBen Skeggs u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); 719639c308eSBen Skeggs if (temp != ram_rd32(fuc, gpio2E)) { 720639c308eSBen Skeggs ram_wr32(fuc, gpiotrig, 1); 721639c308eSBen Skeggs ram_nsec(fuc, 20000); 722639c308eSBen Skeggs } 723639c308eSBen Skeggs } 724639c308eSBen Skeggs 725639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 726639c308eSBen Skeggs if (next->bios.ramcfg_11_03_f0) 727639c308eSBen Skeggs ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); 728639c308eSBen Skeggs 729639c308eSBen Skeggs ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 730b4f2bf33SRoy Spliet 731b4f2bf33SRoy Spliet if (next->bios.ramcfg_DLLoff) 732b4f2bf33SRoy Spliet nvkm_sddr3_dll_disable(fuc); 733b4f2bf33SRoy Spliet 734639c308eSBen Skeggs ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ 735639c308eSBen Skeggs ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 736639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 737639c308eSBen Skeggs ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 738639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 739639c308eSBen Skeggs ram_nsec(fuc, 1000); 740639c308eSBen Skeggs 741639c308eSBen Skeggs ram_wr32(fuc, 0x10f090, 0x00000060); 742639c308eSBen Skeggs ram_wr32(fuc, 0x10f090, 0xc000007e); 743639c308eSBen Skeggs 744639c308eSBen Skeggs /*XXX: there does appear to be some kind of condition here, simply 745639c308eSBen Skeggs * modifying these bits in the vbios from the default pl0 746639c308eSBen Skeggs * entries shows no change. however, the data does appear to 747639c308eSBen Skeggs * be correct and may be required for the transition back 748639c308eSBen Skeggs */ 749639c308eSBen Skeggs mask = 0x00010000; 750639c308eSBen Skeggs data = 0x00010000; 751639c308eSBen Skeggs 752639c308eSBen Skeggs if (1) { 753639c308eSBen Skeggs mask |= 0x800807e0; 754639c308eSBen Skeggs data |= 0x800807e0; 755639c308eSBen Skeggs switch (next->bios.ramcfg_11_03_c0) { 756639c308eSBen Skeggs case 3: data &= ~0x00000040; break; 757639c308eSBen Skeggs case 2: data &= ~0x00000100; break; 758639c308eSBen Skeggs case 1: data &= ~0x80000000; break; 759639c308eSBen Skeggs case 0: data &= ~0x00000400; break; 760639c308eSBen Skeggs } 761639c308eSBen Skeggs 762639c308eSBen Skeggs switch (next->bios.ramcfg_11_03_30) { 763639c308eSBen Skeggs case 3: data &= ~0x00000020; break; 764639c308eSBen Skeggs case 2: data &= ~0x00000080; break; 765639c308eSBen Skeggs case 1: data &= ~0x00080000; break; 766639c308eSBen Skeggs case 0: data &= ~0x00000200; break; 767639c308eSBen Skeggs } 768639c308eSBen Skeggs } 769639c308eSBen Skeggs 770639c308eSBen Skeggs if (next->bios.ramcfg_11_02_80) 771639c308eSBen Skeggs mask |= 0x03000000; 772639c308eSBen Skeggs if (next->bios.ramcfg_11_02_40) 773639c308eSBen Skeggs mask |= 0x00002000; 774639c308eSBen Skeggs if (next->bios.ramcfg_11_07_10) 775639c308eSBen Skeggs mask |= 0x00004000; 776639c308eSBen Skeggs if (next->bios.ramcfg_11_07_08) 777639c308eSBen Skeggs mask |= 0x00000003; 778639c308eSBen Skeggs else 779639c308eSBen Skeggs mask |= 0x14000000; 780639c308eSBen Skeggs ram_mask(fuc, 0x10f824, mask, data); 781639c308eSBen Skeggs 782639c308eSBen Skeggs ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); 783639c308eSBen Skeggs 784639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 785639c308eSBen Skeggs data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 786639c308eSBen Skeggs data |= next->bios.ramcfg_11_03_30 << 16; 787639c308eSBen Skeggs ram_wr32(fuc, 0x1373ec, data); 788639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 789639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 790639c308eSBen Skeggs 791639c308eSBen Skeggs /* (re)program refpll, if required */ 792639c308eSBen Skeggs if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || 793639c308eSBen Skeggs (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { 794639c308eSBen Skeggs ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); 795639c308eSBen Skeggs ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); 796639c308eSBen Skeggs ram_wr32(fuc, 0x137320, 0x00000000); 797639c308eSBen Skeggs ram_mask(fuc, 0x132030, 0xffff0000, runk0); 798639c308eSBen Skeggs ram_mask(fuc, 0x132034, 0x0000ffff, runk1); 799639c308eSBen Skeggs ram_wr32(fuc, 0x132024, rcoef); 800639c308eSBen Skeggs ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); 801639c308eSBen Skeggs ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); 802639c308eSBen Skeggs ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); 803639c308eSBen Skeggs ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); 804639c308eSBen Skeggs } 805639c308eSBen Skeggs 806639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010); 807639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); 808639c308eSBen Skeggs ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); 809639c308eSBen Skeggs 810639c308eSBen Skeggs if (ram_have(fuc, gpioMV)) { 811639c308eSBen Skeggs u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); 812639c308eSBen Skeggs if (temp != ram_rd32(fuc, gpioMV)) { 813639c308eSBen Skeggs ram_wr32(fuc, gpiotrig, 1); 814639c308eSBen Skeggs ram_nsec(fuc, 64000); 815639c308eSBen Skeggs } 816639c308eSBen Skeggs } 817639c308eSBen Skeggs 818639c308eSBen Skeggs if (next->bios.ramcfg_11_02_40 || 819639c308eSBen Skeggs next->bios.ramcfg_11_07_10) { 820639c308eSBen Skeggs ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 821639c308eSBen Skeggs ram_nsec(fuc, 20000); 822639c308eSBen Skeggs } 823639c308eSBen Skeggs 824639c308eSBen Skeggs if (ram->mode != 2) /*XXX*/ { 825639c308eSBen Skeggs if (next->bios.ramcfg_11_07_40) 826639c308eSBen Skeggs ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 827639c308eSBen Skeggs } 828639c308eSBen Skeggs 829639c308eSBen Skeggs ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); 830639c308eSBen Skeggs ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); 831639c308eSBen Skeggs ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); 832639c308eSBen Skeggs 833639c308eSBen Skeggs mask = 0x00010000; 834639c308eSBen Skeggs data = 0x00000000; 835639c308eSBen Skeggs if (!next->bios.ramcfg_11_02_80) 836639c308eSBen Skeggs data |= 0x03000000; 837639c308eSBen Skeggs if (!next->bios.ramcfg_11_02_40) 838639c308eSBen Skeggs data |= 0x00002000; 839639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_10) 840639c308eSBen Skeggs data |= 0x00004000; 841639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_08) 842639c308eSBen Skeggs data |= 0x00000003; 843639c308eSBen Skeggs else 844639c308eSBen Skeggs data |= 0x14000000; 845639c308eSBen Skeggs ram_mask(fuc, 0x10f824, mask, data); 846639c308eSBen Skeggs ram_nsec(fuc, 1000); 847639c308eSBen Skeggs 848639c308eSBen Skeggs if (next->bios.ramcfg_11_08_01) 849639c308eSBen Skeggs data = 0x00100000; 850639c308eSBen Skeggs else 851639c308eSBen Skeggs data = 0x00000000; 852639c308eSBen Skeggs ram_mask(fuc, 0x10f82c, 0x00100000, data); 853639c308eSBen Skeggs 854639c308eSBen Skeggs /* PFB timing */ 855639c308eSBen Skeggs ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); 856639c308eSBen Skeggs ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); 857639c308eSBen Skeggs ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); 858639c308eSBen Skeggs ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); 859639c308eSBen Skeggs ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); 860639c308eSBen Skeggs ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); 861639c308eSBen Skeggs ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); 862639c308eSBen Skeggs ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); 863639c308eSBen Skeggs ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); 864639c308eSBen Skeggs ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); 865639c308eSBen Skeggs ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); 866639c308eSBen Skeggs 867639c308eSBen Skeggs mask = 0x33f00000; 868639c308eSBen Skeggs data = 0x00000000; 869639c308eSBen Skeggs if (!next->bios.ramcfg_11_01_04) 870639c308eSBen Skeggs data |= 0x20200000; 871639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_80) 872639c308eSBen Skeggs data |= 0x12800000; 873639c308eSBen Skeggs /*XXX: see note above about there probably being some condition 874639c308eSBen Skeggs * for the 10f824 stuff that uses ramcfg 3... 875639c308eSBen Skeggs */ 876639c308eSBen Skeggs if (next->bios.ramcfg_11_03_f0) { 877639c308eSBen Skeggs if (next->bios.rammap_11_08_0c) { 878639c308eSBen Skeggs if (!next->bios.ramcfg_11_07_80) 879639c308eSBen Skeggs mask |= 0x00000020; 880639c308eSBen Skeggs else 881639c308eSBen Skeggs data |= 0x00000020; 882639c308eSBen Skeggs mask |= 0x08000004; 883639c308eSBen Skeggs } 884639c308eSBen Skeggs data |= 0x04000000; 885639c308eSBen Skeggs } else { 886639c308eSBen Skeggs mask |= 0x44000020; 887639c308eSBen Skeggs data |= 0x08000004; 888639c308eSBen Skeggs } 889639c308eSBen Skeggs 890639c308eSBen Skeggs ram_mask(fuc, 0x10f808, mask, data); 891639c308eSBen Skeggs 892639c308eSBen Skeggs ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); 893639c308eSBen Skeggs 894639c308eSBen Skeggs ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); 895639c308eSBen Skeggs 896639c308eSBen Skeggs data = (next->bios.timing[10] & 0x7f000000) >> 24; 897639c308eSBen Skeggs if (data < next->bios.timing_20_2c_1fc0) 898639c308eSBen Skeggs data = next->bios.timing_20_2c_1fc0; 899639c308eSBen Skeggs ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 900639c308eSBen Skeggs 901639c308eSBen Skeggs ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 902639c308eSBen Skeggs 903639c308eSBen Skeggs ram_wr32(fuc, 0x10f090, 0x4000007f); 904639c308eSBen Skeggs ram_nsec(fuc, 1000); 905639c308eSBen Skeggs 906639c308eSBen Skeggs ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 907639c308eSBen Skeggs ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 908639c308eSBen Skeggs ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 909639c308eSBen Skeggs ram_nsec(fuc, 1000); 910639c308eSBen Skeggs 911b4f2bf33SRoy Spliet if (!next->bios.ramcfg_DLLoff) { 912b4f2bf33SRoy Spliet ram_mask(fuc, mr[1], 0x1, 0x0); 913b4f2bf33SRoy Spliet nvkm_sddr3_dll_reset(fuc); 914b4f2bf33SRoy Spliet } 915639c308eSBen Skeggs 916b4f2bf33SRoy Spliet ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]); 917b4f2bf33SRoy Spliet ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]); 918639c308eSBen Skeggs ram_wr32(fuc, mr[0], ram->base.mr[0]); 919639c308eSBen Skeggs ram_nsec(fuc, 1000); 920639c308eSBen Skeggs 921b4f2bf33SRoy Spliet if (!next->bios.ramcfg_DLLoff) { 922b4f2bf33SRoy Spliet nvkm_sddr3_dll_reset(fuc); 923b4f2bf33SRoy Spliet ram_nsec(fuc, 1000); 924b4f2bf33SRoy Spliet } 925639c308eSBen Skeggs 926639c308eSBen Skeggs if (vc == 0 && ram_have(fuc, gpio2E)) { 927639c308eSBen Skeggs u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); 928639c308eSBen Skeggs if (temp != ram_rd32(fuc, gpio2E)) { 929639c308eSBen Skeggs ram_wr32(fuc, gpiotrig, 1); 930639c308eSBen Skeggs ram_nsec(fuc, 20000); 931639c308eSBen Skeggs } 932639c308eSBen Skeggs } 933639c308eSBen Skeggs 934639c308eSBen Skeggs if (ram->mode != 2) { 935639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); 936639c308eSBen Skeggs ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 937639c308eSBen Skeggs } 938639c308eSBen Skeggs 939639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); 940639c308eSBen Skeggs ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 941639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 942639c308eSBen Skeggs ram_nsec(fuc, 1000); 943639c308eSBen Skeggs 944639c308eSBen Skeggs ram_unblock(fuc); 945380b1cadSKarol Herbst 946380b1cadSKarol Herbst if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) 947639c308eSBen Skeggs ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 948639c308eSBen Skeggs 949639c308eSBen Skeggs if (next->bios.rammap_11_08_01) 950639c308eSBen Skeggs data = 0x00000800; 951639c308eSBen Skeggs else 952639c308eSBen Skeggs data = 0x00000000; 953639c308eSBen Skeggs ram_mask(fuc, 0x10f200, 0x00000800, data); 954639c308eSBen Skeggs return 0; 955639c308eSBen Skeggs } 956639c308eSBen Skeggs 957639c308eSBen Skeggs /******************************************************************************* 958639c308eSBen Skeggs * main hooks 959639c308eSBen Skeggs ******************************************************************************/ 960639c308eSBen Skeggs 961639c308eSBen Skeggs static int 962d36a99d2SBen Skeggs gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data) 963639c308eSBen Skeggs { 964d36a99d2SBen Skeggs struct nvkm_subdev *subdev = &ram->base.fb->subdev; 965639c308eSBen Skeggs struct nvkm_ram_data *cfg; 966639c308eSBen Skeggs u32 mhz = khz / 1000; 967639c308eSBen Skeggs 968639c308eSBen Skeggs list_for_each_entry(cfg, &ram->cfg, head) { 969639c308eSBen Skeggs if (mhz >= cfg->bios.rammap_min && 970639c308eSBen Skeggs mhz <= cfg->bios.rammap_max) { 971639c308eSBen Skeggs *data = *cfg; 972639c308eSBen Skeggs data->freq = khz; 973639c308eSBen Skeggs return 0; 974639c308eSBen Skeggs } 975639c308eSBen Skeggs } 976639c308eSBen Skeggs 977d36a99d2SBen Skeggs nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz); 978639c308eSBen Skeggs return -EINVAL; 979639c308eSBen Skeggs } 980639c308eSBen Skeggs 981639c308eSBen Skeggs static int 98278eaf335SKarol Herbst gk104_calc_pll_output(int fN, int M, int N, int P, int clk) 98378eaf335SKarol Herbst { 98478eaf335SKarol Herbst return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P); 98578eaf335SKarol Herbst } 98678eaf335SKarol Herbst 98778eaf335SKarol Herbst static int 98878eaf335SKarol Herbst gk104_pll_calc_hiclk(int target_khz, int crystal, 98978eaf335SKarol Herbst int *N1, int *fN1, int *M1, int *P1, 99078eaf335SKarol Herbst int *N2, int *M2, int *P2) 99178eaf335SKarol Herbst { 9927eb7497eSBen Skeggs int best_err = target_khz, p_ref, n_ref; 99378eaf335SKarol Herbst bool upper = false; 99478eaf335SKarol Herbst 99578eaf335SKarol Herbst *M1 = 1; 99678eaf335SKarol Herbst /* M has to be 1, otherwise it gets unstable */ 99778eaf335SKarol Herbst *M2 = 1; 99878eaf335SKarol Herbst /* can be 1 or 2, sticking with 1 for simplicity */ 99978eaf335SKarol Herbst *P2 = 1; 100078eaf335SKarol Herbst 100178eaf335SKarol Herbst for (p_ref = 0x7; p_ref >= 0x5; --p_ref) { 100278eaf335SKarol Herbst for (n_ref = 0x25; n_ref <= 0x2b; ++n_ref) { 100378eaf335SKarol Herbst int cur_N, cur_clk, cur_err; 100478eaf335SKarol Herbst 100578eaf335SKarol Herbst cur_clk = gk104_calc_pll_output(0, 1, n_ref, p_ref, crystal); 100678eaf335SKarol Herbst cur_N = target_khz / cur_clk; 100778eaf335SKarol Herbst cur_err = target_khz 100878eaf335SKarol Herbst - gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk); 100978eaf335SKarol Herbst 101078eaf335SKarol Herbst /* we found a better combination */ 101178eaf335SKarol Herbst if (cur_err < best_err) { 101278eaf335SKarol Herbst best_err = cur_err; 101378eaf335SKarol Herbst *N2 = cur_N; 101478eaf335SKarol Herbst *N1 = n_ref; 101578eaf335SKarol Herbst *P1 = p_ref; 101678eaf335SKarol Herbst upper = false; 101778eaf335SKarol Herbst } 101878eaf335SKarol Herbst 101978eaf335SKarol Herbst cur_N += 1; 102078eaf335SKarol Herbst cur_err = gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk) 102178eaf335SKarol Herbst - target_khz; 102278eaf335SKarol Herbst if (cur_err < best_err) { 102378eaf335SKarol Herbst best_err = cur_err; 102478eaf335SKarol Herbst *N2 = cur_N; 102578eaf335SKarol Herbst *N1 = n_ref; 102678eaf335SKarol Herbst *P1 = p_ref; 102778eaf335SKarol Herbst upper = true; 102878eaf335SKarol Herbst } 102978eaf335SKarol Herbst } 103078eaf335SKarol Herbst } 103178eaf335SKarol Herbst 103278eaf335SKarol Herbst /* adjust fN to get closer to the target clock */ 103378eaf335SKarol Herbst *fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal); 103478eaf335SKarol Herbst if (upper) 103578eaf335SKarol Herbst *fN1 = (u16)(1 - *fN1); 103678eaf335SKarol Herbst 103778eaf335SKarol Herbst return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal); 103878eaf335SKarol Herbst } 103978eaf335SKarol Herbst 104078eaf335SKarol Herbst static int 1041d36a99d2SBen Skeggs gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next) 1042639c308eSBen Skeggs { 1043639c308eSBen Skeggs struct gk104_ramfuc *fuc = &ram->fuc; 1044d36a99d2SBen Skeggs struct nvkm_subdev *subdev = &ram->base.fb->subdev; 1045639c308eSBen Skeggs int refclk, i; 1046639c308eSBen Skeggs int ret; 1047639c308eSBen Skeggs 1048d36a99d2SBen Skeggs ret = ram_init(fuc, ram->base.fb); 1049639c308eSBen Skeggs if (ret) 1050639c308eSBen Skeggs return ret; 1051639c308eSBen Skeggs 1052639c308eSBen Skeggs ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; 1053639c308eSBen Skeggs ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; 1054639c308eSBen Skeggs 1055639c308eSBen Skeggs /* XXX: this is *not* what nvidia do. on fermi nvidia generally 1056639c308eSBen Skeggs * select, based on some unknown condition, one of the two possible 1057639c308eSBen Skeggs * reference frequencies listed in the vbios table for mempll and 1058639c308eSBen Skeggs * program refpll to that frequency. 1059639c308eSBen Skeggs * 1060639c308eSBen Skeggs * so far, i've seen very weird values being chosen by nvidia on 1061639c308eSBen Skeggs * kepler boards, no idea how/why they're chosen. 1062639c308eSBen Skeggs */ 1063639c308eSBen Skeggs refclk = next->freq; 106478eaf335SKarol Herbst if (ram->mode == 2) { 106578eaf335SKarol Herbst ret = gk104_pll_calc_hiclk(next->freq, subdev->device->crystal, 106678eaf335SKarol Herbst &ram->N1, &ram->fN1, &ram->M1, &ram->P1, 106778eaf335SKarol Herbst &ram->N2, &ram->M2, &ram->P2); 106878eaf335SKarol Herbst fuc->mempll.refclk = ret; 106978eaf335SKarol Herbst if (ret <= 0) { 107078eaf335SKarol Herbst nvkm_error(subdev, "unable to calc plls\n"); 107178eaf335SKarol Herbst return -EINVAL; 107278eaf335SKarol Herbst } 107378eaf335SKarol Herbst nvkm_debug(subdev, "sucessfully calced PLLs for clock %i kHz" 107478eaf335SKarol Herbst " (refclock: %i kHz)\n", next->freq, ret); 107578eaf335SKarol Herbst } else { 1076639c308eSBen Skeggs /* calculate refpll coefficients */ 1077d36a99d2SBen Skeggs ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1, 1078639c308eSBen Skeggs &ram->fN1, &ram->M1, &ram->P1); 1079639c308eSBen Skeggs fuc->mempll.refclk = ret; 1080639c308eSBen Skeggs if (ret <= 0) { 10813ecd329bSBen Skeggs nvkm_error(subdev, "unable to calc refpll\n"); 1082639c308eSBen Skeggs return -EINVAL; 1083639c308eSBen Skeggs } 1084639c308eSBen Skeggs } 1085639c308eSBen Skeggs 1086639c308eSBen Skeggs for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) { 1087639c308eSBen Skeggs if (ram_have(fuc, mr[i])) 1088639c308eSBen Skeggs ram->base.mr[i] = ram_rd32(fuc, mr[i]); 1089639c308eSBen Skeggs } 1090639c308eSBen Skeggs ram->base.freq = next->freq; 1091639c308eSBen Skeggs 1092639c308eSBen Skeggs switch (ram->base.type) { 1093d36a99d2SBen Skeggs case NVKM_RAM_TYPE_DDR3: 1094639c308eSBen Skeggs ret = nvkm_sddr3_calc(&ram->base); 1095639c308eSBen Skeggs if (ret == 0) 1096d36a99d2SBen Skeggs ret = gk104_ram_calc_sddr3(ram, next->freq); 1097639c308eSBen Skeggs break; 1098d36a99d2SBen Skeggs case NVKM_RAM_TYPE_GDDR5: 1099639c308eSBen Skeggs ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); 1100639c308eSBen Skeggs if (ret == 0) 1101d36a99d2SBen Skeggs ret = gk104_ram_calc_gddr5(ram, next->freq); 1102639c308eSBen Skeggs break; 1103639c308eSBen Skeggs default: 1104639c308eSBen Skeggs ret = -ENOSYS; 1105639c308eSBen Skeggs break; 1106639c308eSBen Skeggs } 1107639c308eSBen Skeggs 1108639c308eSBen Skeggs return ret; 1109639c308eSBen Skeggs } 1110639c308eSBen Skeggs 1111fcb371a1SBen Skeggs int 1112d36a99d2SBen Skeggs gk104_ram_calc(struct nvkm_ram *base, u32 freq) 1113639c308eSBen Skeggs { 1114d36a99d2SBen Skeggs struct gk104_ram *ram = gk104_ram(base); 1115d36a99d2SBen Skeggs struct nvkm_clk *clk = ram->base.fb->subdev.device->clk; 1116639c308eSBen Skeggs struct nvkm_ram_data *xits = &ram->base.xition; 1117639c308eSBen Skeggs struct nvkm_ram_data *copy; 1118639c308eSBen Skeggs int ret; 1119639c308eSBen Skeggs 1120639c308eSBen Skeggs if (ram->base.next == NULL) { 11216625f55cSBen Skeggs ret = gk104_ram_calc_data(ram, 11226625f55cSBen Skeggs nvkm_clk_read(clk, nv_clk_src_mem), 1123639c308eSBen Skeggs &ram->base.former); 1124639c308eSBen Skeggs if (ret) 1125639c308eSBen Skeggs return ret; 1126639c308eSBen Skeggs 1127d36a99d2SBen Skeggs ret = gk104_ram_calc_data(ram, freq, &ram->base.target); 1128639c308eSBen Skeggs if (ret) 1129639c308eSBen Skeggs return ret; 1130639c308eSBen Skeggs 1131639c308eSBen Skeggs if (ram->base.target.freq < ram->base.former.freq) { 1132639c308eSBen Skeggs *xits = ram->base.target; 1133639c308eSBen Skeggs copy = &ram->base.former; 1134639c308eSBen Skeggs } else { 1135639c308eSBen Skeggs *xits = ram->base.former; 1136639c308eSBen Skeggs copy = &ram->base.target; 1137639c308eSBen Skeggs } 1138639c308eSBen Skeggs 1139639c308eSBen Skeggs xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; 1140639c308eSBen Skeggs xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; 1141639c308eSBen Skeggs xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; 1142639c308eSBen Skeggs 1143639c308eSBen Skeggs ram->base.next = &ram->base.target; 1144639c308eSBen Skeggs if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) 1145639c308eSBen Skeggs ram->base.next = &ram->base.xition; 1146639c308eSBen Skeggs } else { 1147639c308eSBen Skeggs BUG_ON(ram->base.next != &ram->base.xition); 1148639c308eSBen Skeggs ram->base.next = &ram->base.target; 1149639c308eSBen Skeggs } 1150639c308eSBen Skeggs 1151d36a99d2SBen Skeggs return gk104_ram_calc_xits(ram, ram->base.next); 1152639c308eSBen Skeggs } 1153639c308eSBen Skeggs 1154639c308eSBen Skeggs static void 1155d36a99d2SBen Skeggs gk104_ram_prog_0(struct gk104_ram *ram, u32 freq) 1156639c308eSBen Skeggs { 1157d36a99d2SBen Skeggs struct nvkm_device *device = ram->base.fb->subdev.device; 1158639c308eSBen Skeggs struct nvkm_ram_data *cfg; 1159639c308eSBen Skeggs u32 mhz = freq / 1000; 1160639c308eSBen Skeggs u32 mask, data; 1161639c308eSBen Skeggs 1162639c308eSBen Skeggs list_for_each_entry(cfg, &ram->cfg, head) { 1163639c308eSBen Skeggs if (mhz >= cfg->bios.rammap_min && 1164639c308eSBen Skeggs mhz <= cfg->bios.rammap_max) 1165639c308eSBen Skeggs break; 1166639c308eSBen Skeggs } 1167639c308eSBen Skeggs 1168639c308eSBen Skeggs if (&cfg->head == &ram->cfg) 1169639c308eSBen Skeggs return; 1170639c308eSBen Skeggs 1171639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { 1172639c308eSBen Skeggs data |= cfg->bios.rammap_11_0a_03fe << 12; 1173639c308eSBen Skeggs mask |= 0x001ff000; 1174639c308eSBen Skeggs } 1175639c308eSBen Skeggs if (ram->diff.rammap_11_09_01ff) { 1176639c308eSBen Skeggs data |= cfg->bios.rammap_11_09_01ff; 1177639c308eSBen Skeggs mask |= 0x000001ff; 1178639c308eSBen Skeggs } 11796758745bSBen Skeggs nvkm_mask(device, 0x10f468, mask, data); 1180639c308eSBen Skeggs 1181639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { 1182639c308eSBen Skeggs data |= cfg->bios.rammap_11_0a_0400; 1183639c308eSBen Skeggs mask |= 0x00000001; 1184639c308eSBen Skeggs } 11856758745bSBen Skeggs nvkm_mask(device, 0x10f420, mask, data); 1186639c308eSBen Skeggs 1187639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { 1188639c308eSBen Skeggs data |= cfg->bios.rammap_11_0a_0800; 1189639c308eSBen Skeggs mask |= 0x00000001; 1190639c308eSBen Skeggs } 11916758745bSBen Skeggs nvkm_mask(device, 0x10f430, mask, data); 1192639c308eSBen Skeggs 1193639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { 1194639c308eSBen Skeggs data |= cfg->bios.rammap_11_0b_01f0; 1195639c308eSBen Skeggs mask |= 0x0000001f; 1196639c308eSBen Skeggs } 11976758745bSBen Skeggs nvkm_mask(device, 0x10f400, mask, data); 1198639c308eSBen Skeggs 1199639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { 1200639c308eSBen Skeggs data |= cfg->bios.rammap_11_0b_0200 << 9; 1201639c308eSBen Skeggs mask |= 0x00000200; 1202639c308eSBen Skeggs } 12036758745bSBen Skeggs nvkm_mask(device, 0x10f410, mask, data); 1204639c308eSBen Skeggs 1205639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0d) { 1206639c308eSBen Skeggs data |= cfg->bios.rammap_11_0d << 16; 1207639c308eSBen Skeggs mask |= 0x00ff0000; 1208639c308eSBen Skeggs } 1209639c308eSBen Skeggs if (ram->diff.rammap_11_0f) { 1210639c308eSBen Skeggs data |= cfg->bios.rammap_11_0f << 8; 1211639c308eSBen Skeggs mask |= 0x0000ff00; 1212639c308eSBen Skeggs } 12136758745bSBen Skeggs nvkm_mask(device, 0x10f440, mask, data); 1214639c308eSBen Skeggs 1215639c308eSBen Skeggs if (mask = 0, data = 0, ram->diff.rammap_11_0e) { 1216639c308eSBen Skeggs data |= cfg->bios.rammap_11_0e << 8; 1217639c308eSBen Skeggs mask |= 0x0000ff00; 1218639c308eSBen Skeggs } 1219639c308eSBen Skeggs if (ram->diff.rammap_11_0b_0800) { 1220639c308eSBen Skeggs data |= cfg->bios.rammap_11_0b_0800 << 7; 1221639c308eSBen Skeggs mask |= 0x00000080; 1222639c308eSBen Skeggs } 1223639c308eSBen Skeggs if (ram->diff.rammap_11_0b_0400) { 1224639c308eSBen Skeggs data |= cfg->bios.rammap_11_0b_0400 << 5; 1225639c308eSBen Skeggs mask |= 0x00000020; 1226639c308eSBen Skeggs } 12276758745bSBen Skeggs nvkm_mask(device, 0x10f444, mask, data); 1228639c308eSBen Skeggs } 1229639c308eSBen Skeggs 1230fcb371a1SBen Skeggs int 1231d36a99d2SBen Skeggs gk104_ram_prog(struct nvkm_ram *base) 1232639c308eSBen Skeggs { 1233d36a99d2SBen Skeggs struct gk104_ram *ram = gk104_ram(base); 1234639c308eSBen Skeggs struct gk104_ramfuc *fuc = &ram->fuc; 1235d36a99d2SBen Skeggs struct nvkm_device *device = ram->base.fb->subdev.device; 1236639c308eSBen Skeggs struct nvkm_ram_data *next = ram->base.next; 1237639c308eSBen Skeggs 1238639c308eSBen Skeggs if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) { 1239639c308eSBen Skeggs ram_exec(fuc, false); 1240639c308eSBen Skeggs return (ram->base.next == &ram->base.xition); 1241639c308eSBen Skeggs } 1242639c308eSBen Skeggs 1243d36a99d2SBen Skeggs gk104_ram_prog_0(ram, 1000); 1244639c308eSBen Skeggs ram_exec(fuc, true); 1245d36a99d2SBen Skeggs gk104_ram_prog_0(ram, next->freq); 1246639c308eSBen Skeggs 1247639c308eSBen Skeggs return (ram->base.next == &ram->base.xition); 1248639c308eSBen Skeggs } 1249639c308eSBen Skeggs 1250fcb371a1SBen Skeggs void 1251d36a99d2SBen Skeggs gk104_ram_tidy(struct nvkm_ram *base) 1252639c308eSBen Skeggs { 1253d36a99d2SBen Skeggs struct gk104_ram *ram = gk104_ram(base); 1254639c308eSBen Skeggs ram->base.next = NULL; 1255d36a99d2SBen Skeggs ram_exec(&ram->fuc, false); 1256639c308eSBen Skeggs } 1257639c308eSBen Skeggs 1258639c308eSBen Skeggs struct gk104_ram_train { 1259639c308eSBen Skeggs u16 mask; 1260639c308eSBen Skeggs struct nvbios_M0209S remap; 1261639c308eSBen Skeggs struct nvbios_M0209S type00; 1262639c308eSBen Skeggs struct nvbios_M0209S type01; 1263639c308eSBen Skeggs struct nvbios_M0209S type04; 1264639c308eSBen Skeggs struct nvbios_M0209S type06; 1265639c308eSBen Skeggs struct nvbios_M0209S type07; 1266639c308eSBen Skeggs struct nvbios_M0209S type08; 1267639c308eSBen Skeggs struct nvbios_M0209S type09; 1268639c308eSBen Skeggs }; 1269639c308eSBen Skeggs 1270639c308eSBen Skeggs static int 1271d36a99d2SBen Skeggs gk104_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg, 1272639c308eSBen Skeggs struct gk104_ram_train *train) 1273639c308eSBen Skeggs { 1274d36a99d2SBen Skeggs struct nvkm_bios *bios = ram->fb->subdev.device->bios; 1275639c308eSBen Skeggs struct nvbios_M0205E M0205E; 1276639c308eSBen Skeggs struct nvbios_M0205S M0205S; 1277639c308eSBen Skeggs struct nvbios_M0209E M0209E; 1278639c308eSBen Skeggs struct nvbios_M0209S *remap = &train->remap; 1279639c308eSBen Skeggs struct nvbios_M0209S *value; 1280639c308eSBen Skeggs u8 ver, hdr, cnt, len; 1281639c308eSBen Skeggs u32 data; 1282639c308eSBen Skeggs 1283639c308eSBen Skeggs /* determine type of data for this index */ 1284639c308eSBen Skeggs if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))) 1285639c308eSBen Skeggs return -ENOENT; 1286639c308eSBen Skeggs 1287639c308eSBen Skeggs switch (M0205E.type) { 1288639c308eSBen Skeggs case 0x00: value = &train->type00; break; 1289639c308eSBen Skeggs case 0x01: value = &train->type01; break; 1290639c308eSBen Skeggs case 0x04: value = &train->type04; break; 1291639c308eSBen Skeggs case 0x06: value = &train->type06; break; 1292639c308eSBen Skeggs case 0x07: value = &train->type07; break; 1293639c308eSBen Skeggs case 0x08: value = &train->type08; break; 1294639c308eSBen Skeggs case 0x09: value = &train->type09; break; 1295639c308eSBen Skeggs default: 1296639c308eSBen Skeggs return 0; 1297639c308eSBen Skeggs } 1298639c308eSBen Skeggs 1299639c308eSBen Skeggs /* training data index determined by ramcfg strap */ 1300639c308eSBen Skeggs if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S))) 1301639c308eSBen Skeggs return -EINVAL; 1302639c308eSBen Skeggs i = M0205S.data; 1303639c308eSBen Skeggs 1304639c308eSBen Skeggs /* training data format information */ 1305639c308eSBen Skeggs if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E))) 1306639c308eSBen Skeggs return -EINVAL; 1307639c308eSBen Skeggs 1308639c308eSBen Skeggs /* ... and the raw data */ 1309639c308eSBen Skeggs if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value))) 1310639c308eSBen Skeggs return -EINVAL; 1311639c308eSBen Skeggs 1312639c308eSBen Skeggs if (M0209E.v02_07 == 2) { 1313639c308eSBen Skeggs /* of course! why wouldn't we have a pointer to another entry 1314639c308eSBen Skeggs * in the same table, and use the first one as an array of 1315639c308eSBen Skeggs * remap indices... 1316639c308eSBen Skeggs */ 1317639c308eSBen Skeggs if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr, 1318639c308eSBen Skeggs remap))) 1319639c308eSBen Skeggs return -EINVAL; 1320639c308eSBen Skeggs 1321639c308eSBen Skeggs for (i = 0; i < ARRAY_SIZE(value->data); i++) 1322639c308eSBen Skeggs value->data[i] = remap->data[value->data[i]]; 1323639c308eSBen Skeggs } else 1324639c308eSBen Skeggs if (M0209E.v02_07 != 1) 1325639c308eSBen Skeggs return -EINVAL; 1326639c308eSBen Skeggs 1327639c308eSBen Skeggs train->mask |= 1 << M0205E.type; 1328639c308eSBen Skeggs return 0; 1329639c308eSBen Skeggs } 1330639c308eSBen Skeggs 1331639c308eSBen Skeggs static int 1332d36a99d2SBen Skeggs gk104_ram_train_init_0(struct nvkm_ram *ram, struct gk104_ram_train *train) 1333639c308eSBen Skeggs { 1334d36a99d2SBen Skeggs struct nvkm_subdev *subdev = &ram->fb->subdev; 13353ecd329bSBen Skeggs struct nvkm_device *device = subdev->device; 1336639c308eSBen Skeggs int i, j; 1337639c308eSBen Skeggs 1338639c308eSBen Skeggs if ((train->mask & 0x03d3) != 0x03d3) { 13393ecd329bSBen Skeggs nvkm_warn(subdev, "missing link training data\n"); 1340639c308eSBen Skeggs return -EINVAL; 1341639c308eSBen Skeggs } 1342639c308eSBen Skeggs 1343639c308eSBen Skeggs for (i = 0; i < 0x30; i++) { 1344639c308eSBen Skeggs for (j = 0; j < 8; j += 4) { 13456758745bSBen Skeggs nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8)); 13466758745bSBen Skeggs nvkm_wr32(device, 0x10f920 + j, 0x00000000 | 1347639c308eSBen Skeggs train->type08.data[i] << 4 | 1348639c308eSBen Skeggs train->type06.data[i]); 13496758745bSBen Skeggs nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]); 13506758745bSBen Skeggs nvkm_wr32(device, 0x10f920 + j, 0x00000100 | 1351639c308eSBen Skeggs train->type09.data[i] << 4 | 1352639c308eSBen Skeggs train->type07.data[i]); 13536758745bSBen Skeggs nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]); 1354639c308eSBen Skeggs } 1355639c308eSBen Skeggs } 1356639c308eSBen Skeggs 1357639c308eSBen Skeggs for (j = 0; j < 8; j += 4) { 1358639c308eSBen Skeggs for (i = 0; i < 0x100; i++) { 13596758745bSBen Skeggs nvkm_wr32(device, 0x10f968 + j, i); 13606758745bSBen Skeggs nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]); 1361639c308eSBen Skeggs } 1362639c308eSBen Skeggs } 1363639c308eSBen Skeggs 1364639c308eSBen Skeggs return 0; 1365639c308eSBen Skeggs } 1366639c308eSBen Skeggs 1367639c308eSBen Skeggs static int 1368d36a99d2SBen Skeggs gk104_ram_train_init(struct nvkm_ram *ram) 1369639c308eSBen Skeggs { 1370d36a99d2SBen Skeggs u8 ramcfg = nvbios_ramcfg_index(&ram->fb->subdev); 1371639c308eSBen Skeggs struct gk104_ram_train *train; 1372b1e4553cSBen Skeggs int ret, i; 1373639c308eSBen Skeggs 1374b1e4553cSBen Skeggs if (!(train = kzalloc(sizeof(*train), GFP_KERNEL))) 1375b1e4553cSBen Skeggs return -ENOMEM; 1376b1e4553cSBen Skeggs 1377639c308eSBen Skeggs for (i = 0; i < 0x100; i++) { 1378d36a99d2SBen Skeggs ret = gk104_ram_train_type(ram, i, ramcfg, train); 1379639c308eSBen Skeggs if (ret && ret != -ENOENT) 1380639c308eSBen Skeggs break; 1381639c308eSBen Skeggs } 1382639c308eSBen Skeggs 1383d36a99d2SBen Skeggs switch (ram->type) { 1384d36a99d2SBen Skeggs case NVKM_RAM_TYPE_GDDR5: 1385d36a99d2SBen Skeggs ret = gk104_ram_train_init_0(ram, train); 1386639c308eSBen Skeggs break; 1387639c308eSBen Skeggs default: 1388639c308eSBen Skeggs ret = 0; 1389639c308eSBen Skeggs break; 1390639c308eSBen Skeggs } 1391639c308eSBen Skeggs 1392639c308eSBen Skeggs kfree(train); 1393639c308eSBen Skeggs return ret; 1394639c308eSBen Skeggs } 1395639c308eSBen Skeggs 1396639c308eSBen Skeggs int 1397d36a99d2SBen Skeggs gk104_ram_init(struct nvkm_ram *ram) 1398639c308eSBen Skeggs { 1399d36a99d2SBen Skeggs struct nvkm_subdev *subdev = &ram->fb->subdev; 1400d36a99d2SBen Skeggs struct nvkm_device *device = subdev->device; 14016758745bSBen Skeggs struct nvkm_bios *bios = device->bios; 1402639c308eSBen Skeggs u8 ver, hdr, cnt, len, snr, ssz; 1403639c308eSBen Skeggs u32 data, save; 1404d36a99d2SBen Skeggs int i; 1405639c308eSBen Skeggs 1406639c308eSBen Skeggs /* run a bunch of tables from rammap table. there's actually 1407639c308eSBen Skeggs * individual pointers for each rammap entry too, but, nvidia 1408639c308eSBen Skeggs * seem to just run the last two entries' scripts early on in 1409639c308eSBen Skeggs * their init, and never again.. we'll just run 'em all once 1410639c308eSBen Skeggs * for now. 1411639c308eSBen Skeggs * 1412639c308eSBen Skeggs * i strongly suspect that each script is for a separate mode 1413639c308eSBen Skeggs * (likely selected by 0x10f65c's lower bits?), and the 1414639c308eSBen Skeggs * binary driver skips the one that's already been setup by 1415639c308eSBen Skeggs * the init tables. 1416639c308eSBen Skeggs */ 1417639c308eSBen Skeggs data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); 1418639c308eSBen Skeggs if (!data || hdr < 0x15) 1419639c308eSBen Skeggs return -EINVAL; 1420639c308eSBen Skeggs 14217f5f518fSBen Skeggs cnt = nvbios_rd08(bios, data + 0x14); /* guess at count */ 14227f5f518fSBen Skeggs data = nvbios_rd32(bios, data + 0x10); /* guess u32... */ 14236758745bSBen Skeggs save = nvkm_rd32(device, 0x10f65c) & 0x000000f0; 1424639c308eSBen Skeggs for (i = 0; i < cnt; i++, data += 4) { 1425639c308eSBen Skeggs if (i != save >> 4) { 14266758745bSBen Skeggs nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4); 1427639c308eSBen Skeggs nvbios_exec(&(struct nvbios_init) { 1428d36a99d2SBen Skeggs .subdev = subdev, 1429639c308eSBen Skeggs .bios = bios, 14307f5f518fSBen Skeggs .offset = nvbios_rd32(bios, data), 1431639c308eSBen Skeggs .execute = 1, 1432639c308eSBen Skeggs }); 1433639c308eSBen Skeggs } 1434639c308eSBen Skeggs } 14356758745bSBen Skeggs nvkm_mask(device, 0x10f65c, 0x000000f0, save); 14366758745bSBen Skeggs nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000); 14376758745bSBen Skeggs nvkm_wr32(device, 0x10ecc0, 0xffffffff); 14386758745bSBen Skeggs nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010); 1439639c308eSBen Skeggs 1440d36a99d2SBen Skeggs return gk104_ram_train_init(ram); 1441639c308eSBen Skeggs } 1442639c308eSBen Skeggs 1443639c308eSBen Skeggs static int 1444639c308eSBen Skeggs gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) 1445639c308eSBen Skeggs { 1446d36a99d2SBen Skeggs struct nvkm_bios *bios = ram->base.fb->subdev.device->bios; 1447639c308eSBen Skeggs struct nvkm_ram_data *cfg; 1448639c308eSBen Skeggs struct nvbios_ramcfg *d = &ram->diff; 1449639c308eSBen Skeggs struct nvbios_ramcfg *p, *n; 1450639c308eSBen Skeggs u8 ver, hdr, cnt, len; 1451639c308eSBen Skeggs u32 data; 1452639c308eSBen Skeggs int ret; 1453639c308eSBen Skeggs 1454639c308eSBen Skeggs if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL))) 1455639c308eSBen Skeggs return -ENOMEM; 1456639c308eSBen Skeggs p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios; 1457639c308eSBen Skeggs n = &cfg->bios; 1458639c308eSBen Skeggs 1459639c308eSBen Skeggs /* memory config data for a range of target frequencies */ 1460639c308eSBen Skeggs data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios); 1461639c308eSBen Skeggs if (ret = -ENOENT, !data) 1462639c308eSBen Skeggs goto done; 1463639c308eSBen Skeggs if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12) 1464639c308eSBen Skeggs goto done; 1465639c308eSBen Skeggs 1466639c308eSBen Skeggs /* ... and a portion specific to the attached memory */ 1467639c308eSBen Skeggs data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg, 1468639c308eSBen Skeggs &ver, &hdr, &cfg->bios); 1469639c308eSBen Skeggs if (ret = -EINVAL, !data) 1470639c308eSBen Skeggs goto done; 1471639c308eSBen Skeggs if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a) 1472639c308eSBen Skeggs goto done; 1473639c308eSBen Skeggs 1474639c308eSBen Skeggs /* lookup memory timings, if bios says they're present */ 1475639c308eSBen Skeggs if (cfg->bios.ramcfg_timing != 0xff) { 1476639c308eSBen Skeggs data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing, 1477639c308eSBen Skeggs &ver, &hdr, &cnt, &len, 1478639c308eSBen Skeggs &cfg->bios); 1479639c308eSBen Skeggs if (ret = -EINVAL, !data) 1480639c308eSBen Skeggs goto done; 1481639c308eSBen Skeggs if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33) 1482639c308eSBen Skeggs goto done; 1483639c308eSBen Skeggs } 1484639c308eSBen Skeggs 1485639c308eSBen Skeggs list_add_tail(&cfg->head, &ram->cfg); 1486639c308eSBen Skeggs if (ret = 0, i == 0) 1487639c308eSBen Skeggs goto done; 1488639c308eSBen Skeggs 1489639c308eSBen Skeggs d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe; 1490639c308eSBen Skeggs d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff; 1491639c308eSBen Skeggs d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400; 1492639c308eSBen Skeggs d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800; 1493639c308eSBen Skeggs d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0; 1494639c308eSBen Skeggs d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200; 1495639c308eSBen Skeggs d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d; 1496639c308eSBen Skeggs d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f; 1497639c308eSBen Skeggs d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e; 1498639c308eSBen Skeggs d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800; 1499639c308eSBen Skeggs d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400; 1500639c308eSBen Skeggs d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01; 1501639c308eSBen Skeggs d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02; 1502639c308eSBen Skeggs d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10; 1503639c308eSBen Skeggs d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03; 1504639c308eSBen Skeggs d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20; 1505639c308eSBen Skeggs d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07; 1506639c308eSBen Skeggs done: 1507639c308eSBen Skeggs if (ret) 1508639c308eSBen Skeggs kfree(cfg); 1509639c308eSBen Skeggs return ret; 1510639c308eSBen Skeggs } 1511639c308eSBen Skeggs 1512fcb371a1SBen Skeggs void * 1513d36a99d2SBen Skeggs gk104_ram_dtor(struct nvkm_ram *base) 1514639c308eSBen Skeggs { 1515d36a99d2SBen Skeggs struct gk104_ram *ram = gk104_ram(base); 1516639c308eSBen Skeggs struct nvkm_ram_data *cfg, *tmp; 1517639c308eSBen Skeggs 1518639c308eSBen Skeggs list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { 1519639c308eSBen Skeggs kfree(cfg); 1520639c308eSBen Skeggs } 1521639c308eSBen Skeggs 1522d36a99d2SBen Skeggs return ram; 1523639c308eSBen Skeggs } 1524639c308eSBen Skeggs 1525d36a99d2SBen Skeggs int 1526fcb371a1SBen Skeggs gk104_ram_new_(const struct nvkm_ram_func *func, struct nvkm_fb *fb, 1527fcb371a1SBen Skeggs struct nvkm_ram **pram, u32 maskaddr) 1528ebaf3e70SKarol Herbst { 15293ecd329bSBen Skeggs struct nvkm_subdev *subdev = &fb->subdev; 15303ecd329bSBen Skeggs struct nvkm_device *device = subdev->device; 15316758745bSBen Skeggs struct nvkm_bios *bios = device->bios; 1532fcb371a1SBen Skeggs struct dcb_gpio_func gpio; 1533639c308eSBen Skeggs struct gk104_ram *ram; 1534639c308eSBen Skeggs int ret, i; 153503c8952fSBen Skeggs u8 ramcfg = nvbios_ramcfg_index(subdev); 1536639c308eSBen Skeggs u32 tmp; 1537639c308eSBen Skeggs 1538d36a99d2SBen Skeggs if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) 1539d36a99d2SBen Skeggs return -ENOMEM; 1540d36a99d2SBen Skeggs *pram = &ram->base; 1541d36a99d2SBen Skeggs 1542fcb371a1SBen Skeggs ret = gf100_ram_ctor(func, fb, maskaddr, &ram->base); 1543639c308eSBen Skeggs if (ret) 1544639c308eSBen Skeggs return ret; 1545639c308eSBen Skeggs 1546639c308eSBen Skeggs INIT_LIST_HEAD(&ram->cfg); 1547639c308eSBen Skeggs 1548639c308eSBen Skeggs /* calculate a mask of differently configured memory partitions, 1549639c308eSBen Skeggs * because, of course reclocking wasn't complicated enough 1550639c308eSBen Skeggs * already without having to treat some of them differently to 1551639c308eSBen Skeggs * the others.... 1552639c308eSBen Skeggs */ 15536758745bSBen Skeggs ram->parts = nvkm_rd32(device, 0x022438); 15546758745bSBen Skeggs ram->pmask = nvkm_rd32(device, 0x022554); 1555639c308eSBen Skeggs ram->pnuts = 0; 1556639c308eSBen Skeggs for (i = 0, tmp = 0; i < ram->parts; i++) { 1557639c308eSBen Skeggs if (!(ram->pmask & (1 << i))) { 15586758745bSBen Skeggs u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000)); 1559639c308eSBen Skeggs if (tmp && tmp != cfg1) { 1560639c308eSBen Skeggs ram->pnuts |= (1 << i); 1561639c308eSBen Skeggs continue; 1562639c308eSBen Skeggs } 1563639c308eSBen Skeggs tmp = cfg1; 1564639c308eSBen Skeggs } 1565639c308eSBen Skeggs } 1566639c308eSBen Skeggs 1567639c308eSBen Skeggs /* parse bios data for all rammap table entries up-front, and 1568639c308eSBen Skeggs * build information on whether certain fields differ between 1569639c308eSBen Skeggs * any of the entries. 1570639c308eSBen Skeggs * 1571639c308eSBen Skeggs * the binary driver appears to completely ignore some fields 1572639c308eSBen Skeggs * when all entries contain the same value. at first, it was 1573639c308eSBen Skeggs * hoped that these were mere optimisations and the bios init 1574639c308eSBen Skeggs * tables had configured as per the values here, but there is 1575639c308eSBen Skeggs * evidence now to suggest that this isn't the case and we do 1576639c308eSBen Skeggs * need to treat this condition as a "don't touch" indicator. 1577639c308eSBen Skeggs */ 1578639c308eSBen Skeggs for (i = 0; !ret; i++) { 1579639c308eSBen Skeggs ret = gk104_ram_ctor_data(ram, ramcfg, i); 1580639c308eSBen Skeggs if (ret && ret != -ENOENT) { 15813ecd329bSBen Skeggs nvkm_error(subdev, "failed to parse ramcfg data\n"); 1582639c308eSBen Skeggs return ret; 1583639c308eSBen Skeggs } 1584639c308eSBen Skeggs } 1585639c308eSBen Skeggs 1586639c308eSBen Skeggs /* parse bios data for both pll's */ 1587639c308eSBen Skeggs ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); 1588639c308eSBen Skeggs if (ret) { 15893ecd329bSBen Skeggs nvkm_error(subdev, "mclk refpll data not found\n"); 1590639c308eSBen Skeggs return ret; 1591639c308eSBen Skeggs } 1592639c308eSBen Skeggs 1593639c308eSBen Skeggs ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll); 1594639c308eSBen Skeggs if (ret) { 15953ecd329bSBen Skeggs nvkm_error(subdev, "mclk pll data not found\n"); 1596639c308eSBen Skeggs return ret; 1597639c308eSBen Skeggs } 1598639c308eSBen Skeggs 1599639c308eSBen Skeggs /* lookup memory voltage gpios */ 1600fcb371a1SBen Skeggs ret = nvkm_gpio_find(device->gpio, 0, 0x18, DCB_GPIO_UNUSED, &gpio); 1601639c308eSBen Skeggs if (ret == 0) { 1602fcb371a1SBen Skeggs ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (gpio.line * 0x04)); 1603fcb371a1SBen Skeggs ram->fuc.r_funcMV[0] = (gpio.log[0] ^ 2) << 12; 1604fcb371a1SBen Skeggs ram->fuc.r_funcMV[1] = (gpio.log[1] ^ 2) << 12; 1605639c308eSBen Skeggs } 1606639c308eSBen Skeggs 1607fcb371a1SBen Skeggs ret = nvkm_gpio_find(device->gpio, 0, 0x2e, DCB_GPIO_UNUSED, &gpio); 1608639c308eSBen Skeggs if (ret == 0) { 1609fcb371a1SBen Skeggs ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (gpio.line * 0x04)); 1610fcb371a1SBen Skeggs ram->fuc.r_func2E[0] = (gpio.log[0] ^ 2) << 12; 1611fcb371a1SBen Skeggs ram->fuc.r_func2E[1] = (gpio.log[1] ^ 2) << 12; 1612639c308eSBen Skeggs } 1613639c308eSBen Skeggs 1614639c308eSBen Skeggs ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604); 1615639c308eSBen Skeggs 1616639c308eSBen Skeggs ram->fuc.r_0x132020 = ramfuc_reg(0x132020); 1617639c308eSBen Skeggs ram->fuc.r_0x132028 = ramfuc_reg(0x132028); 1618639c308eSBen Skeggs ram->fuc.r_0x132024 = ramfuc_reg(0x132024); 1619639c308eSBen Skeggs ram->fuc.r_0x132030 = ramfuc_reg(0x132030); 1620639c308eSBen Skeggs ram->fuc.r_0x132034 = ramfuc_reg(0x132034); 1621639c308eSBen Skeggs ram->fuc.r_0x132000 = ramfuc_reg(0x132000); 1622639c308eSBen Skeggs ram->fuc.r_0x132004 = ramfuc_reg(0x132004); 1623639c308eSBen Skeggs ram->fuc.r_0x132040 = ramfuc_reg(0x132040); 1624639c308eSBen Skeggs 1625639c308eSBen Skeggs ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248); 1626639c308eSBen Skeggs ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290); 1627639c308eSBen Skeggs ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294); 1628639c308eSBen Skeggs ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298); 1629639c308eSBen Skeggs ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c); 1630639c308eSBen Skeggs ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0); 1631639c308eSBen Skeggs ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4); 1632639c308eSBen Skeggs ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8); 1633639c308eSBen Skeggs ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac); 1634639c308eSBen Skeggs ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc); 1635639c308eSBen Skeggs ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8); 1636639c308eSBen Skeggs ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250); 1637639c308eSBen Skeggs ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c); 1638639c308eSBen Skeggs ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4); 1639639c308eSBen Skeggs ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8); 1640639c308eSBen Skeggs ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604); 1641639c308eSBen Skeggs ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614); 1642639c308eSBen Skeggs ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610); 1643639c308eSBen Skeggs ram->fuc.r_0x100770 = ramfuc_reg(0x100770); 1644639c308eSBen Skeggs ram->fuc.r_0x100778 = ramfuc_reg(0x100778); 1645639c308eSBen Skeggs ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224); 1646639c308eSBen Skeggs 1647639c308eSBen Skeggs ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870); 1648639c308eSBen Skeggs ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698); 1649639c308eSBen Skeggs ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694); 1650639c308eSBen Skeggs ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8); 1651639c308eSBen Skeggs ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808); 1652639c308eSBen Skeggs ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670); 1653639c308eSBen Skeggs ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c); 1654639c308eSBen Skeggs ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830); 1655639c308eSBen Skeggs ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec); 1656639c308eSBen Skeggs ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800); 1657639c308eSBen Skeggs ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c); 1658639c308eSBen Skeggs 1659639c308eSBen Skeggs ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978); 1660639c308eSBen Skeggs ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910); 1661639c308eSBen Skeggs ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); 1662639c308eSBen Skeggs 1663639c308eSBen Skeggs switch (ram->base.type) { 1664d36a99d2SBen Skeggs case NVKM_RAM_TYPE_GDDR5: 1665639c308eSBen Skeggs ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); 1666639c308eSBen Skeggs ram->fuc.r_mr[1] = ramfuc_reg(0x10f330); 1667639c308eSBen Skeggs ram->fuc.r_mr[2] = ramfuc_reg(0x10f334); 1668639c308eSBen Skeggs ram->fuc.r_mr[3] = ramfuc_reg(0x10f338); 1669639c308eSBen Skeggs ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c); 1670639c308eSBen Skeggs ram->fuc.r_mr[5] = ramfuc_reg(0x10f340); 1671639c308eSBen Skeggs ram->fuc.r_mr[6] = ramfuc_reg(0x10f344); 1672639c308eSBen Skeggs ram->fuc.r_mr[7] = ramfuc_reg(0x10f348); 1673639c308eSBen Skeggs ram->fuc.r_mr[8] = ramfuc_reg(0x10f354); 1674639c308eSBen Skeggs ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c); 1675639c308eSBen Skeggs break; 1676d36a99d2SBen Skeggs case NVKM_RAM_TYPE_DDR3: 1677639c308eSBen Skeggs ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); 1678b4f2bf33SRoy Spliet ram->fuc.r_mr[1] = ramfuc_reg(0x10f304); 1679639c308eSBen Skeggs ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); 1680639c308eSBen Skeggs break; 1681639c308eSBen Skeggs default: 1682639c308eSBen Skeggs break; 1683639c308eSBen Skeggs } 1684639c308eSBen Skeggs 1685639c308eSBen Skeggs ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000); 1686639c308eSBen Skeggs ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200); 1687639c308eSBen Skeggs ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210); 1688639c308eSBen Skeggs ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310); 1689639c308eSBen Skeggs ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314); 1690639c308eSBen Skeggs ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318); 1691639c308eSBen Skeggs ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090); 1692639c308eSBen Skeggs ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c); 1693639c308eSBen Skeggs ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824); 1694639c308eSBen Skeggs ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0); 1695639c308eSBen Skeggs ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4); 1696639c308eSBen Skeggs ram->fuc.r_0x137320 = ramfuc_reg(0x137320); 1697639c308eSBen Skeggs ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); 1698639c308eSBen Skeggs ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); 1699639c308eSBen Skeggs ram->fuc.r_0x100710 = ramfuc_reg(0x100710); 1700639c308eSBen Skeggs ram->fuc.r_0x100750 = ramfuc_reg(0x100750); 1701639c308eSBen Skeggs return 0; 1702639c308eSBen Skeggs } 1703fcb371a1SBen Skeggs 1704fcb371a1SBen Skeggs static const struct nvkm_ram_func 1705fcb371a1SBen Skeggs gk104_ram = { 1706fcb371a1SBen Skeggs .dtor = gk104_ram_dtor, 1707fcb371a1SBen Skeggs .init = gk104_ram_init, 1708fcb371a1SBen Skeggs .get = gf100_ram_get, 1709fcb371a1SBen Skeggs .put = gf100_ram_put, 1710fcb371a1SBen Skeggs .calc = gk104_ram_calc, 1711fcb371a1SBen Skeggs .prog = gk104_ram_prog, 1712fcb371a1SBen Skeggs .tidy = gk104_ram_tidy, 1713fcb371a1SBen Skeggs }; 1714fcb371a1SBen Skeggs 1715fcb371a1SBen Skeggs int 1716fcb371a1SBen Skeggs gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) 1717fcb371a1SBen Skeggs { 1718fcb371a1SBen Skeggs return gk104_ram_new_(&gk104_ram, fb, pram, 0x022554); 1719fcb371a1SBen Skeggs } 1720