1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv50.h"
25 
26 #include <core/client.h>
27 #include <core/engctx.h>
28 #include <core/enum.h>
29 
30 int
31 nv50_fb_memtype[0x80] = {
32 	1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
33 	1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
34 	1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
35 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
36 	1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
37 	0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
38 	1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
39 	1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
40 };
41 
42 bool
43 nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype)
44 {
45 	return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
46 }
47 
48 static const struct nvkm_enum vm_dispatch_subclients[] = {
49 	{ 0x00000000, "GRCTX", NULL },
50 	{ 0x00000001, "NOTIFY", NULL },
51 	{ 0x00000002, "QUERY", NULL },
52 	{ 0x00000003, "COND", NULL },
53 	{ 0x00000004, "M2M_IN", NULL },
54 	{ 0x00000005, "M2M_OUT", NULL },
55 	{ 0x00000006, "M2M_NOTIFY", NULL },
56 	{}
57 };
58 
59 static const struct nvkm_enum vm_ccache_subclients[] = {
60 	{ 0x00000000, "CB", NULL },
61 	{ 0x00000001, "TIC", NULL },
62 	{ 0x00000002, "TSC", NULL },
63 	{}
64 };
65 
66 static const struct nvkm_enum vm_prop_subclients[] = {
67 	{ 0x00000000, "RT0", NULL },
68 	{ 0x00000001, "RT1", NULL },
69 	{ 0x00000002, "RT2", NULL },
70 	{ 0x00000003, "RT3", NULL },
71 	{ 0x00000004, "RT4", NULL },
72 	{ 0x00000005, "RT5", NULL },
73 	{ 0x00000006, "RT6", NULL },
74 	{ 0x00000007, "RT7", NULL },
75 	{ 0x00000008, "ZETA", NULL },
76 	{ 0x00000009, "LOCAL", NULL },
77 	{ 0x0000000a, "GLOBAL", NULL },
78 	{ 0x0000000b, "STACK", NULL },
79 	{ 0x0000000c, "DST2D", NULL },
80 	{}
81 };
82 
83 static const struct nvkm_enum vm_pfifo_subclients[] = {
84 	{ 0x00000000, "PUSHBUF", NULL },
85 	{ 0x00000001, "SEMAPHORE", NULL },
86 	{}
87 };
88 
89 static const struct nvkm_enum vm_bar_subclients[] = {
90 	{ 0x00000000, "FB", NULL },
91 	{ 0x00000001, "IN", NULL },
92 	{}
93 };
94 
95 static const struct nvkm_enum vm_client[] = {
96 	{ 0x00000000, "STRMOUT", NULL },
97 	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
98 	{ 0x00000004, "PFIFO_WRITE", NULL },
99 	{ 0x00000005, "CCACHE", vm_ccache_subclients },
100 	{ 0x00000006, "PMSPPP", NULL },
101 	{ 0x00000007, "CLIPID", NULL },
102 	{ 0x00000008, "PFIFO_READ", NULL },
103 	{ 0x00000009, "VFETCH", NULL },
104 	{ 0x0000000a, "TEXTURE", NULL },
105 	{ 0x0000000b, "PROP", vm_prop_subclients },
106 	{ 0x0000000c, "PVP", NULL },
107 	{ 0x0000000d, "PBSP", NULL },
108 	{ 0x0000000e, "PCRYPT", NULL },
109 	{ 0x0000000f, "PCOUNTER", NULL },
110 	{ 0x00000011, "PDAEMON", NULL },
111 	{}
112 };
113 
114 static const struct nvkm_enum vm_engine[] = {
115 	{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
116 	{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
117 	{ 0x00000004, "PEEPHOLE", NULL },
118 	{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
119 	{ 0x00000006, "BAR", vm_bar_subclients },
120 	{ 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
121 	{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
122 	{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
123 	{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
124 	{ 0x0000000b, "PCOUNTER", NULL },
125 	{ 0x0000000c, "SEMAPHORE_BG", NULL },
126 	{ 0x0000000d, "PCE0", NULL, NVDEV_ENGINE_CE0 },
127 	{ 0x0000000e, "PDAEMON", NULL },
128 	{}
129 };
130 
131 static const struct nvkm_enum vm_fault[] = {
132 	{ 0x00000000, "PT_NOT_PRESENT", NULL },
133 	{ 0x00000001, "PT_TOO_SHORT", NULL },
134 	{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
135 	{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
136 	{ 0x00000004, "PAGE_READ_ONLY", NULL },
137 	{ 0x00000006, "NULL_DMAOBJ", NULL },
138 	{ 0x00000007, "WRONG_MEMTYPE", NULL },
139 	{ 0x0000000b, "VRAM_LIMIT", NULL },
140 	{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
141 	{}
142 };
143 
144 static void
145 nv50_fb_intr(struct nvkm_subdev *subdev)
146 {
147 	struct nvkm_device *device = nv_device(subdev);
148 	struct nvkm_engine *engine;
149 	struct nv50_fb *fb = (void *)subdev;
150 	const struct nvkm_enum *en, *cl;
151 	struct nvkm_object *engctx = NULL;
152 	u32 trap[6], idx, chan;
153 	u8 st0, st1, st2, st3;
154 	int i;
155 
156 	idx = nv_rd32(fb, 0x100c90);
157 	if (!(idx & 0x80000000))
158 		return;
159 	idx &= 0x00ffffff;
160 
161 	for (i = 0; i < 6; i++) {
162 		nv_wr32(fb, 0x100c90, idx | i << 24);
163 		trap[i] = nv_rd32(fb, 0x100c94);
164 	}
165 	nv_wr32(fb, 0x100c90, idx | 0x80000000);
166 
167 	/* decode status bits into something more useful */
168 	if (device->chipset  < 0xa3 ||
169 	    device->chipset == 0xaa || device->chipset == 0xac) {
170 		st0 = (trap[0] & 0x0000000f) >> 0;
171 		st1 = (trap[0] & 0x000000f0) >> 4;
172 		st2 = (trap[0] & 0x00000f00) >> 8;
173 		st3 = (trap[0] & 0x0000f000) >> 12;
174 	} else {
175 		st0 = (trap[0] & 0x000000ff) >> 0;
176 		st1 = (trap[0] & 0x0000ff00) >> 8;
177 		st2 = (trap[0] & 0x00ff0000) >> 16;
178 		st3 = (trap[0] & 0xff000000) >> 24;
179 	}
180 	chan = (trap[2] << 16) | trap[1];
181 
182 	en = nvkm_enum_find(vm_engine, st0);
183 
184 	if (en && en->data2) {
185 		const struct nvkm_enum *orig_en = en;
186 		while (en->name && en->value == st0 && en->data2) {
187 			engine = nvkm_engine(subdev, en->data2);
188 			/*XXX: clean this up */
189 			if (!engine && en->data2 == NVDEV_ENGINE_BSP)
190 				engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD);
191 			if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
192 				engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC);
193 			if (!engine && en->data2 == NVDEV_ENGINE_VP)
194 				engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC);
195 			if (engine) {
196 				engctx = nvkm_engctx_get(engine, chan);
197 				if (engctx)
198 					break;
199 			}
200 			en++;
201 		}
202 		if (!engctx)
203 			en = orig_en;
204 	}
205 
206 	nv_error(fb, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
207 		 (trap[5] & 0x00000100) ? "read" : "write",
208 		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
209 		 nvkm_client_name(engctx));
210 
211 	nvkm_engctx_put(engctx);
212 
213 	if (en)
214 		pr_cont("%s/", en->name);
215 	else
216 		pr_cont("%02x/", st0);
217 
218 	cl = nvkm_enum_find(vm_client, st2);
219 	if (cl)
220 		pr_cont("%s/", cl->name);
221 	else
222 		pr_cont("%02x/", st2);
223 
224 	if      (cl && cl->data) cl = nvkm_enum_find(cl->data, st3);
225 	else if (en && en->data) cl = nvkm_enum_find(en->data, st3);
226 	else                     cl = NULL;
227 	if (cl)
228 		pr_cont("%s", cl->name);
229 	else
230 		pr_cont("%02x", st3);
231 
232 	pr_cont(" reason: ");
233 	en = nvkm_enum_find(vm_fault, st1);
234 	if (en)
235 		pr_cont("%s\n", en->name);
236 	else
237 		pr_cont("0x%08x\n", st1);
238 }
239 
240 int
241 nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
242 	     struct nvkm_oclass *oclass, void *data, u32 size,
243 	     struct nvkm_object **pobject)
244 {
245 	struct nvkm_device *device = nv_device(parent);
246 	struct nv50_fb *fb;
247 	int ret;
248 
249 	ret = nvkm_fb_create(parent, engine, oclass, &fb);
250 	*pobject = nv_object(fb);
251 	if (ret)
252 		return ret;
253 
254 	fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
255 	if (fb->r100c08_page) {
256 		fb->r100c08 = dma_map_page(nv_device_base(device),
257 					     fb->r100c08_page, 0, PAGE_SIZE,
258 					     DMA_BIDIRECTIONAL);
259 		if (dma_mapping_error(nv_device_base(device), fb->r100c08))
260 			return -EFAULT;
261 	} else {
262 		nv_warn(fb, "failed 0x100c08 page alloc\n");
263 	}
264 
265 	nv_subdev(fb)->intr = nv50_fb_intr;
266 	return 0;
267 }
268 
269 void
270 nv50_fb_dtor(struct nvkm_object *object)
271 {
272 	struct nvkm_device *device = nv_device(object);
273 	struct nv50_fb *fb = (void *)object;
274 
275 	if (fb->r100c08_page) {
276 		dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE,
277 			       DMA_BIDIRECTIONAL);
278 		__free_page(fb->r100c08_page);
279 	}
280 
281 	nvkm_fb_destroy(&fb->base);
282 }
283 
284 int
285 nv50_fb_init(struct nvkm_object *object)
286 {
287 	struct nv50_fb_impl *impl = (void *)object->oclass;
288 	struct nv50_fb *fb = (void *)object;
289 	int ret;
290 
291 	ret = nvkm_fb_init(&fb->base);
292 	if (ret)
293 		return ret;
294 
295 	/* Not a clue what this is exactly.  Without pointing it at a
296 	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
297 	 * cause IOMMU "read from address 0" errors (rh#561267)
298 	 */
299 	nv_wr32(fb, 0x100c08, fb->r100c08 >> 8);
300 
301 	/* This is needed to get meaningful information from 100c90
302 	 * on traps. No idea what these values mean exactly. */
303 	nv_wr32(fb, 0x100c90, impl->trap);
304 	return 0;
305 }
306 
307 struct nvkm_oclass *
308 nv50_fb_oclass = &(struct nv50_fb_impl) {
309 	.base.base.handle = NV_SUBDEV(FB, 0x50),
310 	.base.base.ofuncs = &(struct nvkm_ofuncs) {
311 		.ctor = nv50_fb_ctor,
312 		.dtor = nv50_fb_dtor,
313 		.init = nv50_fb_init,
314 		.fini = _nvkm_fb_fini,
315 	},
316 	.base.memtype = nv50_fb_memtype_valid,
317 	.base.ram = &nv50_ram_oclass,
318 	.trap = 0x000707ff,
319 }.base.base;
320