1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "ram.h" 26 27 #include <core/client.h> 28 #include <core/enum.h> 29 #include <engine/fifo.h> 30 31 int 32 nv50_fb_memtype[0x80] = { 33 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34 1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0, 35 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0, 36 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0, 38 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2, 40 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0 41 }; 42 43 bool 44 nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype) 45 { 46 return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0; 47 } 48 49 static const struct nvkm_enum vm_dispatch_subclients[] = { 50 { 0x00000000, "GRCTX" }, 51 { 0x00000001, "NOTIFY" }, 52 { 0x00000002, "QUERY" }, 53 { 0x00000003, "COND" }, 54 { 0x00000004, "M2M_IN" }, 55 { 0x00000005, "M2M_OUT" }, 56 { 0x00000006, "M2M_NOTIFY" }, 57 {} 58 }; 59 60 static const struct nvkm_enum vm_ccache_subclients[] = { 61 { 0x00000000, "CB" }, 62 { 0x00000001, "TIC" }, 63 { 0x00000002, "TSC" }, 64 {} 65 }; 66 67 static const struct nvkm_enum vm_prop_subclients[] = { 68 { 0x00000000, "RT0" }, 69 { 0x00000001, "RT1" }, 70 { 0x00000002, "RT2" }, 71 { 0x00000003, "RT3" }, 72 { 0x00000004, "RT4" }, 73 { 0x00000005, "RT5" }, 74 { 0x00000006, "RT6" }, 75 { 0x00000007, "RT7" }, 76 { 0x00000008, "ZETA" }, 77 { 0x00000009, "LOCAL" }, 78 { 0x0000000a, "GLOBAL" }, 79 { 0x0000000b, "STACK" }, 80 { 0x0000000c, "DST2D" }, 81 {} 82 }; 83 84 static const struct nvkm_enum vm_pfifo_subclients[] = { 85 { 0x00000000, "PUSHBUF" }, 86 { 0x00000001, "SEMAPHORE" }, 87 {} 88 }; 89 90 static const struct nvkm_enum vm_bar_subclients[] = { 91 { 0x00000000, "FB" }, 92 { 0x00000001, "IN" }, 93 {} 94 }; 95 96 static const struct nvkm_enum vm_client[] = { 97 { 0x00000000, "STRMOUT" }, 98 { 0x00000003, "DISPATCH", vm_dispatch_subclients }, 99 { 0x00000004, "PFIFO_WRITE" }, 100 { 0x00000005, "CCACHE", vm_ccache_subclients }, 101 { 0x00000006, "PMSPPP" }, 102 { 0x00000007, "CLIPID" }, 103 { 0x00000008, "PFIFO_READ" }, 104 { 0x00000009, "VFETCH" }, 105 { 0x0000000a, "TEXTURE" }, 106 { 0x0000000b, "PROP", vm_prop_subclients }, 107 { 0x0000000c, "PVP" }, 108 { 0x0000000d, "PBSP" }, 109 { 0x0000000e, "PCRYPT" }, 110 { 0x0000000f, "PCOUNTER" }, 111 { 0x00000011, "PDAEMON" }, 112 {} 113 }; 114 115 static const struct nvkm_enum vm_engine[] = { 116 { 0x00000000, "PGRAPH" }, 117 { 0x00000001, "PVP" }, 118 { 0x00000004, "PEEPHOLE" }, 119 { 0x00000005, "PFIFO", vm_pfifo_subclients }, 120 { 0x00000006, "BAR", vm_bar_subclients }, 121 { 0x00000008, "PMSPPP" }, 122 { 0x00000008, "PMPEG" }, 123 { 0x00000009, "PBSP" }, 124 { 0x0000000a, "PCRYPT" }, 125 { 0x0000000b, "PCOUNTER" }, 126 { 0x0000000c, "SEMAPHORE_BG" }, 127 { 0x0000000d, "PCE0" }, 128 { 0x0000000e, "PDAEMON" }, 129 {} 130 }; 131 132 static const struct nvkm_enum vm_fault[] = { 133 { 0x00000000, "PT_NOT_PRESENT" }, 134 { 0x00000001, "PT_TOO_SHORT" }, 135 { 0x00000002, "PAGE_NOT_PRESENT" }, 136 { 0x00000003, "PAGE_SYSTEM_ONLY" }, 137 { 0x00000004, "PAGE_READ_ONLY" }, 138 { 0x00000006, "NULL_DMAOBJ" }, 139 { 0x00000007, "WRONG_MEMTYPE" }, 140 { 0x0000000b, "VRAM_LIMIT" }, 141 { 0x0000000f, "DMAOBJ_LIMIT" }, 142 {} 143 }; 144 145 static void 146 nv50_fb_intr(struct nvkm_subdev *subdev) 147 { 148 struct nv50_fb *fb = (void *)subdev; 149 struct nvkm_device *device = fb->base.subdev.device; 150 struct nvkm_fifo *fifo = device->fifo; 151 struct nvkm_fifo_chan *chan; 152 const struct nvkm_enum *en, *re, *cl, *sc; 153 u32 trap[6], idx, inst; 154 u8 st0, st1, st2, st3; 155 unsigned long flags; 156 int i; 157 158 idx = nvkm_rd32(device, 0x100c90); 159 if (!(idx & 0x80000000)) 160 return; 161 idx &= 0x00ffffff; 162 163 for (i = 0; i < 6; i++) { 164 nvkm_wr32(device, 0x100c90, idx | i << 24); 165 trap[i] = nvkm_rd32(device, 0x100c94); 166 } 167 nvkm_wr32(device, 0x100c90, idx | 0x80000000); 168 169 /* decode status bits into something more useful */ 170 if (device->chipset < 0xa3 || 171 device->chipset == 0xaa || device->chipset == 0xac) { 172 st0 = (trap[0] & 0x0000000f) >> 0; 173 st1 = (trap[0] & 0x000000f0) >> 4; 174 st2 = (trap[0] & 0x00000f00) >> 8; 175 st3 = (trap[0] & 0x0000f000) >> 12; 176 } else { 177 st0 = (trap[0] & 0x000000ff) >> 0; 178 st1 = (trap[0] & 0x0000ff00) >> 8; 179 st2 = (trap[0] & 0x00ff0000) >> 16; 180 st3 = (trap[0] & 0xff000000) >> 24; 181 } 182 inst = ((trap[2] << 16) | trap[1]) << 12; 183 184 en = nvkm_enum_find(vm_engine, st0); 185 re = nvkm_enum_find(vm_fault , st1); 186 cl = nvkm_enum_find(vm_client, st2); 187 if (cl && cl->data) sc = nvkm_enum_find(cl->data, st3); 188 else if (en && en->data) sc = nvkm_enum_find(en->data, st3); 189 else sc = NULL; 190 191 chan = nvkm_fifo_chan_inst(fifo, inst, &flags); 192 nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel " 193 "%08x [%s] engine %02x [%s] client %02x [%s] " 194 "subclient %02x [%s] reason %08x [%s]\n", 195 (trap[5] & 0x00000100) ? "read" : "write", 196 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, inst, 197 nvkm_client_name(chan), st0, en ? en->name : "", 198 st2, cl ? cl->name : "", st3, sc ? sc->name : "", 199 st1, re ? re->name : ""); 200 nvkm_fifo_chan_put(fifo, flags, &chan); 201 } 202 203 int 204 nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 205 struct nvkm_oclass *oclass, void *data, u32 size, 206 struct nvkm_object **pobject) 207 { 208 struct nvkm_device *device = nv_device(parent); 209 struct nv50_fb *fb; 210 int ret; 211 212 ret = nvkm_fb_create(parent, engine, oclass, &fb); 213 *pobject = nv_object(fb); 214 if (ret) 215 return ret; 216 217 fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); 218 if (fb->r100c08_page) { 219 fb->r100c08 = dma_map_page(nv_device_base(device), 220 fb->r100c08_page, 0, PAGE_SIZE, 221 DMA_BIDIRECTIONAL); 222 if (dma_mapping_error(nv_device_base(device), fb->r100c08)) 223 return -EFAULT; 224 } else { 225 nvkm_warn(&fb->base.subdev, "failed 100c08 page alloc\n"); 226 } 227 228 nv_subdev(fb)->intr = nv50_fb_intr; 229 return 0; 230 } 231 232 void 233 nv50_fb_dtor(struct nvkm_object *object) 234 { 235 struct nvkm_device *device = nv_device(object); 236 struct nv50_fb *fb = (void *)object; 237 238 if (fb->r100c08_page) { 239 dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE, 240 DMA_BIDIRECTIONAL); 241 __free_page(fb->r100c08_page); 242 } 243 244 nvkm_fb_destroy(&fb->base); 245 } 246 247 int 248 nv50_fb_init(struct nvkm_object *object) 249 { 250 struct nv50_fb_impl *impl = (void *)object->oclass; 251 struct nv50_fb *fb = (void *)object; 252 struct nvkm_device *device = fb->base.subdev.device; 253 int ret; 254 255 ret = nvkm_fb_init(&fb->base); 256 if (ret) 257 return ret; 258 259 /* Not a clue what this is exactly. Without pointing it at a 260 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) 261 * cause IOMMU "read from address 0" errors (rh#561267) 262 */ 263 nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8); 264 265 /* This is needed to get meaningful information from 100c90 266 * on traps. No idea what these values mean exactly. */ 267 nvkm_wr32(device, 0x100c90, impl->trap); 268 return 0; 269 } 270 271 struct nvkm_oclass * 272 nv50_fb_oclass = &(struct nv50_fb_impl) { 273 .base.base.handle = NV_SUBDEV(FB, 0x50), 274 .base.base.ofuncs = &(struct nvkm_ofuncs) { 275 .ctor = nv50_fb_ctor, 276 .dtor = nv50_fb_dtor, 277 .init = nv50_fb_init, 278 .fini = _nvkm_fb_fini, 279 }, 280 .base.memtype = nv50_fb_memtype_valid, 281 .base.ram_new = nv50_ram_new, 282 .trap = 0x000707ff, 283 }.base.base; 284