1 /* 2 * Copyright (C) 2010 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #include "nv04.h" 28 29 void 30 nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, 31 u32 flags, struct nouveau_fb_tile *tile) 32 { 33 /* for performance, select alternate bank offset for zeta */ 34 if (!(flags & 4)) { 35 tile->addr = (0 << 4); 36 } else { 37 if (pfb->tile.comp) /* z compression */ 38 pfb->tile.comp(pfb, i, size, flags, tile); 39 tile->addr = (1 << 4); 40 } 41 42 tile->addr |= 0x00000001; /* enable */ 43 tile->addr |= addr; 44 tile->limit = max(1u, addr + size) - 1; 45 tile->pitch = pitch; 46 } 47 48 static void 49 nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, 50 struct nouveau_fb_tile *tile) 51 { 52 u32 tiles = DIV_ROUND_UP(size, 0x40); 53 u32 tags = round_up(tiles / pfb->ram->parts, 0x40); 54 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { 55 if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ 56 else tile->zcomp |= 0x02000000; /* Z24S8 */ 57 tile->zcomp |= ((tile->tag->offset ) >> 6); 58 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12; 59 #ifdef __BIG_ENDIAN 60 tile->zcomp |= 0x10000000; 61 #endif 62 } 63 } 64 65 static int 66 calc_bias(struct nv04_fb_priv *priv, int k, int i, int j) 67 { 68 struct nouveau_device *device = nv_device(priv); 69 int b = (device->chipset > 0x30 ? 70 nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : 71 0) & 0xf; 72 73 return 2 * (b & 0x8 ? b - 0x10 : b); 74 } 75 76 static int 77 calc_ref(struct nv04_fb_priv *priv, int l, int k, int i) 78 { 79 int j, x = 0; 80 81 for (j = 0; j < 4; j++) { 82 int m = (l >> (8 * i) & 0xff) + calc_bias(priv, k, i, j); 83 84 x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j); 85 } 86 87 return x; 88 } 89 90 int 91 nv30_fb_init(struct nouveau_object *object) 92 { 93 struct nouveau_device *device = nv_device(object); 94 struct nv04_fb_priv *priv = (void *)object; 95 int ret, i, j; 96 97 ret = nouveau_fb_init(&priv->base); 98 if (ret) 99 return ret; 100 101 /* Init the memory timing regs at 0x10037c/0x1003ac */ 102 if (device->chipset == 0x30 || 103 device->chipset == 0x31 || 104 device->chipset == 0x35) { 105 /* Related to ROP count */ 106 int n = (device->chipset == 0x31 ? 2 : 4); 107 int l = nv_rd32(priv, 0x1003d0); 108 109 for (i = 0; i < n; i++) { 110 for (j = 0; j < 3; j++) 111 nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j, 112 calc_ref(priv, l, 0, j)); 113 114 for (j = 0; j < 2; j++) 115 nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j, 116 calc_ref(priv, l, 1, j)); 117 } 118 } 119 120 return 0; 121 } 122 123 struct nouveau_oclass * 124 nv30_fb_oclass = &(struct nv04_fb_impl) { 125 .base.base.handle = NV_SUBDEV(FB, 0x30), 126 .base.base.ofuncs = &(struct nouveau_ofuncs) { 127 .ctor = nv04_fb_ctor, 128 .dtor = _nouveau_fb_dtor, 129 .init = nv30_fb_init, 130 .fini = _nouveau_fb_fini, 131 }, 132 .base.memtype = nv04_fb_memtype_valid, 133 .base.ram = &nv20_ram_oclass, 134 .tile.regions = 8, 135 .tile.init = nv30_fb_tile_init, 136 .tile.comp = nv30_fb_tile_comp, 137 .tile.fini = nv20_fb_tile_fini, 138 .tile.prog = nv20_fb_tile_prog, 139 }.base.base; 140