1c39f472eSBen Skeggs /* 2c39f472eSBen Skeggs * Copyright (C) 2010 Francisco Jerez. 3c39f472eSBen Skeggs * All Rights Reserved. 4c39f472eSBen Skeggs * 5c39f472eSBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining 6c39f472eSBen Skeggs * a copy of this software and associated documentation files (the 7c39f472eSBen Skeggs * "Software"), to deal in the Software without restriction, including 8c39f472eSBen Skeggs * without limitation the rights to use, copy, modify, merge, publish, 9c39f472eSBen Skeggs * distribute, sublicense, and/or sell copies of the Software, and to 10c39f472eSBen Skeggs * permit persons to whom the Software is furnished to do so, subject to 11c39f472eSBen Skeggs * the following conditions: 12c39f472eSBen Skeggs * 13c39f472eSBen Skeggs * The above copyright notice and this permission notice (including the 14c39f472eSBen Skeggs * next paragraph) shall be included in all copies or substantial 15c39f472eSBen Skeggs * portions of the Software. 16c39f472eSBen Skeggs * 17c39f472eSBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18c39f472eSBen Skeggs * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c39f472eSBen Skeggs * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20c39f472eSBen Skeggs * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21c39f472eSBen Skeggs * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22c39f472eSBen Skeggs * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23c39f472eSBen Skeggs * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c39f472eSBen Skeggs * 25c39f472eSBen Skeggs */ 26c39f472eSBen Skeggs #include "nv04.h" 27d36a99d2SBen Skeggs #include "ram.h" 28c39f472eSBen Skeggs 29c39f472eSBen Skeggs void 30b1e4553cSBen Skeggs nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, 31639c308eSBen Skeggs u32 flags, struct nvkm_fb_tile *tile) 32c39f472eSBen Skeggs { 33c39f472eSBen Skeggs /* for performance, select alternate bank offset for zeta */ 34c39f472eSBen Skeggs if (!(flags & 4)) { 35c39f472eSBen Skeggs tile->addr = (0 << 4); 36c39f472eSBen Skeggs } else { 37b1e4553cSBen Skeggs if (fb->tile.comp) /* z compression */ 38b1e4553cSBen Skeggs fb->tile.comp(fb, i, size, flags, tile); 39c39f472eSBen Skeggs tile->addr = (1 << 4); 40c39f472eSBen Skeggs } 41c39f472eSBen Skeggs 42c39f472eSBen Skeggs tile->addr |= 0x00000001; /* enable */ 43c39f472eSBen Skeggs tile->addr |= addr; 44c39f472eSBen Skeggs tile->limit = max(1u, addr + size) - 1; 45c39f472eSBen Skeggs tile->pitch = pitch; 46c39f472eSBen Skeggs } 47c39f472eSBen Skeggs 48c39f472eSBen Skeggs static void 49b1e4553cSBen Skeggs nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, 50639c308eSBen Skeggs struct nvkm_fb_tile *tile) 51c39f472eSBen Skeggs { 52c39f472eSBen Skeggs u32 tiles = DIV_ROUND_UP(size, 0x40); 53b1e4553cSBen Skeggs u32 tags = round_up(tiles / fb->ram->parts, 0x40); 54d36a99d2SBen Skeggs if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { 55c39f472eSBen Skeggs if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ 56c39f472eSBen Skeggs else tile->zcomp |= 0x02000000; /* Z24S8 */ 57c39f472eSBen Skeggs tile->zcomp |= ((tile->tag->offset ) >> 6); 58c39f472eSBen Skeggs tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12; 59c39f472eSBen Skeggs #ifdef __BIG_ENDIAN 60c39f472eSBen Skeggs tile->zcomp |= 0x10000000; 61c39f472eSBen Skeggs #endif 62c39f472eSBen Skeggs } 63c39f472eSBen Skeggs } 64c39f472eSBen Skeggs 65c39f472eSBen Skeggs static int 66b1e4553cSBen Skeggs calc_bias(struct nvkm_fb *fb, int k, int i, int j) 67c39f472eSBen Skeggs { 68b1e4553cSBen Skeggs struct nvkm_device *device = nv_device(fb); 69c39f472eSBen Skeggs int b = (device->chipset > 0x30 ? 706758745bSBen Skeggs nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >> 716758745bSBen Skeggs (4 * (i ^ 1)) : 72c39f472eSBen Skeggs 0) & 0xf; 73c39f472eSBen Skeggs 74c39f472eSBen Skeggs return 2 * (b & 0x8 ? b - 0x10 : b); 75c39f472eSBen Skeggs } 76c39f472eSBen Skeggs 77c39f472eSBen Skeggs static int 78b1e4553cSBen Skeggs calc_ref(struct nvkm_fb *fb, int l, int k, int i) 79c39f472eSBen Skeggs { 80c39f472eSBen Skeggs int j, x = 0; 81c39f472eSBen Skeggs 82c39f472eSBen Skeggs for (j = 0; j < 4; j++) { 83b1e4553cSBen Skeggs int m = (l >> (8 * i) & 0xff) + calc_bias(fb, k, i, j); 84c39f472eSBen Skeggs 85c39f472eSBen Skeggs x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j); 86c39f472eSBen Skeggs } 87c39f472eSBen Skeggs 88c39f472eSBen Skeggs return x; 89c39f472eSBen Skeggs } 90c39f472eSBen Skeggs 91c39f472eSBen Skeggs int 92639c308eSBen Skeggs nv30_fb_init(struct nvkm_object *object) 93c39f472eSBen Skeggs { 94639c308eSBen Skeggs struct nvkm_device *device = nv_device(object); 95b1e4553cSBen Skeggs struct nvkm_fb *fb = (void *)object; 96c39f472eSBen Skeggs int ret, i, j; 97c39f472eSBen Skeggs 98b1e4553cSBen Skeggs ret = nvkm_fb_init(fb); 99c39f472eSBen Skeggs if (ret) 100c39f472eSBen Skeggs return ret; 101c39f472eSBen Skeggs 102c39f472eSBen Skeggs /* Init the memory timing regs at 0x10037c/0x1003ac */ 103c39f472eSBen Skeggs if (device->chipset == 0x30 || 104c39f472eSBen Skeggs device->chipset == 0x31 || 105c39f472eSBen Skeggs device->chipset == 0x35) { 106c39f472eSBen Skeggs /* Related to ROP count */ 107c39f472eSBen Skeggs int n = (device->chipset == 0x31 ? 2 : 4); 1086758745bSBen Skeggs int l = nvkm_rd32(device, 0x1003d0); 109c39f472eSBen Skeggs 110c39f472eSBen Skeggs for (i = 0; i < n; i++) { 111c39f472eSBen Skeggs for (j = 0; j < 3; j++) 1126758745bSBen Skeggs nvkm_wr32(device, 0x10037c + 0xc * i + 0x4 * j, 113b1e4553cSBen Skeggs calc_ref(fb, l, 0, j)); 114c39f472eSBen Skeggs 115c39f472eSBen Skeggs for (j = 0; j < 2; j++) 1166758745bSBen Skeggs nvkm_wr32(device, 0x1003ac + 0x8 * i + 0x4 * j, 117b1e4553cSBen Skeggs calc_ref(fb, l, 1, j)); 118c39f472eSBen Skeggs } 119c39f472eSBen Skeggs } 120c39f472eSBen Skeggs 121c39f472eSBen Skeggs return 0; 122c39f472eSBen Skeggs } 123c39f472eSBen Skeggs 124639c308eSBen Skeggs struct nvkm_oclass * 125c39f472eSBen Skeggs nv30_fb_oclass = &(struct nv04_fb_impl) { 126c39f472eSBen Skeggs .base.base.handle = NV_SUBDEV(FB, 0x30), 127639c308eSBen Skeggs .base.base.ofuncs = &(struct nvkm_ofuncs) { 128c39f472eSBen Skeggs .ctor = nv04_fb_ctor, 129639c308eSBen Skeggs .dtor = _nvkm_fb_dtor, 130c39f472eSBen Skeggs .init = nv30_fb_init, 131639c308eSBen Skeggs .fini = _nvkm_fb_fini, 132c39f472eSBen Skeggs }, 133c39f472eSBen Skeggs .base.memtype = nv04_fb_memtype_valid, 134d36a99d2SBen Skeggs .base.ram_new = nv20_ram_new, 135c39f472eSBen Skeggs .tile.regions = 8, 136c39f472eSBen Skeggs .tile.init = nv30_fb_tile_init, 137c39f472eSBen Skeggs .tile.comp = nv30_fb_tile_comp, 138c39f472eSBen Skeggs .tile.fini = nv20_fb_tile_fini, 139c39f472eSBen Skeggs .tile.prog = nv20_fb_tile_prog, 140c39f472eSBen Skeggs }.base.base; 141