1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <subdev/bios.h> 27 #include <subdev/bios/dcb.h> 28 #include <subdev/bios/disp.h> 29 #include <subdev/bios/init.h> 30 #include <subdev/bios/pll.h> 31 #include <subdev/clk/pll.h> 32 #include <subdev/ibus.h> 33 #include <subdev/vga.h> 34 35 int 36 nv50_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) 37 { 38 struct nvkm_subdev *subdev = &init->subdev; 39 struct nvkm_device *device = subdev->device; 40 struct nvkm_bios *bios = device->bios; 41 struct nvbios_pll info; 42 int N1, M1, N2, M2, P; 43 int ret; 44 45 ret = nvbios_pll_parse(bios, type, &info); 46 if (ret) { 47 nv_error(subdev, "failed to retrieve pll data, %d\n", ret); 48 return ret; 49 } 50 51 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); 52 if (!ret) { 53 nv_error(subdev, "failed pll calculation\n"); 54 return ret; 55 } 56 57 switch (info.type) { 58 case PLL_VPLL0: 59 case PLL_VPLL1: 60 nvkm_wr32(device, info.reg + 0, 0x10000611); 61 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); 62 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) | 63 (M2 << 16) | N2); 64 break; 65 case PLL_MEMORY: 66 nvkm_mask(device, info.reg + 0, 0x01ff0000, 67 (P << 22) | 68 (info.bias_p << 19) | 69 (P << 16)); 70 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); 71 break; 72 default: 73 nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16)); 74 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); 75 break; 76 } 77 78 return 0; 79 } 80 81 static u64 82 nv50_devinit_disable(struct nvkm_devinit *init) 83 { 84 struct nvkm_device *device = init->subdev.device; 85 u32 r001540 = nvkm_rd32(device, 0x001540); 86 u64 disable = 0ULL; 87 88 if (!(r001540 & 0x40000000)) 89 disable |= (1ULL << NVDEV_ENGINE_MPEG); 90 91 return disable; 92 } 93 94 int 95 nv50_devinit_init(struct nvkm_object *object) 96 { 97 struct nvkm_bios *bios = nvkm_bios(object); 98 struct nvkm_ibus *ibus = nvkm_ibus(object); 99 struct nv50_devinit *init = (void *)object; 100 struct nvbios_outp info; 101 struct dcb_output outp; 102 u8 ver = 0xff, hdr, cnt, len; 103 int ret, i = 0; 104 105 if (!init->base.post) { 106 if (!nv_rdvgac(init, 0, 0x00) && 107 !nv_rdvgac(init, 0, 0x1a)) { 108 nv_info(init, "adaptor not initialised\n"); 109 init->base.post = true; 110 } 111 } 112 113 /* some boards appear to require certain init register timeouts 114 * to be bumped before runing devinit scripts. not a clue why 115 * the vbios engineers didn't make the scripts just work... 116 */ 117 if (init->base.post && ibus) 118 nv_ofuncs(ibus)->init(nv_object(ibus)); 119 120 ret = nvkm_devinit_init(&init->base); 121 if (ret) 122 return ret; 123 124 /* if we ran the init tables, we have to execute the first script 125 * pointer of each dcb entry's display encoder table in order 126 * to properly initialise each encoder. 127 */ 128 while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { 129 if (nvbios_outp_match(bios, outp.hasht, outp.hashm, 130 &ver, &hdr, &cnt, &len, &info)) { 131 struct nvbios_init exec = { 132 .subdev = nv_subdev(init), 133 .bios = bios, 134 .offset = info.script[0], 135 .outp = &outp, 136 .crtc = -1, 137 .execute = 1, 138 }; 139 140 nvbios_exec(&exec); 141 } 142 i++; 143 } 144 145 return 0; 146 } 147 148 int 149 nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 150 struct nvkm_oclass *oclass, void *data, u32 size, 151 struct nvkm_object **pobject) 152 { 153 struct nv50_devinit *init; 154 int ret; 155 156 ret = nvkm_devinit_create(parent, engine, oclass, &init); 157 *pobject = nv_object(init); 158 if (ret) 159 return ret; 160 161 return 0; 162 } 163 164 struct nvkm_oclass * 165 nv50_devinit_oclass = &(struct nvkm_devinit_impl) { 166 .base.handle = NV_SUBDEV(DEVINIT, 0x50), 167 .base.ofuncs = &(struct nvkm_ofuncs) { 168 .ctor = nv50_devinit_ctor, 169 .dtor = _nvkm_devinit_dtor, 170 .init = nv50_devinit_init, 171 .fini = _nvkm_devinit_fini, 172 }, 173 .pll_set = nv50_devinit_pll_set, 174 .disable = nv50_devinit_disable, 175 .post = nvbios_init, 176 }.base; 177