1 /* 2 * Copyright (C) 2010 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 #include "nv04.h" 27 #include "fbmem.h" 28 29 #include <subdev/bios.h> 30 #include <subdev/bios/init.h> 31 #include <subdev/bios/pll.h> 32 #include <subdev/clk/pll.h> 33 #include <subdev/vga.h> 34 35 static void 36 nv04_devinit_meminit(struct nvkm_devinit *init) 37 { 38 struct nvkm_device *device = init->subdev.device; 39 u32 patt = 0xdeadbeef; 40 struct io_mapping *fb; 41 int i; 42 43 /* Map the framebuffer aperture */ 44 fb = fbmem_init(device); 45 if (!fb) { 46 nv_error(init, "failed to map fb\n"); 47 return; 48 } 49 50 /* Sequencer and refresh off */ 51 nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) | 0x20); 52 nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 53 54 nvkm_mask(device, NV04_PFB_BOOT_0, ~0, 55 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 56 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 57 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 58 59 for (i = 0; i < 4; i++) 60 fbmem_poke(fb, 4 * i, patt); 61 62 fbmem_poke(fb, 0x400000, patt + 1); 63 64 if (fbmem_peek(fb, 0) == patt + 1) { 65 nvkm_mask(device, NV04_PFB_BOOT_0, 66 NV04_PFB_BOOT_0_RAM_TYPE, 67 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 68 nvkm_mask(device, NV04_PFB_DEBUG_0, 69 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 70 71 for (i = 0; i < 4; i++) 72 fbmem_poke(fb, 4 * i, patt); 73 74 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff)) 75 nvkm_mask(device, NV04_PFB_BOOT_0, 76 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 77 NV04_PFB_BOOT_0_RAM_AMOUNT, 78 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 79 } else 80 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) { 81 nvkm_mask(device, NV04_PFB_BOOT_0, 82 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 83 NV04_PFB_BOOT_0_RAM_AMOUNT, 84 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 85 } else 86 if (fbmem_peek(fb, 0) != patt) { 87 if (fbmem_readback(fb, 0x800000, patt)) 88 nvkm_mask(device, NV04_PFB_BOOT_0, 89 NV04_PFB_BOOT_0_RAM_AMOUNT, 90 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 91 else 92 nvkm_mask(device, NV04_PFB_BOOT_0, 93 NV04_PFB_BOOT_0_RAM_AMOUNT, 94 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 95 96 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 97 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 98 } else 99 if (!fbmem_readback(fb, 0x800000, patt)) { 100 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 101 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 102 103 } 104 105 /* Refresh on, sequencer on */ 106 nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 107 nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) & ~0x20); 108 fbmem_fini(fb); 109 } 110 111 static int 112 powerctrl_1_shift(int chip_version, int reg) 113 { 114 int shift = -4; 115 116 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20) 117 return shift; 118 119 switch (reg) { 120 case 0x680520: 121 shift += 4; 122 case 0x680508: 123 shift += 4; 124 case 0x680504: 125 shift += 4; 126 case 0x680500: 127 shift += 4; 128 } 129 130 /* 131 * the shift for vpll regs is only used for nv3x chips with a single 132 * stage pll 133 */ 134 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 || 135 chip_version == 0x36 || chip_version >= 0x40)) 136 shift = -4; 137 138 return shift; 139 } 140 141 void 142 setPLL_single(struct nvkm_devinit *init, u32 reg, 143 struct nvkm_pll_vals *pv) 144 { 145 struct nvkm_device *device = init->subdev.device; 146 int chip_version = device->bios->version.chip; 147 uint32_t oldpll = nvkm_rd32(device, reg); 148 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; 149 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; 150 uint32_t saved_powerctrl_1 = 0; 151 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); 152 153 if (oldpll == pll) 154 return; /* already set */ 155 156 if (shift_powerctrl_1 >= 0) { 157 saved_powerctrl_1 = nvkm_rd32(device, 0x001584); 158 nvkm_wr32(device, 0x001584, 159 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 160 1 << shift_powerctrl_1); 161 } 162 163 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) 164 /* upclock -- write new post divider first */ 165 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); 166 else 167 /* downclock -- write new NM first */ 168 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); 169 170 if ((chip_version < 0x17 || chip_version == 0x1a) && 171 chip_version != 0x11) 172 /* wait a bit on older chips */ 173 msleep(64); 174 nvkm_rd32(device, reg); 175 176 /* then write the other half as well */ 177 nvkm_wr32(device, reg, pll); 178 179 if (shift_powerctrl_1 >= 0) 180 nvkm_wr32(device, 0x001584, saved_powerctrl_1); 181 } 182 183 static uint32_t 184 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) 185 { 186 bool head_a = (reg1 == 0x680508); 187 188 if (ss) /* single stage pll mode */ 189 ramdac580 |= head_a ? 0x00000100 : 0x10000000; 190 else 191 ramdac580 &= head_a ? 0xfffffeff : 0xefffffff; 192 193 return ramdac580; 194 } 195 196 void 197 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, 198 struct nvkm_pll_vals *pv) 199 { 200 struct nvkm_device *device = init->subdev.device; 201 int chip_version = device->bios->version.chip; 202 bool nv3035 = chip_version == 0x30 || chip_version == 0x35; 203 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); 204 uint32_t oldpll1 = nvkm_rd32(device, reg1); 205 uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0; 206 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; 207 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; 208 uint32_t oldramdac580 = 0, ramdac580 = 0; 209 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ 210 uint32_t saved_powerctrl_1 = 0, savedc040 = 0; 211 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); 212 213 /* model specific additions to generic pll1 and pll2 set up above */ 214 if (nv3035) { 215 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | 216 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; 217 pll2 = 0; 218 } 219 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ 220 oldramdac580 = nvkm_rd32(device, 0x680580); 221 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); 222 if (oldramdac580 != ramdac580) 223 oldpll1 = ~0; /* force mismatch */ 224 if (single_stage) 225 /* magic value used by nvidia in single stage mode */ 226 pll2 |= 0x011f; 227 } 228 if (chip_version > 0x70) 229 /* magic bits set by the blob (but not the bios) on g71-73 */ 230 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; 231 232 if (oldpll1 == pll1 && oldpll2 == pll2) 233 return; /* already set */ 234 235 if (shift_powerctrl_1 >= 0) { 236 saved_powerctrl_1 = nvkm_rd32(device, 0x001584); 237 nvkm_wr32(device, 0x001584, 238 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 239 1 << shift_powerctrl_1); 240 } 241 242 if (chip_version >= 0x40) { 243 int shift_c040 = 14; 244 245 switch (reg1) { 246 case 0x680504: 247 shift_c040 += 2; 248 case 0x680500: 249 shift_c040 += 2; 250 case 0x680520: 251 shift_c040 += 2; 252 case 0x680508: 253 shift_c040 += 2; 254 } 255 256 savedc040 = nvkm_rd32(device, 0xc040); 257 if (shift_c040 != 14) 258 nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040)); 259 } 260 261 if (oldramdac580 != ramdac580) 262 nvkm_wr32(device, 0x680580, ramdac580); 263 264 if (!nv3035) 265 nvkm_wr32(device, reg2, pll2); 266 nvkm_wr32(device, reg1, pll1); 267 268 if (shift_powerctrl_1 >= 0) 269 nvkm_wr32(device, 0x001584, saved_powerctrl_1); 270 if (chip_version >= 0x40) 271 nvkm_wr32(device, 0xc040, savedc040); 272 } 273 274 void 275 setPLL_double_lowregs(struct nvkm_devinit *init, u32 NMNMreg, 276 struct nvkm_pll_vals *pv) 277 { 278 /* When setting PLLs, there is a merry game of disabling and enabling 279 * various bits of hardware during the process. This function is a 280 * synthesis of six nv4x traces, nearly each card doing a subtly 281 * different thing. With luck all the necessary bits for each card are 282 * combined herein. Without luck it deviates from each card's formula 283 * so as to not work on any :) 284 */ 285 struct nvkm_device *device = init->subdev.device; 286 uint32_t Preg = NMNMreg - 4; 287 bool mpll = Preg == 0x4020; 288 uint32_t oldPval = nvkm_rd32(device, Preg); 289 uint32_t NMNM = pv->NM2 << 16 | pv->NM1; 290 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | 291 0xc << 28 | pv->log2P << 16; 292 uint32_t saved4600 = 0; 293 /* some cards have different maskc040s */ 294 uint32_t maskc040 = ~(3 << 14), savedc040; 295 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; 296 297 if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) 298 return; 299 300 if (Preg == 0x4000) 301 maskc040 = ~0x333; 302 if (Preg == 0x4058) 303 maskc040 = ~(0xc << 24); 304 305 if (mpll) { 306 struct nvbios_pll info; 307 uint8_t Pval2; 308 309 if (nvbios_pll_parse(device->bios, Preg, &info)) 310 return; 311 312 Pval2 = pv->log2P + info.bias_p; 313 if (Pval2 > info.max_p) 314 Pval2 = info.max_p; 315 Pval |= 1 << 28 | Pval2 << 20; 316 317 saved4600 = nvkm_rd32(device, 0x4600); 318 nvkm_wr32(device, 0x4600, saved4600 | 8 << 28); 319 } 320 if (single_stage) 321 Pval |= mpll ? 1 << 12 : 1 << 8; 322 323 nvkm_wr32(device, Preg, oldPval | 1 << 28); 324 nvkm_wr32(device, Preg, Pval & ~(4 << 28)); 325 if (mpll) { 326 Pval |= 8 << 20; 327 nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28)); 328 nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28)); 329 } 330 331 savedc040 = nvkm_rd32(device, 0xc040); 332 nvkm_wr32(device, 0xc040, savedc040 & maskc040); 333 334 nvkm_wr32(device, NMNMreg, NMNM); 335 if (NMNMreg == 0x4024) 336 nvkm_wr32(device, 0x403c, NMNM); 337 338 nvkm_wr32(device, Preg, Pval); 339 if (mpll) { 340 Pval &= ~(8 << 20); 341 nvkm_wr32(device, 0x4020, Pval); 342 nvkm_wr32(device, 0x4038, Pval); 343 nvkm_wr32(device, 0x4600, saved4600); 344 } 345 346 nvkm_wr32(device, 0xc040, savedc040); 347 348 if (mpll) { 349 nvkm_wr32(device, 0x4020, Pval & ~(1 << 28)); 350 nvkm_wr32(device, 0x4038, Pval & ~(1 << 28)); 351 } 352 } 353 354 int 355 nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) 356 { 357 struct nvkm_bios *bios = nvkm_bios(devinit); 358 struct nvkm_pll_vals pv; 359 struct nvbios_pll info; 360 int cv = bios->version.chip; 361 int N1, M1, N2, M2, P; 362 int ret; 363 364 ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info); 365 if (ret) 366 return ret; 367 368 ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, 369 &N1, &M1, &N2, &M2, &P); 370 if (!ret) 371 return -EINVAL; 372 373 pv.refclk = info.refclk; 374 pv.N1 = N1; 375 pv.M1 = M1; 376 pv.N2 = N2; 377 pv.M2 = M2; 378 pv.log2P = P; 379 380 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 381 cv >= 0x40) { 382 if (type > 0x405c) 383 setPLL_double_highregs(devinit, type, &pv); 384 else 385 setPLL_double_lowregs(devinit, type, &pv); 386 } else 387 setPLL_single(devinit, type, &pv); 388 389 return 0; 390 } 391 392 int 393 nv04_devinit_fini(struct nvkm_object *object, bool suspend) 394 { 395 struct nv04_devinit *init = (void *)object; 396 struct nvkm_device *device = init->base.subdev.device; 397 int ret; 398 399 /* make i2c busses accessible */ 400 nvkm_mask(device, 0x000200, 0x00000001, 0x00000001); 401 402 ret = nvkm_devinit_fini(&init->base, suspend); 403 if (ret) 404 return ret; 405 406 /* unslave crtcs */ 407 if (init->owner < 0) 408 init->owner = nv_rdvgaowner(init); 409 nv_wrvgaowner(init, 0); 410 return 0; 411 } 412 413 int 414 nv04_devinit_init(struct nvkm_object *object) 415 { 416 struct nv04_devinit *init = (void *)object; 417 418 if (!init->base.post) { 419 u32 htotal = nv_rdvgac(init, 0, 0x06); 420 htotal |= (nv_rdvgac(init, 0, 0x07) & 0x01) << 8; 421 htotal |= (nv_rdvgac(init, 0, 0x07) & 0x20) << 4; 422 htotal |= (nv_rdvgac(init, 0, 0x25) & 0x01) << 10; 423 htotal |= (nv_rdvgac(init, 0, 0x41) & 0x01) << 11; 424 if (!htotal) { 425 nv_info(init, "adaptor not initialised\n"); 426 init->base.post = true; 427 } 428 } 429 430 return nvkm_devinit_init(&init->base); 431 } 432 433 void 434 nv04_devinit_dtor(struct nvkm_object *object) 435 { 436 struct nv04_devinit *init = (void *)object; 437 438 /* restore vga owner saved at first init */ 439 nv_wrvgaowner(init, init->owner); 440 441 nvkm_devinit_destroy(&init->base); 442 } 443 444 int 445 nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 446 struct nvkm_oclass *oclass, void *data, u32 size, 447 struct nvkm_object **pobject) 448 { 449 struct nv04_devinit *init; 450 int ret; 451 452 ret = nvkm_devinit_create(parent, engine, oclass, &init); 453 *pobject = nv_object(init); 454 if (ret) 455 return ret; 456 457 init->owner = -1; 458 return 0; 459 } 460 461 struct nvkm_oclass * 462 nv04_devinit_oclass = &(struct nvkm_devinit_impl) { 463 .base.handle = NV_SUBDEV(DEVINIT, 0x04), 464 .base.ofuncs = &(struct nvkm_ofuncs) { 465 .ctor = nv04_devinit_ctor, 466 .dtor = nv04_devinit_dtor, 467 .init = nv04_devinit_init, 468 .fini = nv04_devinit_fini, 469 }, 470 .meminit = nv04_devinit_meminit, 471 .pll_set = nv04_devinit_pll_set, 472 .post = nvbios_init, 473 }.base; 474