1 /* 2 * Copyright (C) 2010 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 #include "nv04.h" 27 #include "fbmem.h" 28 29 #include <subdev/bios.h> 30 #include <subdev/bios/init.h> 31 #include <subdev/bios/pll.h> 32 #include <subdev/clk/pll.h> 33 #include <subdev/vga.h> 34 35 static void 36 nv04_devinit_meminit(struct nvkm_devinit *devinit) 37 { 38 struct nv04_devinit_priv *priv = (void *)devinit; 39 u32 patt = 0xdeadbeef; 40 struct io_mapping *fb; 41 int i; 42 43 /* Map the framebuffer aperture */ 44 fb = fbmem_init(nv_device(priv)); 45 if (!fb) { 46 nv_error(priv, "failed to map fb\n"); 47 return; 48 } 49 50 /* Sequencer and refresh off */ 51 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20); 52 nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 53 54 nv_mask(priv, NV04_PFB_BOOT_0, ~0, 55 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 56 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 57 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 58 59 for (i = 0; i < 4; i++) 60 fbmem_poke(fb, 4 * i, patt); 61 62 fbmem_poke(fb, 0x400000, patt + 1); 63 64 if (fbmem_peek(fb, 0) == patt + 1) { 65 nv_mask(priv, NV04_PFB_BOOT_0, 66 NV04_PFB_BOOT_0_RAM_TYPE, 67 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 68 nv_mask(priv, NV04_PFB_DEBUG_0, 69 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 70 71 for (i = 0; i < 4; i++) 72 fbmem_poke(fb, 4 * i, patt); 73 74 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff)) 75 nv_mask(priv, NV04_PFB_BOOT_0, 76 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 77 NV04_PFB_BOOT_0_RAM_AMOUNT, 78 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 79 } else 80 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) { 81 nv_mask(priv, NV04_PFB_BOOT_0, 82 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 83 NV04_PFB_BOOT_0_RAM_AMOUNT, 84 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 85 } else 86 if (fbmem_peek(fb, 0) != patt) { 87 if (fbmem_readback(fb, 0x800000, patt)) 88 nv_mask(priv, NV04_PFB_BOOT_0, 89 NV04_PFB_BOOT_0_RAM_AMOUNT, 90 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 91 else 92 nv_mask(priv, NV04_PFB_BOOT_0, 93 NV04_PFB_BOOT_0_RAM_AMOUNT, 94 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 95 96 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 97 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 98 } else 99 if (!fbmem_readback(fb, 0x800000, patt)) { 100 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 101 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 102 103 } 104 105 /* Refresh on, sequencer on */ 106 nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 107 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20); 108 fbmem_fini(fb); 109 } 110 111 static int 112 powerctrl_1_shift(int chip_version, int reg) 113 { 114 int shift = -4; 115 116 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20) 117 return shift; 118 119 switch (reg) { 120 case 0x680520: 121 shift += 4; 122 case 0x680508: 123 shift += 4; 124 case 0x680504: 125 shift += 4; 126 case 0x680500: 127 shift += 4; 128 } 129 130 /* 131 * the shift for vpll regs is only used for nv3x chips with a single 132 * stage pll 133 */ 134 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 || 135 chip_version == 0x36 || chip_version >= 0x40)) 136 shift = -4; 137 138 return shift; 139 } 140 141 void 142 setPLL_single(struct nvkm_devinit *devinit, u32 reg, 143 struct nvkm_pll_vals *pv) 144 { 145 int chip_version = nvkm_bios(devinit)->version.chip; 146 uint32_t oldpll = nv_rd32(devinit, reg); 147 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; 148 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; 149 uint32_t saved_powerctrl_1 = 0; 150 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); 151 152 if (oldpll == pll) 153 return; /* already set */ 154 155 if (shift_powerctrl_1 >= 0) { 156 saved_powerctrl_1 = nv_rd32(devinit, 0x001584); 157 nv_wr32(devinit, 0x001584, 158 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 159 1 << shift_powerctrl_1); 160 } 161 162 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) 163 /* upclock -- write new post divider first */ 164 nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff)); 165 else 166 /* downclock -- write new NM first */ 167 nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1); 168 169 if ((chip_version < 0x17 || chip_version == 0x1a) && 170 chip_version != 0x11) 171 /* wait a bit on older chips */ 172 msleep(64); 173 nv_rd32(devinit, reg); 174 175 /* then write the other half as well */ 176 nv_wr32(devinit, reg, pll); 177 178 if (shift_powerctrl_1 >= 0) 179 nv_wr32(devinit, 0x001584, saved_powerctrl_1); 180 } 181 182 static uint32_t 183 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) 184 { 185 bool head_a = (reg1 == 0x680508); 186 187 if (ss) /* single stage pll mode */ 188 ramdac580 |= head_a ? 0x00000100 : 0x10000000; 189 else 190 ramdac580 &= head_a ? 0xfffffeff : 0xefffffff; 191 192 return ramdac580; 193 } 194 195 void 196 setPLL_double_highregs(struct nvkm_devinit *devinit, u32 reg1, 197 struct nvkm_pll_vals *pv) 198 { 199 int chip_version = nvkm_bios(devinit)->version.chip; 200 bool nv3035 = chip_version == 0x30 || chip_version == 0x35; 201 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); 202 uint32_t oldpll1 = nv_rd32(devinit, reg1); 203 uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0; 204 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; 205 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; 206 uint32_t oldramdac580 = 0, ramdac580 = 0; 207 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ 208 uint32_t saved_powerctrl_1 = 0, savedc040 = 0; 209 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); 210 211 /* model specific additions to generic pll1 and pll2 set up above */ 212 if (nv3035) { 213 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | 214 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; 215 pll2 = 0; 216 } 217 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ 218 oldramdac580 = nv_rd32(devinit, 0x680580); 219 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); 220 if (oldramdac580 != ramdac580) 221 oldpll1 = ~0; /* force mismatch */ 222 if (single_stage) 223 /* magic value used by nvidia in single stage mode */ 224 pll2 |= 0x011f; 225 } 226 if (chip_version > 0x70) 227 /* magic bits set by the blob (but not the bios) on g71-73 */ 228 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; 229 230 if (oldpll1 == pll1 && oldpll2 == pll2) 231 return; /* already set */ 232 233 if (shift_powerctrl_1 >= 0) { 234 saved_powerctrl_1 = nv_rd32(devinit, 0x001584); 235 nv_wr32(devinit, 0x001584, 236 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 237 1 << shift_powerctrl_1); 238 } 239 240 if (chip_version >= 0x40) { 241 int shift_c040 = 14; 242 243 switch (reg1) { 244 case 0x680504: 245 shift_c040 += 2; 246 case 0x680500: 247 shift_c040 += 2; 248 case 0x680520: 249 shift_c040 += 2; 250 case 0x680508: 251 shift_c040 += 2; 252 } 253 254 savedc040 = nv_rd32(devinit, 0xc040); 255 if (shift_c040 != 14) 256 nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040)); 257 } 258 259 if (oldramdac580 != ramdac580) 260 nv_wr32(devinit, 0x680580, ramdac580); 261 262 if (!nv3035) 263 nv_wr32(devinit, reg2, pll2); 264 nv_wr32(devinit, reg1, pll1); 265 266 if (shift_powerctrl_1 >= 0) 267 nv_wr32(devinit, 0x001584, saved_powerctrl_1); 268 if (chip_version >= 0x40) 269 nv_wr32(devinit, 0xc040, savedc040); 270 } 271 272 void 273 setPLL_double_lowregs(struct nvkm_devinit *devinit, u32 NMNMreg, 274 struct nvkm_pll_vals *pv) 275 { 276 /* When setting PLLs, there is a merry game of disabling and enabling 277 * various bits of hardware during the process. This function is a 278 * synthesis of six nv4x traces, nearly each card doing a subtly 279 * different thing. With luck all the necessary bits for each card are 280 * combined herein. Without luck it deviates from each card's formula 281 * so as to not work on any :) 282 */ 283 284 uint32_t Preg = NMNMreg - 4; 285 bool mpll = Preg == 0x4020; 286 uint32_t oldPval = nv_rd32(devinit, Preg); 287 uint32_t NMNM = pv->NM2 << 16 | pv->NM1; 288 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | 289 0xc << 28 | pv->log2P << 16; 290 uint32_t saved4600 = 0; 291 /* some cards have different maskc040s */ 292 uint32_t maskc040 = ~(3 << 14), savedc040; 293 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; 294 295 if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) 296 return; 297 298 if (Preg == 0x4000) 299 maskc040 = ~0x333; 300 if (Preg == 0x4058) 301 maskc040 = ~(0xc << 24); 302 303 if (mpll) { 304 struct nvbios_pll info; 305 uint8_t Pval2; 306 307 if (nvbios_pll_parse(nvkm_bios(devinit), Preg, &info)) 308 return; 309 310 Pval2 = pv->log2P + info.bias_p; 311 if (Pval2 > info.max_p) 312 Pval2 = info.max_p; 313 Pval |= 1 << 28 | Pval2 << 20; 314 315 saved4600 = nv_rd32(devinit, 0x4600); 316 nv_wr32(devinit, 0x4600, saved4600 | 8 << 28); 317 } 318 if (single_stage) 319 Pval |= mpll ? 1 << 12 : 1 << 8; 320 321 nv_wr32(devinit, Preg, oldPval | 1 << 28); 322 nv_wr32(devinit, Preg, Pval & ~(4 << 28)); 323 if (mpll) { 324 Pval |= 8 << 20; 325 nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28)); 326 nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28)); 327 } 328 329 savedc040 = nv_rd32(devinit, 0xc040); 330 nv_wr32(devinit, 0xc040, savedc040 & maskc040); 331 332 nv_wr32(devinit, NMNMreg, NMNM); 333 if (NMNMreg == 0x4024) 334 nv_wr32(devinit, 0x403c, NMNM); 335 336 nv_wr32(devinit, Preg, Pval); 337 if (mpll) { 338 Pval &= ~(8 << 20); 339 nv_wr32(devinit, 0x4020, Pval); 340 nv_wr32(devinit, 0x4038, Pval); 341 nv_wr32(devinit, 0x4600, saved4600); 342 } 343 344 nv_wr32(devinit, 0xc040, savedc040); 345 346 if (mpll) { 347 nv_wr32(devinit, 0x4020, Pval & ~(1 << 28)); 348 nv_wr32(devinit, 0x4038, Pval & ~(1 << 28)); 349 } 350 } 351 352 int 353 nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) 354 { 355 struct nvkm_bios *bios = nvkm_bios(devinit); 356 struct nvkm_pll_vals pv; 357 struct nvbios_pll info; 358 int cv = bios->version.chip; 359 int N1, M1, N2, M2, P; 360 int ret; 361 362 ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info); 363 if (ret) 364 return ret; 365 366 ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, 367 &N1, &M1, &N2, &M2, &P); 368 if (!ret) 369 return -EINVAL; 370 371 pv.refclk = info.refclk; 372 pv.N1 = N1; 373 pv.M1 = M1; 374 pv.N2 = N2; 375 pv.M2 = M2; 376 pv.log2P = P; 377 378 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 379 cv >= 0x40) { 380 if (type > 0x405c) 381 setPLL_double_highregs(devinit, type, &pv); 382 else 383 setPLL_double_lowregs(devinit, type, &pv); 384 } else 385 setPLL_single(devinit, type, &pv); 386 387 return 0; 388 } 389 390 int 391 nv04_devinit_fini(struct nvkm_object *object, bool suspend) 392 { 393 struct nv04_devinit_priv *priv = (void *)object; 394 int ret; 395 396 /* make i2c busses accessible */ 397 nv_mask(priv, 0x000200, 0x00000001, 0x00000001); 398 399 ret = nvkm_devinit_fini(&priv->base, suspend); 400 if (ret) 401 return ret; 402 403 /* unslave crtcs */ 404 if (priv->owner < 0) 405 priv->owner = nv_rdvgaowner(priv); 406 nv_wrvgaowner(priv, 0); 407 return 0; 408 } 409 410 int 411 nv04_devinit_init(struct nvkm_object *object) 412 { 413 struct nv04_devinit_priv *priv = (void *)object; 414 415 if (!priv->base.post) { 416 u32 htotal = nv_rdvgac(priv, 0, 0x06); 417 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8; 418 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4; 419 htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10; 420 htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11; 421 if (!htotal) { 422 nv_info(priv, "adaptor not initialised\n"); 423 priv->base.post = true; 424 } 425 } 426 427 return nvkm_devinit_init(&priv->base); 428 } 429 430 void 431 nv04_devinit_dtor(struct nvkm_object *object) 432 { 433 struct nv04_devinit_priv *priv = (void *)object; 434 435 /* restore vga owner saved at first init */ 436 nv_wrvgaowner(priv, priv->owner); 437 438 nvkm_devinit_destroy(&priv->base); 439 } 440 441 int 442 nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 443 struct nvkm_oclass *oclass, void *data, u32 size, 444 struct nvkm_object **pobject) 445 { 446 struct nv04_devinit_priv *priv; 447 int ret; 448 449 ret = nvkm_devinit_create(parent, engine, oclass, &priv); 450 *pobject = nv_object(priv); 451 if (ret) 452 return ret; 453 454 priv->owner = -1; 455 return 0; 456 } 457 458 struct nvkm_oclass * 459 nv04_devinit_oclass = &(struct nvkm_devinit_impl) { 460 .base.handle = NV_SUBDEV(DEVINIT, 0x04), 461 .base.ofuncs = &(struct nvkm_ofuncs) { 462 .ctor = nv04_devinit_ctor, 463 .dtor = nv04_devinit_dtor, 464 .init = nv04_devinit_init, 465 .fini = nv04_devinit_fini, 466 }, 467 .meminit = nv04_devinit_meminit, 468 .pll_set = nv04_devinit_pll_set, 469 .post = nvbios_init, 470 }.base; 471