1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "pll.h" 26 #include "seq.h" 27 28 #include <subdev/bios.h> 29 #include <subdev/bios/pll.h> 30 31 static u32 32 read_div(struct nv50_clk *clk) 33 { 34 struct nvkm_device *device = clk->base.subdev.device; 35 switch (device->chipset) { 36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 37 case 0x84: 38 case 0x86: 39 case 0x98: 40 case 0xa0: 41 return nvkm_rd32(device, 0x004700); 42 case 0x92: 43 case 0x94: 44 case 0x96: 45 return nvkm_rd32(device, 0x004800); 46 default: 47 return 0x00000000; 48 } 49 } 50 51 static u32 52 read_pll_src(struct nv50_clk *clk, u32 base) 53 { 54 struct nvkm_subdev *subdev = &clk->base.subdev; 55 struct nvkm_device *device = subdev->device; 56 u32 coef, ref = clk->base.read(&clk->base, nv_clk_src_crystal); 57 u32 rsel = nvkm_rd32(device, 0x00e18c); 58 int P, N, M, id; 59 60 switch (device->chipset) { 61 case 0x50: 62 case 0xa0: 63 switch (base) { 64 case 0x4020: 65 case 0x4028: id = !!(rsel & 0x00000004); break; 66 case 0x4008: id = !!(rsel & 0x00000008); break; 67 case 0x4030: id = 0; break; 68 default: 69 nvkm_error(subdev, "ref: bad pll %06x\n", base); 70 return 0; 71 } 72 73 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); 74 ref *= (coef & 0x01000000) ? 2 : 4; 75 P = (coef & 0x00070000) >> 16; 76 N = ((coef & 0x0000ff00) >> 8) + 1; 77 M = ((coef & 0x000000ff) >> 0) + 1; 78 break; 79 case 0x84: 80 case 0x86: 81 case 0x92: 82 coef = nvkm_rd32(device, 0x00e81c); 83 P = (coef & 0x00070000) >> 16; 84 N = (coef & 0x0000ff00) >> 8; 85 M = (coef & 0x000000ff) >> 0; 86 break; 87 case 0x94: 88 case 0x96: 89 case 0x98: 90 rsel = nvkm_rd32(device, 0x00c050); 91 switch (base) { 92 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; 93 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; 94 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; 95 case 0x4030: rsel = 3; break; 96 default: 97 nvkm_error(subdev, "ref: bad pll %06x\n", base); 98 return 0; 99 } 100 101 switch (rsel) { 102 case 0: id = 1; break; 103 case 1: return clk->base.read(&clk->base, nv_clk_src_crystal); 104 case 2: return clk->base.read(&clk->base, nv_clk_src_href); 105 case 3: id = 0; break; 106 } 107 108 coef = nvkm_rd32(device, 0x00e81c + (id * 0x28)); 109 P = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7; 110 P += (coef & 0x00070000) >> 16; 111 N = (coef & 0x0000ff00) >> 8; 112 M = (coef & 0x000000ff) >> 0; 113 break; 114 default: 115 BUG_ON(1); 116 } 117 118 if (M) 119 return (ref * N / M) >> P; 120 121 return 0; 122 } 123 124 static u32 125 read_pll_ref(struct nv50_clk *clk, u32 base) 126 { 127 struct nvkm_subdev *subdev = &clk->base.subdev; 128 struct nvkm_device *device = subdev->device; 129 u32 src, mast = nvkm_rd32(device, 0x00c040); 130 131 switch (base) { 132 case 0x004028: 133 src = !!(mast & 0x00200000); 134 break; 135 case 0x004020: 136 src = !!(mast & 0x00400000); 137 break; 138 case 0x004008: 139 src = !!(mast & 0x00010000); 140 break; 141 case 0x004030: 142 src = !!(mast & 0x02000000); 143 break; 144 case 0x00e810: 145 return clk->base.read(&clk->base, nv_clk_src_crystal); 146 default: 147 nvkm_error(subdev, "bad pll %06x\n", base); 148 return 0; 149 } 150 151 if (src) 152 return clk->base.read(&clk->base, nv_clk_src_href); 153 154 return read_pll_src(clk, base); 155 } 156 157 static u32 158 read_pll(struct nv50_clk *clk, u32 base) 159 { 160 struct nvkm_device *device = clk->base.subdev.device; 161 u32 mast = nvkm_rd32(device, 0x00c040); 162 u32 ctrl = nvkm_rd32(device, base + 0); 163 u32 coef = nvkm_rd32(device, base + 4); 164 u32 ref = read_pll_ref(clk, base); 165 u32 freq = 0; 166 int N1, N2, M1, M2; 167 168 if (base == 0x004028 && (mast & 0x00100000)) { 169 /* wtf, appears to only disable post-divider on gt200 */ 170 if (device->chipset != 0xa0) 171 return clk->base.read(&clk->base, nv_clk_src_dom6); 172 } 173 174 N2 = (coef & 0xff000000) >> 24; 175 M2 = (coef & 0x00ff0000) >> 16; 176 N1 = (coef & 0x0000ff00) >> 8; 177 M1 = (coef & 0x000000ff); 178 if ((ctrl & 0x80000000) && M1) { 179 freq = ref * N1 / M1; 180 if ((ctrl & 0x40000100) == 0x40000000) { 181 if (M2) 182 freq = freq * N2 / M2; 183 else 184 freq = 0; 185 } 186 } 187 188 return freq; 189 } 190 191 static int 192 nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 193 { 194 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 195 struct nvkm_subdev *subdev = &clk->base.subdev; 196 struct nvkm_device *device = subdev->device; 197 u32 mast = nvkm_rd32(device, 0x00c040); 198 u32 P = 0; 199 200 switch (src) { 201 case nv_clk_src_crystal: 202 return device->crystal; 203 case nv_clk_src_href: 204 return 100000; /* PCIE reference clock */ 205 case nv_clk_src_hclk: 206 return div_u64((u64)clk->base.read(&clk->base, nv_clk_src_href) * 27778, 10000); 207 case nv_clk_src_hclkm3: 208 return clk->base.read(&clk->base, nv_clk_src_hclk) * 3; 209 case nv_clk_src_hclkm3d2: 210 return clk->base.read(&clk->base, nv_clk_src_hclk) * 3 / 2; 211 case nv_clk_src_host: 212 switch (mast & 0x30000000) { 213 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_href); 214 case 0x10000000: break; 215 case 0x20000000: /* !0x50 */ 216 case 0x30000000: return clk->base.read(&clk->base, nv_clk_src_hclk); 217 } 218 break; 219 case nv_clk_src_core: 220 if (!(mast & 0x00100000)) 221 P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; 222 switch (mast & 0x00000003) { 223 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 224 case 0x00000001: return clk->base.read(&clk->base, nv_clk_src_dom6); 225 case 0x00000002: return read_pll(clk, 0x004020) >> P; 226 case 0x00000003: return read_pll(clk, 0x004028) >> P; 227 } 228 break; 229 case nv_clk_src_shader: 230 P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; 231 switch (mast & 0x00000030) { 232 case 0x00000000: 233 if (mast & 0x00000080) 234 return clk->base.read(&clk->base, nv_clk_src_host) >> P; 235 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 236 case 0x00000010: break; 237 case 0x00000020: return read_pll(clk, 0x004028) >> P; 238 case 0x00000030: return read_pll(clk, 0x004020) >> P; 239 } 240 break; 241 case nv_clk_src_mem: 242 P = (nvkm_rd32(device, 0x004008) & 0x00070000) >> 16; 243 if (nvkm_rd32(device, 0x004008) & 0x00000200) { 244 switch (mast & 0x0000c000) { 245 case 0x00000000: 246 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 247 case 0x00008000: 248 case 0x0000c000: 249 return clk->base.read(&clk->base, nv_clk_src_href) >> P; 250 } 251 } else { 252 return read_pll(clk, 0x004008) >> P; 253 } 254 break; 255 case nv_clk_src_vdec: 256 P = (read_div(clk) & 0x00000700) >> 8; 257 switch (device->chipset) { 258 case 0x84: 259 case 0x86: 260 case 0x92: 261 case 0x94: 262 case 0x96: 263 case 0xa0: 264 switch (mast & 0x00000c00) { 265 case 0x00000000: 266 if (device->chipset == 0xa0) /* wtf?? */ 267 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 268 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 269 case 0x00000400: 270 return 0; 271 case 0x00000800: 272 if (mast & 0x01000000) 273 return read_pll(clk, 0x004028) >> P; 274 return read_pll(clk, 0x004030) >> P; 275 case 0x00000c00: 276 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 277 } 278 break; 279 case 0x98: 280 switch (mast & 0x00000c00) { 281 case 0x00000000: 282 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 283 case 0x00000400: 284 return 0; 285 case 0x00000800: 286 return clk->base.read(&clk->base, nv_clk_src_hclkm3d2) >> P; 287 case 0x00000c00: 288 return clk->base.read(&clk->base, nv_clk_src_mem) >> P; 289 } 290 break; 291 } 292 break; 293 case nv_clk_src_dom6: 294 switch (device->chipset) { 295 case 0x50: 296 case 0xa0: 297 return read_pll(clk, 0x00e810) >> 2; 298 case 0x84: 299 case 0x86: 300 case 0x92: 301 case 0x94: 302 case 0x96: 303 case 0x98: 304 P = (read_div(clk) & 0x00000007) >> 0; 305 switch (mast & 0x0c000000) { 306 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_href); 307 case 0x04000000: break; 308 case 0x08000000: return clk->base.read(&clk->base, nv_clk_src_hclk); 309 case 0x0c000000: 310 return clk->base.read(&clk->base, nv_clk_src_hclkm3) >> P; 311 } 312 break; 313 default: 314 break; 315 } 316 default: 317 break; 318 } 319 320 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast); 321 return -EINVAL; 322 } 323 324 static u32 325 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P) 326 { 327 struct nvkm_bios *bios = nvkm_bios(clk); 328 struct nvbios_pll pll; 329 int ret; 330 331 ret = nvbios_pll_parse(bios, reg, &pll); 332 if (ret) 333 return 0; 334 335 pll.vco2.max_freq = 0; 336 pll.refclk = read_pll_ref(clk, reg); 337 if (!pll.refclk) 338 return 0; 339 340 return nv04_pll_calc(nv_subdev(clk), &pll, idx, N, M, NULL, NULL, P); 341 } 342 343 static inline u32 344 calc_div(u32 src, u32 target, int *div) 345 { 346 u32 clk0 = src, clk1 = src; 347 for (*div = 0; *div <= 7; (*div)++) { 348 if (clk0 <= target) { 349 clk1 = clk0 << (*div ? 1 : 0); 350 break; 351 } 352 clk0 >>= 1; 353 } 354 355 if (target - clk0 <= clk1 - target) 356 return clk0; 357 (*div)--; 358 return clk1; 359 } 360 361 static inline u32 362 clk_same(u32 a, u32 b) 363 { 364 return ((a / 1000) == (b / 1000)); 365 } 366 367 static int 368 nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 369 { 370 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 371 struct nv50_clk_hwsq *hwsq = &clk->hwsq; 372 const int shader = cstate->domain[nv_clk_src_shader]; 373 const int core = cstate->domain[nv_clk_src_core]; 374 const int vdec = cstate->domain[nv_clk_src_vdec]; 375 const int dom6 = cstate->domain[nv_clk_src_dom6]; 376 u32 mastm = 0, mastv = 0; 377 u32 divsm = 0, divsv = 0; 378 int N, M, P1, P2; 379 int freq, out; 380 381 /* prepare a hwsq script from which we'll perform the reclock */ 382 out = clk_init(hwsq, nv_subdev(clk)); 383 if (out) 384 return out; 385 386 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ 387 clk_nsec(hwsq, 8000); 388 clk_setf(hwsq, 0x10, 0x00); /* disable fb */ 389 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 390 391 /* vdec: avoid modifying xpll until we know exactly how the other 392 * clock domains work, i suspect at least some of them can also be 393 * tied to xpll... 394 */ 395 if (vdec) { 396 /* see how close we can get using nvclk as a source */ 397 freq = calc_div(core, vdec, &P1); 398 399 /* see how close we can get using xpll/hclk as a source */ 400 if (nv_device(clk)->chipset != 0x98) 401 out = read_pll(clk, 0x004030); 402 else 403 out = clk->base.read(&clk->base, nv_clk_src_hclkm3d2); 404 out = calc_div(out, vdec, &P2); 405 406 /* select whichever gets us closest */ 407 if (abs(vdec - freq) <= abs(vdec - out)) { 408 if (nv_device(clk)->chipset != 0x98) 409 mastv |= 0x00000c00; 410 divsv |= P1 << 8; 411 } else { 412 mastv |= 0x00000800; 413 divsv |= P2 << 8; 414 } 415 416 mastm |= 0x00000c00; 417 divsm |= 0x00000700; 418 } 419 420 /* dom6: nfi what this is, but we're limited to various combinations 421 * of the host clock frequency 422 */ 423 if (dom6) { 424 if (clk_same(dom6, clk->base.read(&clk->base, nv_clk_src_href))) { 425 mastv |= 0x00000000; 426 } else 427 if (clk_same(dom6, clk->base.read(&clk->base, nv_clk_src_hclk))) { 428 mastv |= 0x08000000; 429 } else { 430 freq = clk->base.read(&clk->base, nv_clk_src_hclk) * 3; 431 calc_div(freq, dom6, &P1); 432 433 mastv |= 0x0c000000; 434 divsv |= P1; 435 } 436 437 mastm |= 0x0c000000; 438 divsm |= 0x00000007; 439 } 440 441 /* vdec/dom6: switch to "safe" clocks temporarily, update dividers 442 * and then switch to target clocks 443 */ 444 clk_mask(hwsq, mast, mastm, 0x00000000); 445 clk_mask(hwsq, divs, divsm, divsv); 446 clk_mask(hwsq, mast, mastm, mastv); 447 448 /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, 449 * sclk to hclk) before reprogramming 450 */ 451 if (nv_device(clk)->chipset < 0x92) 452 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); 453 else 454 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); 455 456 /* core: for the moment at least, always use nvpll */ 457 freq = calc_pll(clk, 0x4028, core, &N, &M, &P1); 458 if (freq == 0) 459 return -ERANGE; 460 461 clk_mask(hwsq, nvpll[0], 0xc03f0100, 462 0x80000000 | (P1 << 19) | (P1 << 16)); 463 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); 464 465 /* shader: tie to nvclk if possible, otherwise use spll. have to be 466 * very careful that the shader clock is at least twice the core, or 467 * some chipsets will be very unhappy. i expect most or all of these 468 * cases will be handled by tying to nvclk, but it's possible there's 469 * corners 470 */ 471 if (P1-- && shader == (core << 1)) { 472 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); 473 clk_mask(hwsq, mast, 0x00100033, 0x00000023); 474 } else { 475 freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1); 476 if (freq == 0) 477 return -ERANGE; 478 479 clk_mask(hwsq, spll[0], 0xc03f0100, 480 0x80000000 | (P1 << 19) | (P1 << 16)); 481 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); 482 clk_mask(hwsq, mast, 0x00100033, 0x00000033); 483 } 484 485 /* restore normal operation */ 486 clk_setf(hwsq, 0x10, 0x01); /* enable fb */ 487 clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 488 clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ 489 return 0; 490 } 491 492 static int 493 nv50_clk_prog(struct nvkm_clk *obj) 494 { 495 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 496 return clk_exec(&clk->hwsq, true); 497 } 498 499 static void 500 nv50_clk_tidy(struct nvkm_clk *obj) 501 { 502 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 503 clk_exec(&clk->hwsq, false); 504 } 505 506 int 507 nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 508 struct nvkm_oclass *oclass, void *data, u32 size, 509 struct nvkm_object **pobject) 510 { 511 struct nv50_clk_oclass *pclass = (void *)oclass; 512 struct nv50_clk *clk; 513 int ret; 514 515 ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, 516 NULL, 0, nv_device(parent)->chipset == 0xa0, 517 &clk); 518 *pobject = nv_object(clk); 519 if (ret) 520 return ret; 521 522 clk->hwsq.r_fifo = hwsq_reg(0x002504); 523 clk->hwsq.r_spll[0] = hwsq_reg(0x004020); 524 clk->hwsq.r_spll[1] = hwsq_reg(0x004024); 525 clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028); 526 clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); 527 switch (nv_device(clk)->chipset) { 528 case 0x92: 529 case 0x94: 530 case 0x96: 531 clk->hwsq.r_divs = hwsq_reg(0x004800); 532 break; 533 default: 534 clk->hwsq.r_divs = hwsq_reg(0x004700); 535 break; 536 } 537 clk->hwsq.r_mast = hwsq_reg(0x00c040); 538 539 clk->base.read = nv50_clk_read; 540 clk->base.calc = nv50_clk_calc; 541 clk->base.prog = nv50_clk_prog; 542 clk->base.tidy = nv50_clk_tidy; 543 return 0; 544 } 545 546 static struct nvkm_domain 547 nv50_domains[] = { 548 { nv_clk_src_crystal, 0xff }, 549 { nv_clk_src_href , 0xff }, 550 { nv_clk_src_core , 0xff, 0, "core", 1000 }, 551 { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, 552 { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, 553 { nv_clk_src_max } 554 }; 555 556 struct nvkm_oclass * 557 nv50_clk_oclass = &(struct nv50_clk_oclass) { 558 .base.handle = NV_SUBDEV(CLK, 0x50), 559 .base.ofuncs = &(struct nvkm_ofuncs) { 560 .ctor = nv50_clk_ctor, 561 .dtor = _nvkm_clk_dtor, 562 .init = _nvkm_clk_init, 563 .fini = _nvkm_clk_fini, 564 }, 565 .domains = nv50_domains, 566 }.base; 567