1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "pll.h" 26 #include "seq.h" 27 28 #include <subdev/bios.h> 29 #include <subdev/bios/pll.h> 30 31 static u32 32 read_div(struct nv50_clk_priv *priv) 33 { 34 switch (nv_device(priv)->chipset) { 35 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 36 case 0x84: 37 case 0x86: 38 case 0x98: 39 case 0xa0: 40 return nv_rd32(priv, 0x004700); 41 case 0x92: 42 case 0x94: 43 case 0x96: 44 return nv_rd32(priv, 0x004800); 45 default: 46 return 0x00000000; 47 } 48 } 49 50 static u32 51 read_pll_src(struct nv50_clk_priv *priv, u32 base) 52 { 53 struct nvkm_clk *clk = &priv->base; 54 u32 coef, ref = clk->read(clk, nv_clk_src_crystal); 55 u32 rsel = nv_rd32(priv, 0x00e18c); 56 int P, N, M, id; 57 58 switch (nv_device(priv)->chipset) { 59 case 0x50: 60 case 0xa0: 61 switch (base) { 62 case 0x4020: 63 case 0x4028: id = !!(rsel & 0x00000004); break; 64 case 0x4008: id = !!(rsel & 0x00000008); break; 65 case 0x4030: id = 0; break; 66 default: 67 nv_error(priv, "ref: bad pll 0x%06x\n", base); 68 return 0; 69 } 70 71 coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); 72 ref *= (coef & 0x01000000) ? 2 : 4; 73 P = (coef & 0x00070000) >> 16; 74 N = ((coef & 0x0000ff00) >> 8) + 1; 75 M = ((coef & 0x000000ff) >> 0) + 1; 76 break; 77 case 0x84: 78 case 0x86: 79 case 0x92: 80 coef = nv_rd32(priv, 0x00e81c); 81 P = (coef & 0x00070000) >> 16; 82 N = (coef & 0x0000ff00) >> 8; 83 M = (coef & 0x000000ff) >> 0; 84 break; 85 case 0x94: 86 case 0x96: 87 case 0x98: 88 rsel = nv_rd32(priv, 0x00c050); 89 switch (base) { 90 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; 91 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; 92 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; 93 case 0x4030: rsel = 3; break; 94 default: 95 nv_error(priv, "ref: bad pll 0x%06x\n", base); 96 return 0; 97 } 98 99 switch (rsel) { 100 case 0: id = 1; break; 101 case 1: return clk->read(clk, nv_clk_src_crystal); 102 case 2: return clk->read(clk, nv_clk_src_href); 103 case 3: id = 0; break; 104 } 105 106 coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); 107 P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; 108 P += (coef & 0x00070000) >> 16; 109 N = (coef & 0x0000ff00) >> 8; 110 M = (coef & 0x000000ff) >> 0; 111 break; 112 default: 113 BUG_ON(1); 114 } 115 116 if (M) 117 return (ref * N / M) >> P; 118 119 return 0; 120 } 121 122 static u32 123 read_pll_ref(struct nv50_clk_priv *priv, u32 base) 124 { 125 struct nvkm_clk *clk = &priv->base; 126 u32 src, mast = nv_rd32(priv, 0x00c040); 127 128 switch (base) { 129 case 0x004028: 130 src = !!(mast & 0x00200000); 131 break; 132 case 0x004020: 133 src = !!(mast & 0x00400000); 134 break; 135 case 0x004008: 136 src = !!(mast & 0x00010000); 137 break; 138 case 0x004030: 139 src = !!(mast & 0x02000000); 140 break; 141 case 0x00e810: 142 return clk->read(clk, nv_clk_src_crystal); 143 default: 144 nv_error(priv, "bad pll 0x%06x\n", base); 145 return 0; 146 } 147 148 if (src) 149 return clk->read(clk, nv_clk_src_href); 150 151 return read_pll_src(priv, base); 152 } 153 154 static u32 155 read_pll(struct nv50_clk_priv *priv, u32 base) 156 { 157 struct nvkm_clk *clk = &priv->base; 158 u32 mast = nv_rd32(priv, 0x00c040); 159 u32 ctrl = nv_rd32(priv, base + 0); 160 u32 coef = nv_rd32(priv, base + 4); 161 u32 ref = read_pll_ref(priv, base); 162 u32 freq = 0; 163 int N1, N2, M1, M2; 164 165 if (base == 0x004028 && (mast & 0x00100000)) { 166 /* wtf, appears to only disable post-divider on gt200 */ 167 if (nv_device(priv)->chipset != 0xa0) 168 return clk->read(clk, nv_clk_src_dom6); 169 } 170 171 N2 = (coef & 0xff000000) >> 24; 172 M2 = (coef & 0x00ff0000) >> 16; 173 N1 = (coef & 0x0000ff00) >> 8; 174 M1 = (coef & 0x000000ff); 175 if ((ctrl & 0x80000000) && M1) { 176 freq = ref * N1 / M1; 177 if ((ctrl & 0x40000100) == 0x40000000) { 178 if (M2) 179 freq = freq * N2 / M2; 180 else 181 freq = 0; 182 } 183 } 184 185 return freq; 186 } 187 188 static int 189 nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) 190 { 191 struct nv50_clk_priv *priv = (void *)clk; 192 u32 mast = nv_rd32(priv, 0x00c040); 193 u32 P = 0; 194 195 switch (src) { 196 case nv_clk_src_crystal: 197 return nv_device(priv)->crystal; 198 case nv_clk_src_href: 199 return 100000; /* PCIE reference clock */ 200 case nv_clk_src_hclk: 201 return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); 202 case nv_clk_src_hclkm3: 203 return clk->read(clk, nv_clk_src_hclk) * 3; 204 case nv_clk_src_hclkm3d2: 205 return clk->read(clk, nv_clk_src_hclk) * 3 / 2; 206 case nv_clk_src_host: 207 switch (mast & 0x30000000) { 208 case 0x00000000: return clk->read(clk, nv_clk_src_href); 209 case 0x10000000: break; 210 case 0x20000000: /* !0x50 */ 211 case 0x30000000: return clk->read(clk, nv_clk_src_hclk); 212 } 213 break; 214 case nv_clk_src_core: 215 if (!(mast & 0x00100000)) 216 P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16; 217 switch (mast & 0x00000003) { 218 case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; 219 case 0x00000001: return clk->read(clk, nv_clk_src_dom6); 220 case 0x00000002: return read_pll(priv, 0x004020) >> P; 221 case 0x00000003: return read_pll(priv, 0x004028) >> P; 222 } 223 break; 224 case nv_clk_src_shader: 225 P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16; 226 switch (mast & 0x00000030) { 227 case 0x00000000: 228 if (mast & 0x00000080) 229 return clk->read(clk, nv_clk_src_host) >> P; 230 return clk->read(clk, nv_clk_src_crystal) >> P; 231 case 0x00000010: break; 232 case 0x00000020: return read_pll(priv, 0x004028) >> P; 233 case 0x00000030: return read_pll(priv, 0x004020) >> P; 234 } 235 break; 236 case nv_clk_src_mem: 237 P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16; 238 if (nv_rd32(priv, 0x004008) & 0x00000200) { 239 switch (mast & 0x0000c000) { 240 case 0x00000000: 241 return clk->read(clk, nv_clk_src_crystal) >> P; 242 case 0x00008000: 243 case 0x0000c000: 244 return clk->read(clk, nv_clk_src_href) >> P; 245 } 246 } else { 247 return read_pll(priv, 0x004008) >> P; 248 } 249 break; 250 case nv_clk_src_vdec: 251 P = (read_div(priv) & 0x00000700) >> 8; 252 switch (nv_device(priv)->chipset) { 253 case 0x84: 254 case 0x86: 255 case 0x92: 256 case 0x94: 257 case 0x96: 258 case 0xa0: 259 switch (mast & 0x00000c00) { 260 case 0x00000000: 261 if (nv_device(priv)->chipset == 0xa0) /* wtf?? */ 262 return clk->read(clk, nv_clk_src_core) >> P; 263 return clk->read(clk, nv_clk_src_crystal) >> P; 264 case 0x00000400: 265 return 0; 266 case 0x00000800: 267 if (mast & 0x01000000) 268 return read_pll(priv, 0x004028) >> P; 269 return read_pll(priv, 0x004030) >> P; 270 case 0x00000c00: 271 return clk->read(clk, nv_clk_src_core) >> P; 272 } 273 break; 274 case 0x98: 275 switch (mast & 0x00000c00) { 276 case 0x00000000: 277 return clk->read(clk, nv_clk_src_core) >> P; 278 case 0x00000400: 279 return 0; 280 case 0x00000800: 281 return clk->read(clk, nv_clk_src_hclkm3d2) >> P; 282 case 0x00000c00: 283 return clk->read(clk, nv_clk_src_mem) >> P; 284 } 285 break; 286 } 287 break; 288 case nv_clk_src_dom6: 289 switch (nv_device(priv)->chipset) { 290 case 0x50: 291 case 0xa0: 292 return read_pll(priv, 0x00e810) >> 2; 293 case 0x84: 294 case 0x86: 295 case 0x92: 296 case 0x94: 297 case 0x96: 298 case 0x98: 299 P = (read_div(priv) & 0x00000007) >> 0; 300 switch (mast & 0x0c000000) { 301 case 0x00000000: return clk->read(clk, nv_clk_src_href); 302 case 0x04000000: break; 303 case 0x08000000: return clk->read(clk, nv_clk_src_hclk); 304 case 0x0c000000: 305 return clk->read(clk, nv_clk_src_hclkm3) >> P; 306 } 307 break; 308 default: 309 break; 310 } 311 default: 312 break; 313 } 314 315 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); 316 return -EINVAL; 317 } 318 319 static u32 320 calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) 321 { 322 struct nvkm_bios *bios = nvkm_bios(priv); 323 struct nvbios_pll pll; 324 int ret; 325 326 ret = nvbios_pll_parse(bios, reg, &pll); 327 if (ret) 328 return 0; 329 330 pll.vco2.max_freq = 0; 331 pll.refclk = read_pll_ref(priv, reg); 332 if (!pll.refclk) 333 return 0; 334 335 return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); 336 } 337 338 static inline u32 339 calc_div(u32 src, u32 target, int *div) 340 { 341 u32 clk0 = src, clk1 = src; 342 for (*div = 0; *div <= 7; (*div)++) { 343 if (clk0 <= target) { 344 clk1 = clk0 << (*div ? 1 : 0); 345 break; 346 } 347 clk0 >>= 1; 348 } 349 350 if (target - clk0 <= clk1 - target) 351 return clk0; 352 (*div)--; 353 return clk1; 354 } 355 356 static inline u32 357 clk_same(u32 a, u32 b) 358 { 359 return ((a / 1000) == (b / 1000)); 360 } 361 362 static int 363 nv50_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) 364 { 365 struct nv50_clk_priv *priv = (void *)clk; 366 struct nv50_clk_hwsq *hwsq = &priv->hwsq; 367 const int shader = cstate->domain[nv_clk_src_shader]; 368 const int core = cstate->domain[nv_clk_src_core]; 369 const int vdec = cstate->domain[nv_clk_src_vdec]; 370 const int dom6 = cstate->domain[nv_clk_src_dom6]; 371 u32 mastm = 0, mastv = 0; 372 u32 divsm = 0, divsv = 0; 373 int N, M, P1, P2; 374 int freq, out; 375 376 /* prepare a hwsq script from which we'll perform the reclock */ 377 out = clk_init(hwsq, nv_subdev(clk)); 378 if (out) 379 return out; 380 381 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ 382 clk_nsec(hwsq, 8000); 383 clk_setf(hwsq, 0x10, 0x00); /* disable fb */ 384 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 385 386 /* vdec: avoid modifying xpll until we know exactly how the other 387 * clock domains work, i suspect at least some of them can also be 388 * tied to xpll... 389 */ 390 if (vdec) { 391 /* see how close we can get using nvclk as a source */ 392 freq = calc_div(core, vdec, &P1); 393 394 /* see how close we can get using xpll/hclk as a source */ 395 if (nv_device(priv)->chipset != 0x98) 396 out = read_pll(priv, 0x004030); 397 else 398 out = clk->read(clk, nv_clk_src_hclkm3d2); 399 out = calc_div(out, vdec, &P2); 400 401 /* select whichever gets us closest */ 402 if (abs(vdec - freq) <= abs(vdec - out)) { 403 if (nv_device(priv)->chipset != 0x98) 404 mastv |= 0x00000c00; 405 divsv |= P1 << 8; 406 } else { 407 mastv |= 0x00000800; 408 divsv |= P2 << 8; 409 } 410 411 mastm |= 0x00000c00; 412 divsm |= 0x00000700; 413 } 414 415 /* dom6: nfi what this is, but we're limited to various combinations 416 * of the host clock frequency 417 */ 418 if (dom6) { 419 if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { 420 mastv |= 0x00000000; 421 } else 422 if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { 423 mastv |= 0x08000000; 424 } else { 425 freq = clk->read(clk, nv_clk_src_hclk) * 3; 426 freq = calc_div(freq, dom6, &P1); 427 428 mastv |= 0x0c000000; 429 divsv |= P1; 430 } 431 432 mastm |= 0x0c000000; 433 divsm |= 0x00000007; 434 } 435 436 /* vdec/dom6: switch to "safe" clocks temporarily, update dividers 437 * and then switch to target clocks 438 */ 439 clk_mask(hwsq, mast, mastm, 0x00000000); 440 clk_mask(hwsq, divs, divsm, divsv); 441 clk_mask(hwsq, mast, mastm, mastv); 442 443 /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, 444 * sclk to hclk) before reprogramming 445 */ 446 if (nv_device(priv)->chipset < 0x92) 447 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); 448 else 449 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); 450 451 /* core: for the moment at least, always use nvpll */ 452 freq = calc_pll(priv, 0x4028, core, &N, &M, &P1); 453 if (freq == 0) 454 return -ERANGE; 455 456 clk_mask(hwsq, nvpll[0], 0xc03f0100, 457 0x80000000 | (P1 << 19) | (P1 << 16)); 458 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); 459 460 /* shader: tie to nvclk if possible, otherwise use spll. have to be 461 * very careful that the shader clock is at least twice the core, or 462 * some chipsets will be very unhappy. i expect most or all of these 463 * cases will be handled by tying to nvclk, but it's possible there's 464 * corners 465 */ 466 if (P1-- && shader == (core << 1)) { 467 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); 468 clk_mask(hwsq, mast, 0x00100033, 0x00000023); 469 } else { 470 freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1); 471 if (freq == 0) 472 return -ERANGE; 473 474 clk_mask(hwsq, spll[0], 0xc03f0100, 475 0x80000000 | (P1 << 19) | (P1 << 16)); 476 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); 477 clk_mask(hwsq, mast, 0x00100033, 0x00000033); 478 } 479 480 /* restore normal operation */ 481 clk_setf(hwsq, 0x10, 0x01); /* enable fb */ 482 clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 483 clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ 484 return 0; 485 } 486 487 static int 488 nv50_clk_prog(struct nvkm_clk *clk) 489 { 490 struct nv50_clk_priv *priv = (void *)clk; 491 return clk_exec(&priv->hwsq, true); 492 } 493 494 static void 495 nv50_clk_tidy(struct nvkm_clk *clk) 496 { 497 struct nv50_clk_priv *priv = (void *)clk; 498 clk_exec(&priv->hwsq, false); 499 } 500 501 int 502 nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 503 struct nvkm_oclass *oclass, void *data, u32 size, 504 struct nvkm_object **pobject) 505 { 506 struct nv50_clk_oclass *pclass = (void *)oclass; 507 struct nv50_clk_priv *priv; 508 int ret; 509 510 ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, 511 NULL, 0, nv_device(parent)->chipset == 0xa0, 512 &priv); 513 *pobject = nv_object(priv); 514 if (ret) 515 return ret; 516 517 priv->hwsq.r_fifo = hwsq_reg(0x002504); 518 priv->hwsq.r_spll[0] = hwsq_reg(0x004020); 519 priv->hwsq.r_spll[1] = hwsq_reg(0x004024); 520 priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028); 521 priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); 522 switch (nv_device(priv)->chipset) { 523 case 0x92: 524 case 0x94: 525 case 0x96: 526 priv->hwsq.r_divs = hwsq_reg(0x004800); 527 break; 528 default: 529 priv->hwsq.r_divs = hwsq_reg(0x004700); 530 break; 531 } 532 priv->hwsq.r_mast = hwsq_reg(0x00c040); 533 534 priv->base.read = nv50_clk_read; 535 priv->base.calc = nv50_clk_calc; 536 priv->base.prog = nv50_clk_prog; 537 priv->base.tidy = nv50_clk_tidy; 538 return 0; 539 } 540 541 static struct nvkm_domain 542 nv50_domains[] = { 543 { nv_clk_src_crystal, 0xff }, 544 { nv_clk_src_href , 0xff }, 545 { nv_clk_src_core , 0xff, 0, "core", 1000 }, 546 { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, 547 { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, 548 { nv_clk_src_max } 549 }; 550 551 struct nvkm_oclass * 552 nv50_clk_oclass = &(struct nv50_clk_oclass) { 553 .base.handle = NV_SUBDEV(CLK, 0x50), 554 .base.ofuncs = &(struct nvkm_ofuncs) { 555 .ctor = nv50_clk_ctor, 556 .dtor = _nvkm_clk_dtor, 557 .init = _nvkm_clk_init, 558 .fini = _nvkm_clk_fini, 559 }, 560 .domains = nv50_domains, 561 }.base; 562