1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "pll.h" 26 #include "seq.h" 27 28 #include <subdev/bios.h> 29 #include <subdev/bios/pll.h> 30 31 static u32 32 read_div(struct nv50_clk *clk) 33 { 34 struct nvkm_device *device = clk->base.subdev.device; 35 switch (device->chipset) { 36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 37 case 0x84: 38 case 0x86: 39 case 0x98: 40 case 0xa0: 41 return nvkm_rd32(device, 0x004700); 42 case 0x92: 43 case 0x94: 44 case 0x96: 45 return nvkm_rd32(device, 0x004800); 46 default: 47 return 0x00000000; 48 } 49 } 50 51 static u32 52 read_pll_src(struct nv50_clk *clk, u32 base) 53 { 54 struct nvkm_device *device = clk->base.subdev.device; 55 u32 coef, ref = clk->base.read(&clk->base, nv_clk_src_crystal); 56 u32 rsel = nvkm_rd32(device, 0x00e18c); 57 int P, N, M, id; 58 59 switch (device->chipset) { 60 case 0x50: 61 case 0xa0: 62 switch (base) { 63 case 0x4020: 64 case 0x4028: id = !!(rsel & 0x00000004); break; 65 case 0x4008: id = !!(rsel & 0x00000008); break; 66 case 0x4030: id = 0; break; 67 default: 68 nv_error(clk, "ref: bad pll 0x%06x\n", base); 69 return 0; 70 } 71 72 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); 73 ref *= (coef & 0x01000000) ? 2 : 4; 74 P = (coef & 0x00070000) >> 16; 75 N = ((coef & 0x0000ff00) >> 8) + 1; 76 M = ((coef & 0x000000ff) >> 0) + 1; 77 break; 78 case 0x84: 79 case 0x86: 80 case 0x92: 81 coef = nvkm_rd32(device, 0x00e81c); 82 P = (coef & 0x00070000) >> 16; 83 N = (coef & 0x0000ff00) >> 8; 84 M = (coef & 0x000000ff) >> 0; 85 break; 86 case 0x94: 87 case 0x96: 88 case 0x98: 89 rsel = nvkm_rd32(device, 0x00c050); 90 switch (base) { 91 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; 92 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; 93 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; 94 case 0x4030: rsel = 3; break; 95 default: 96 nv_error(clk, "ref: bad pll 0x%06x\n", base); 97 return 0; 98 } 99 100 switch (rsel) { 101 case 0: id = 1; break; 102 case 1: return clk->base.read(&clk->base, nv_clk_src_crystal); 103 case 2: return clk->base.read(&clk->base, nv_clk_src_href); 104 case 3: id = 0; break; 105 } 106 107 coef = nvkm_rd32(device, 0x00e81c + (id * 0x28)); 108 P = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7; 109 P += (coef & 0x00070000) >> 16; 110 N = (coef & 0x0000ff00) >> 8; 111 M = (coef & 0x000000ff) >> 0; 112 break; 113 default: 114 BUG_ON(1); 115 } 116 117 if (M) 118 return (ref * N / M) >> P; 119 120 return 0; 121 } 122 123 static u32 124 read_pll_ref(struct nv50_clk *clk, u32 base) 125 { 126 struct nvkm_device *device = clk->base.subdev.device; 127 u32 src, mast = nvkm_rd32(device, 0x00c040); 128 129 switch (base) { 130 case 0x004028: 131 src = !!(mast & 0x00200000); 132 break; 133 case 0x004020: 134 src = !!(mast & 0x00400000); 135 break; 136 case 0x004008: 137 src = !!(mast & 0x00010000); 138 break; 139 case 0x004030: 140 src = !!(mast & 0x02000000); 141 break; 142 case 0x00e810: 143 return clk->base.read(&clk->base, nv_clk_src_crystal); 144 default: 145 nv_error(clk, "bad pll 0x%06x\n", base); 146 return 0; 147 } 148 149 if (src) 150 return clk->base.read(&clk->base, nv_clk_src_href); 151 152 return read_pll_src(clk, base); 153 } 154 155 static u32 156 read_pll(struct nv50_clk *clk, u32 base) 157 { 158 struct nvkm_device *device = clk->base.subdev.device; 159 u32 mast = nvkm_rd32(device, 0x00c040); 160 u32 ctrl = nvkm_rd32(device, base + 0); 161 u32 coef = nvkm_rd32(device, base + 4); 162 u32 ref = read_pll_ref(clk, base); 163 u32 freq = 0; 164 int N1, N2, M1, M2; 165 166 if (base == 0x004028 && (mast & 0x00100000)) { 167 /* wtf, appears to only disable post-divider on gt200 */ 168 if (device->chipset != 0xa0) 169 return clk->base.read(&clk->base, nv_clk_src_dom6); 170 } 171 172 N2 = (coef & 0xff000000) >> 24; 173 M2 = (coef & 0x00ff0000) >> 16; 174 N1 = (coef & 0x0000ff00) >> 8; 175 M1 = (coef & 0x000000ff); 176 if ((ctrl & 0x80000000) && M1) { 177 freq = ref * N1 / M1; 178 if ((ctrl & 0x40000100) == 0x40000000) { 179 if (M2) 180 freq = freq * N2 / M2; 181 else 182 freq = 0; 183 } 184 } 185 186 return freq; 187 } 188 189 static int 190 nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 191 { 192 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 193 struct nvkm_device *device = clk->base.subdev.device; 194 u32 mast = nvkm_rd32(device, 0x00c040); 195 u32 P = 0; 196 197 switch (src) { 198 case nv_clk_src_crystal: 199 return device->crystal; 200 case nv_clk_src_href: 201 return 100000; /* PCIE reference clock */ 202 case nv_clk_src_hclk: 203 return div_u64((u64)clk->base.read(&clk->base, nv_clk_src_href) * 27778, 10000); 204 case nv_clk_src_hclkm3: 205 return clk->base.read(&clk->base, nv_clk_src_hclk) * 3; 206 case nv_clk_src_hclkm3d2: 207 return clk->base.read(&clk->base, nv_clk_src_hclk) * 3 / 2; 208 case nv_clk_src_host: 209 switch (mast & 0x30000000) { 210 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_href); 211 case 0x10000000: break; 212 case 0x20000000: /* !0x50 */ 213 case 0x30000000: return clk->base.read(&clk->base, nv_clk_src_hclk); 214 } 215 break; 216 case nv_clk_src_core: 217 if (!(mast & 0x00100000)) 218 P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; 219 switch (mast & 0x00000003) { 220 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 221 case 0x00000001: return clk->base.read(&clk->base, nv_clk_src_dom6); 222 case 0x00000002: return read_pll(clk, 0x004020) >> P; 223 case 0x00000003: return read_pll(clk, 0x004028) >> P; 224 } 225 break; 226 case nv_clk_src_shader: 227 P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; 228 switch (mast & 0x00000030) { 229 case 0x00000000: 230 if (mast & 0x00000080) 231 return clk->base.read(&clk->base, nv_clk_src_host) >> P; 232 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 233 case 0x00000010: break; 234 case 0x00000020: return read_pll(clk, 0x004028) >> P; 235 case 0x00000030: return read_pll(clk, 0x004020) >> P; 236 } 237 break; 238 case nv_clk_src_mem: 239 P = (nvkm_rd32(device, 0x004008) & 0x00070000) >> 16; 240 if (nvkm_rd32(device, 0x004008) & 0x00000200) { 241 switch (mast & 0x0000c000) { 242 case 0x00000000: 243 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 244 case 0x00008000: 245 case 0x0000c000: 246 return clk->base.read(&clk->base, nv_clk_src_href) >> P; 247 } 248 } else { 249 return read_pll(clk, 0x004008) >> P; 250 } 251 break; 252 case nv_clk_src_vdec: 253 P = (read_div(clk) & 0x00000700) >> 8; 254 switch (device->chipset) { 255 case 0x84: 256 case 0x86: 257 case 0x92: 258 case 0x94: 259 case 0x96: 260 case 0xa0: 261 switch (mast & 0x00000c00) { 262 case 0x00000000: 263 if (device->chipset == 0xa0) /* wtf?? */ 264 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 265 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 266 case 0x00000400: 267 return 0; 268 case 0x00000800: 269 if (mast & 0x01000000) 270 return read_pll(clk, 0x004028) >> P; 271 return read_pll(clk, 0x004030) >> P; 272 case 0x00000c00: 273 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 274 } 275 break; 276 case 0x98: 277 switch (mast & 0x00000c00) { 278 case 0x00000000: 279 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 280 case 0x00000400: 281 return 0; 282 case 0x00000800: 283 return clk->base.read(&clk->base, nv_clk_src_hclkm3d2) >> P; 284 case 0x00000c00: 285 return clk->base.read(&clk->base, nv_clk_src_mem) >> P; 286 } 287 break; 288 } 289 break; 290 case nv_clk_src_dom6: 291 switch (device->chipset) { 292 case 0x50: 293 case 0xa0: 294 return read_pll(clk, 0x00e810) >> 2; 295 case 0x84: 296 case 0x86: 297 case 0x92: 298 case 0x94: 299 case 0x96: 300 case 0x98: 301 P = (read_div(clk) & 0x00000007) >> 0; 302 switch (mast & 0x0c000000) { 303 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_href); 304 case 0x04000000: break; 305 case 0x08000000: return clk->base.read(&clk->base, nv_clk_src_hclk); 306 case 0x0c000000: 307 return clk->base.read(&clk->base, nv_clk_src_hclkm3) >> P; 308 } 309 break; 310 default: 311 break; 312 } 313 default: 314 break; 315 } 316 317 nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast); 318 return -EINVAL; 319 } 320 321 static u32 322 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P) 323 { 324 struct nvkm_bios *bios = nvkm_bios(clk); 325 struct nvbios_pll pll; 326 int ret; 327 328 ret = nvbios_pll_parse(bios, reg, &pll); 329 if (ret) 330 return 0; 331 332 pll.vco2.max_freq = 0; 333 pll.refclk = read_pll_ref(clk, reg); 334 if (!pll.refclk) 335 return 0; 336 337 return nv04_pll_calc(nv_subdev(clk), &pll, idx, N, M, NULL, NULL, P); 338 } 339 340 static inline u32 341 calc_div(u32 src, u32 target, int *div) 342 { 343 u32 clk0 = src, clk1 = src; 344 for (*div = 0; *div <= 7; (*div)++) { 345 if (clk0 <= target) { 346 clk1 = clk0 << (*div ? 1 : 0); 347 break; 348 } 349 clk0 >>= 1; 350 } 351 352 if (target - clk0 <= clk1 - target) 353 return clk0; 354 (*div)--; 355 return clk1; 356 } 357 358 static inline u32 359 clk_same(u32 a, u32 b) 360 { 361 return ((a / 1000) == (b / 1000)); 362 } 363 364 static int 365 nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 366 { 367 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 368 struct nv50_clk_hwsq *hwsq = &clk->hwsq; 369 const int shader = cstate->domain[nv_clk_src_shader]; 370 const int core = cstate->domain[nv_clk_src_core]; 371 const int vdec = cstate->domain[nv_clk_src_vdec]; 372 const int dom6 = cstate->domain[nv_clk_src_dom6]; 373 u32 mastm = 0, mastv = 0; 374 u32 divsm = 0, divsv = 0; 375 int N, M, P1, P2; 376 int freq, out; 377 378 /* prepare a hwsq script from which we'll perform the reclock */ 379 out = clk_init(hwsq, nv_subdev(clk)); 380 if (out) 381 return out; 382 383 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ 384 clk_nsec(hwsq, 8000); 385 clk_setf(hwsq, 0x10, 0x00); /* disable fb */ 386 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 387 388 /* vdec: avoid modifying xpll until we know exactly how the other 389 * clock domains work, i suspect at least some of them can also be 390 * tied to xpll... 391 */ 392 if (vdec) { 393 /* see how close we can get using nvclk as a source */ 394 freq = calc_div(core, vdec, &P1); 395 396 /* see how close we can get using xpll/hclk as a source */ 397 if (nv_device(clk)->chipset != 0x98) 398 out = read_pll(clk, 0x004030); 399 else 400 out = clk->base.read(&clk->base, nv_clk_src_hclkm3d2); 401 out = calc_div(out, vdec, &P2); 402 403 /* select whichever gets us closest */ 404 if (abs(vdec - freq) <= abs(vdec - out)) { 405 if (nv_device(clk)->chipset != 0x98) 406 mastv |= 0x00000c00; 407 divsv |= P1 << 8; 408 } else { 409 mastv |= 0x00000800; 410 divsv |= P2 << 8; 411 } 412 413 mastm |= 0x00000c00; 414 divsm |= 0x00000700; 415 } 416 417 /* dom6: nfi what this is, but we're limited to various combinations 418 * of the host clock frequency 419 */ 420 if (dom6) { 421 if (clk_same(dom6, clk->base.read(&clk->base, nv_clk_src_href))) { 422 mastv |= 0x00000000; 423 } else 424 if (clk_same(dom6, clk->base.read(&clk->base, nv_clk_src_hclk))) { 425 mastv |= 0x08000000; 426 } else { 427 freq = clk->base.read(&clk->base, nv_clk_src_hclk) * 3; 428 calc_div(freq, dom6, &P1); 429 430 mastv |= 0x0c000000; 431 divsv |= P1; 432 } 433 434 mastm |= 0x0c000000; 435 divsm |= 0x00000007; 436 } 437 438 /* vdec/dom6: switch to "safe" clocks temporarily, update dividers 439 * and then switch to target clocks 440 */ 441 clk_mask(hwsq, mast, mastm, 0x00000000); 442 clk_mask(hwsq, divs, divsm, divsv); 443 clk_mask(hwsq, mast, mastm, mastv); 444 445 /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, 446 * sclk to hclk) before reprogramming 447 */ 448 if (nv_device(clk)->chipset < 0x92) 449 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); 450 else 451 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); 452 453 /* core: for the moment at least, always use nvpll */ 454 freq = calc_pll(clk, 0x4028, core, &N, &M, &P1); 455 if (freq == 0) 456 return -ERANGE; 457 458 clk_mask(hwsq, nvpll[0], 0xc03f0100, 459 0x80000000 | (P1 << 19) | (P1 << 16)); 460 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); 461 462 /* shader: tie to nvclk if possible, otherwise use spll. have to be 463 * very careful that the shader clock is at least twice the core, or 464 * some chipsets will be very unhappy. i expect most or all of these 465 * cases will be handled by tying to nvclk, but it's possible there's 466 * corners 467 */ 468 if (P1-- && shader == (core << 1)) { 469 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); 470 clk_mask(hwsq, mast, 0x00100033, 0x00000023); 471 } else { 472 freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1); 473 if (freq == 0) 474 return -ERANGE; 475 476 clk_mask(hwsq, spll[0], 0xc03f0100, 477 0x80000000 | (P1 << 19) | (P1 << 16)); 478 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); 479 clk_mask(hwsq, mast, 0x00100033, 0x00000033); 480 } 481 482 /* restore normal operation */ 483 clk_setf(hwsq, 0x10, 0x01); /* enable fb */ 484 clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 485 clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ 486 return 0; 487 } 488 489 static int 490 nv50_clk_prog(struct nvkm_clk *obj) 491 { 492 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 493 return clk_exec(&clk->hwsq, true); 494 } 495 496 static void 497 nv50_clk_tidy(struct nvkm_clk *obj) 498 { 499 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 500 clk_exec(&clk->hwsq, false); 501 } 502 503 int 504 nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 505 struct nvkm_oclass *oclass, void *data, u32 size, 506 struct nvkm_object **pobject) 507 { 508 struct nv50_clk_oclass *pclass = (void *)oclass; 509 struct nv50_clk *clk; 510 int ret; 511 512 ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, 513 NULL, 0, nv_device(parent)->chipset == 0xa0, 514 &clk); 515 *pobject = nv_object(clk); 516 if (ret) 517 return ret; 518 519 clk->hwsq.r_fifo = hwsq_reg(0x002504); 520 clk->hwsq.r_spll[0] = hwsq_reg(0x004020); 521 clk->hwsq.r_spll[1] = hwsq_reg(0x004024); 522 clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028); 523 clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); 524 switch (nv_device(clk)->chipset) { 525 case 0x92: 526 case 0x94: 527 case 0x96: 528 clk->hwsq.r_divs = hwsq_reg(0x004800); 529 break; 530 default: 531 clk->hwsq.r_divs = hwsq_reg(0x004700); 532 break; 533 } 534 clk->hwsq.r_mast = hwsq_reg(0x00c040); 535 536 clk->base.read = nv50_clk_read; 537 clk->base.calc = nv50_clk_calc; 538 clk->base.prog = nv50_clk_prog; 539 clk->base.tidy = nv50_clk_tidy; 540 return 0; 541 } 542 543 static struct nvkm_domain 544 nv50_domains[] = { 545 { nv_clk_src_crystal, 0xff }, 546 { nv_clk_src_href , 0xff }, 547 { nv_clk_src_core , 0xff, 0, "core", 1000 }, 548 { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, 549 { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, 550 { nv_clk_src_max } 551 }; 552 553 struct nvkm_oclass * 554 nv50_clk_oclass = &(struct nv50_clk_oclass) { 555 .base.handle = NV_SUBDEV(CLK, 0x50), 556 .base.ofuncs = &(struct nvkm_ofuncs) { 557 .ctor = nv50_clk_ctor, 558 .dtor = _nvkm_clk_dtor, 559 .init = _nvkm_clk_init, 560 .fini = _nvkm_clk_fini, 561 }, 562 .domains = nv50_domains, 563 }.base; 564