1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/clk.h> 25 #include "pll.h" 26 27 #include <subdev/bios.h> 28 #include <subdev/bios/pll.h> 29 30 struct nv40_clk { 31 struct nvkm_clk base; 32 u32 ctrl; 33 u32 npll_ctrl; 34 u32 npll_coef; 35 u32 spll; 36 }; 37 38 static struct nvkm_domain 39 nv40_domain[] = { 40 { nv_clk_src_crystal, 0xff }, 41 { nv_clk_src_href , 0xff }, 42 { nv_clk_src_core , 0xff, 0, "core", 1000 }, 43 { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, 44 { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, 45 { nv_clk_src_max } 46 }; 47 48 static u32 49 read_pll_1(struct nv40_clk *clk, u32 reg) 50 { 51 u32 ctrl = nv_rd32(clk, reg + 0x00); 52 int P = (ctrl & 0x00070000) >> 16; 53 int N = (ctrl & 0x0000ff00) >> 8; 54 int M = (ctrl & 0x000000ff) >> 0; 55 u32 ref = 27000, khz = 0; 56 57 if (ctrl & 0x80000000) 58 khz = ref * N / M; 59 60 return khz >> P; 61 } 62 63 static u32 64 read_pll_2(struct nv40_clk *clk, u32 reg) 65 { 66 u32 ctrl = nv_rd32(clk, reg + 0x00); 67 u32 coef = nv_rd32(clk, reg + 0x04); 68 int N2 = (coef & 0xff000000) >> 24; 69 int M2 = (coef & 0x00ff0000) >> 16; 70 int N1 = (coef & 0x0000ff00) >> 8; 71 int M1 = (coef & 0x000000ff) >> 0; 72 int P = (ctrl & 0x00070000) >> 16; 73 u32 ref = 27000, khz = 0; 74 75 if ((ctrl & 0x80000000) && M1) { 76 khz = ref * N1 / M1; 77 if ((ctrl & 0x40000100) == 0x40000000) { 78 if (M2) 79 khz = khz * N2 / M2; 80 else 81 khz = 0; 82 } 83 } 84 85 return khz >> P; 86 } 87 88 static u32 89 read_clk(struct nv40_clk *clk, u32 src) 90 { 91 switch (src) { 92 case 3: 93 return read_pll_2(clk, 0x004000); 94 case 2: 95 return read_pll_1(clk, 0x004008); 96 default: 97 break; 98 } 99 100 return 0; 101 } 102 103 static int 104 nv40_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 105 { 106 struct nv40_clk *clk = container_of(obj, typeof(*clk), base); 107 u32 mast = nv_rd32(clk, 0x00c040); 108 109 switch (src) { 110 case nv_clk_src_crystal: 111 return nv_device(clk)->crystal; 112 case nv_clk_src_href: 113 return 100000; /*XXX: PCIE/AGP differ*/ 114 case nv_clk_src_core: 115 return read_clk(clk, (mast & 0x00000003) >> 0); 116 case nv_clk_src_shader: 117 return read_clk(clk, (mast & 0x00000030) >> 4); 118 case nv_clk_src_mem: 119 return read_pll_2(clk, 0x4020); 120 default: 121 break; 122 } 123 124 nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast); 125 return -EINVAL; 126 } 127 128 static int 129 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, 130 int *N1, int *M1, int *N2, int *M2, int *log2P) 131 { 132 struct nvkm_bios *bios = nvkm_bios(clk); 133 struct nvbios_pll pll; 134 int ret; 135 136 ret = nvbios_pll_parse(bios, reg, &pll); 137 if (ret) 138 return ret; 139 140 if (khz < pll.vco1.max_freq) 141 pll.vco2.max_freq = 0; 142 143 ret = nv04_pll_calc(nv_subdev(clk), &pll, khz, N1, M1, N2, M2, log2P); 144 if (ret == 0) 145 return -ERANGE; 146 147 return ret; 148 } 149 150 static int 151 nv40_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 152 { 153 struct nv40_clk *clk = container_of(obj, typeof(*clk), base); 154 int gclk = cstate->domain[nv_clk_src_core]; 155 int sclk = cstate->domain[nv_clk_src_shader]; 156 int N1, M1, N2, M2, log2P; 157 int ret; 158 159 /* core/geometric clock */ 160 ret = nv40_clk_calc_pll(clk, 0x004000, gclk, 161 &N1, &M1, &N2, &M2, &log2P); 162 if (ret < 0) 163 return ret; 164 165 if (N2 == M2) { 166 clk->npll_ctrl = 0x80000100 | (log2P << 16); 167 clk->npll_coef = (N1 << 8) | M1; 168 } else { 169 clk->npll_ctrl = 0xc0000000 | (log2P << 16); 170 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; 171 } 172 173 /* use the second pll for shader/rop clock, if it differs from core */ 174 if (sclk && sclk != gclk) { 175 ret = nv40_clk_calc_pll(clk, 0x004008, sclk, 176 &N1, &M1, NULL, NULL, &log2P); 177 if (ret < 0) 178 return ret; 179 180 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; 181 clk->ctrl = 0x00000223; 182 } else { 183 clk->spll = 0x00000000; 184 clk->ctrl = 0x00000333; 185 } 186 187 return 0; 188 } 189 190 static int 191 nv40_clk_prog(struct nvkm_clk *obj) 192 { 193 struct nv40_clk *clk = container_of(obj, typeof(*clk), base); 194 nv_mask(clk, 0x00c040, 0x00000333, 0x00000000); 195 nv_wr32(clk, 0x004004, clk->npll_coef); 196 nv_mask(clk, 0x004000, 0xc0070100, clk->npll_ctrl); 197 nv_mask(clk, 0x004008, 0xc007ffff, clk->spll); 198 mdelay(5); 199 nv_mask(clk, 0x00c040, 0x00000333, clk->ctrl); 200 return 0; 201 } 202 203 static void 204 nv40_clk_tidy(struct nvkm_clk *obj) 205 { 206 } 207 208 static int 209 nv40_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 210 struct nvkm_oclass *oclass, void *data, u32 size, 211 struct nvkm_object **pobject) 212 { 213 struct nv40_clk *clk; 214 int ret; 215 216 ret = nvkm_clk_create(parent, engine, oclass, nv40_domain, 217 NULL, 0, true, &clk); 218 *pobject = nv_object(clk); 219 if (ret) 220 return ret; 221 222 clk->base.pll_calc = nv04_clk_pll_calc; 223 clk->base.pll_prog = nv04_clk_pll_prog; 224 clk->base.read = nv40_clk_read; 225 clk->base.calc = nv40_clk_calc; 226 clk->base.prog = nv40_clk_prog; 227 clk->base.tidy = nv40_clk_tidy; 228 return 0; 229 } 230 231 struct nvkm_oclass 232 nv40_clk_oclass = { 233 .handle = NV_SUBDEV(CLK, 0x40), 234 .ofuncs = &(struct nvkm_ofuncs) { 235 .ctor = nv40_clk_ctor, 236 .dtor = _nvkm_clk_dtor, 237 .init = _nvkm_clk_init, 238 .fini = _nvkm_clk_fini, 239 }, 240 }; 241