1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * Roy Spliet 24 */ 25 #include "gt215.h" 26 #include "pll.h" 27 28 #include <engine/fifo.h> 29 #include <subdev/bios.h> 30 #include <subdev/bios/pll.h> 31 #include <subdev/timer.h> 32 33 struct gt215_clk_priv { 34 struct nvkm_clk base; 35 struct gt215_clk_info eng[nv_clk_src_max]; 36 }; 37 38 static u32 read_clk(struct gt215_clk_priv *, int, bool); 39 static u32 read_pll(struct gt215_clk_priv *, int, u32); 40 41 static u32 42 read_vco(struct gt215_clk_priv *priv, int clk) 43 { 44 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); 45 46 switch (sctl & 0x00000030) { 47 case 0x00000000: 48 return nv_device(priv)->crystal; 49 case 0x00000020: 50 return read_pll(priv, 0x41, 0x00e820); 51 case 0x00000030: 52 return read_pll(priv, 0x42, 0x00e8a0); 53 default: 54 return 0; 55 } 56 } 57 58 static u32 59 read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en) 60 { 61 u32 sctl, sdiv, sclk; 62 63 /* refclk for the 0xe8xx plls is a fixed frequency */ 64 if (clk >= 0x40) { 65 if (nv_device(priv)->chipset == 0xaf) { 66 /* no joke.. seriously.. sigh.. */ 67 return nv_rd32(priv, 0x00471c) * 1000; 68 } 69 70 return nv_device(priv)->crystal; 71 } 72 73 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); 74 if (!ignore_en && !(sctl & 0x00000100)) 75 return 0; 76 77 /* out_alt */ 78 if (sctl & 0x00000400) 79 return 108000; 80 81 /* vco_out */ 82 switch (sctl & 0x00003000) { 83 case 0x00000000: 84 if (!(sctl & 0x00000200)) 85 return nv_device(priv)->crystal; 86 return 0; 87 case 0x00002000: 88 if (sctl & 0x00000040) 89 return 108000; 90 return 100000; 91 case 0x00003000: 92 /* vco_enable */ 93 if (!(sctl & 0x00000001)) 94 return 0; 95 96 sclk = read_vco(priv, clk); 97 sdiv = ((sctl & 0x003f0000) >> 16) + 2; 98 return (sclk * 2) / sdiv; 99 default: 100 return 0; 101 } 102 } 103 104 static u32 105 read_pll(struct gt215_clk_priv *priv, int clk, u32 pll) 106 { 107 u32 ctrl = nv_rd32(priv, pll + 0); 108 u32 sclk = 0, P = 1, N = 1, M = 1; 109 110 if (!(ctrl & 0x00000008)) { 111 if (ctrl & 0x00000001) { 112 u32 coef = nv_rd32(priv, pll + 4); 113 M = (coef & 0x000000ff) >> 0; 114 N = (coef & 0x0000ff00) >> 8; 115 P = (coef & 0x003f0000) >> 16; 116 117 /* no post-divider on these.. 118 * XXX: it looks more like two post-"dividers" that 119 * cross each other out in the default RPLL config */ 120 if ((pll & 0x00ff00) == 0x00e800) 121 P = 1; 122 123 sclk = read_clk(priv, 0x00 + clk, false); 124 } 125 } else { 126 sclk = read_clk(priv, 0x10 + clk, false); 127 } 128 129 if (M * P) 130 return sclk * N / (M * P); 131 132 return 0; 133 } 134 135 static int 136 gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) 137 { 138 struct gt215_clk_priv *priv = (void *)clk; 139 u32 hsrc; 140 141 switch (src) { 142 case nv_clk_src_crystal: 143 return nv_device(priv)->crystal; 144 case nv_clk_src_core: 145 case nv_clk_src_core_intm: 146 return read_pll(priv, 0x00, 0x4200); 147 case nv_clk_src_shader: 148 return read_pll(priv, 0x01, 0x4220); 149 case nv_clk_src_mem: 150 return read_pll(priv, 0x02, 0x4000); 151 case nv_clk_src_disp: 152 return read_clk(priv, 0x20, false); 153 case nv_clk_src_vdec: 154 return read_clk(priv, 0x21, false); 155 case nv_clk_src_daemon: 156 return read_clk(priv, 0x25, false); 157 case nv_clk_src_host: 158 hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; 159 switch (hsrc) { 160 case 0: 161 return read_clk(priv, 0x1d, false); 162 case 2: 163 case 3: 164 return 277000; 165 default: 166 nv_error(clk, "unknown HOST clock source %d\n", hsrc); 167 return -EINVAL; 168 } 169 default: 170 nv_error(clk, "invalid clock source %d\n", src); 171 return -EINVAL; 172 } 173 174 return 0; 175 } 176 177 int 178 gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz, 179 struct gt215_clk_info *info) 180 { 181 struct gt215_clk_priv *priv = (void *)clock; 182 u32 oclk, sclk, sdiv, diff; 183 184 info->clk = 0; 185 186 switch (khz) { 187 case 27000: 188 info->clk = 0x00000100; 189 return khz; 190 case 100000: 191 info->clk = 0x00002100; 192 return khz; 193 case 108000: 194 info->clk = 0x00002140; 195 return khz; 196 default: 197 sclk = read_vco(priv, clk); 198 sdiv = min((sclk * 2) / khz, (u32)65); 199 oclk = (sclk * 2) / sdiv; 200 diff = ((khz + 3000) - oclk); 201 202 /* When imprecise, play it safe and aim for a clock lower than 203 * desired rather than higher */ 204 if (diff < 0) { 205 sdiv++; 206 oclk = (sclk * 2) / sdiv; 207 } 208 209 /* divider can go as low as 2, limited here because NVIDIA 210 * and the VBIOS on my NVA8 seem to prefer using the PLL 211 * for 810MHz - is there a good reason? 212 * XXX: PLLs with refclk 810MHz? */ 213 if (sdiv > 4) { 214 info->clk = (((sdiv - 2) << 16) | 0x00003100); 215 return oclk; 216 } 217 218 break; 219 } 220 221 return -ERANGE; 222 } 223 224 int 225 gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz, 226 struct gt215_clk_info *info) 227 { 228 struct nvkm_bios *bios = nvkm_bios(clock); 229 struct gt215_clk_priv *priv = (void *)clock; 230 struct nvbios_pll limits; 231 int P, N, M, diff; 232 int ret; 233 234 info->pll = 0; 235 236 /* If we can get a within [-2, 3) MHz of a divider, we'll disable the 237 * PLL and use the divider instead. */ 238 ret = gt215_clk_info(clock, clk, khz, info); 239 diff = khz - ret; 240 if (!pll || (diff >= -2000 && diff < 3000)) { 241 goto out; 242 } 243 244 /* Try with PLL */ 245 ret = nvbios_pll_parse(bios, pll, &limits); 246 if (ret) 247 return ret; 248 249 ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info); 250 if (ret != limits.refclk) 251 return -EINVAL; 252 253 ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); 254 if (ret >= 0) { 255 info->pll = (P << 16) | (N << 8) | M; 256 } 257 258 out: 259 info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); 260 return ret ? ret : -ERANGE; 261 } 262 263 static int 264 calc_clk(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate, 265 int clk, u32 pll, int idx) 266 { 267 int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx], 268 &priv->eng[idx]); 269 if (ret >= 0) 270 return 0; 271 return ret; 272 } 273 274 static int 275 calc_host(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate) 276 { 277 int ret = 0; 278 u32 kHz = cstate->domain[nv_clk_src_host]; 279 struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; 280 281 if (kHz == 277000) { 282 info->clk = 0; 283 info->host_out = NVA3_HOST_277; 284 return 0; 285 } 286 287 info->host_out = NVA3_HOST_CLK; 288 289 ret = gt215_clk_info(&priv->base, 0x1d, kHz, info); 290 if (ret >= 0) 291 return 0; 292 293 return ret; 294 } 295 296 int 297 gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) 298 { 299 struct nvkm_fifo *pfifo = nvkm_fifo(clk); 300 301 /* halt and idle execution engines */ 302 nv_mask(clk, 0x020060, 0x00070000, 0x00000000); 303 nv_mask(clk, 0x002504, 0x00000001, 0x00000001); 304 /* Wait until the interrupt handler is finished */ 305 if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) 306 return -EBUSY; 307 308 if (pfifo) 309 pfifo->pause(pfifo, flags); 310 311 if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) 312 return -EIO; 313 if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) 314 return -EIO; 315 316 return 0; 317 } 318 319 void 320 gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) 321 { 322 struct nvkm_fifo *pfifo = nvkm_fifo(clk); 323 324 if (pfifo && flags) 325 pfifo->start(pfifo, flags); 326 327 nv_mask(clk, 0x002504, 0x00000001, 0x00000000); 328 nv_mask(clk, 0x020060, 0x00070000, 0x00040000); 329 } 330 331 static void 332 disable_clk_src(struct gt215_clk_priv *priv, u32 src) 333 { 334 nv_mask(priv, src, 0x00000100, 0x00000000); 335 nv_mask(priv, src, 0x00000001, 0x00000000); 336 } 337 338 static void 339 prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx) 340 { 341 struct gt215_clk_info *info = &priv->eng[idx]; 342 const u32 src0 = 0x004120 + (clk * 4); 343 const u32 src1 = 0x004160 + (clk * 4); 344 const u32 ctrl = pll + 0; 345 const u32 coef = pll + 4; 346 u32 bypass; 347 348 if (info->pll) { 349 /* Always start from a non-PLL clock */ 350 bypass = nv_rd32(priv, ctrl) & 0x00000008; 351 if (!bypass) { 352 nv_mask(priv, src1, 0x00000101, 0x00000101); 353 nv_mask(priv, ctrl, 0x00000008, 0x00000008); 354 udelay(20); 355 } 356 357 nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); 358 nv_wr32(priv, coef, info->pll); 359 nv_mask(priv, ctrl, 0x00000015, 0x00000015); 360 nv_mask(priv, ctrl, 0x00000010, 0x00000000); 361 if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { 362 nv_mask(priv, ctrl, 0x00000010, 0x00000010); 363 nv_mask(priv, src0, 0x00000101, 0x00000000); 364 return; 365 } 366 nv_mask(priv, ctrl, 0x00000010, 0x00000010); 367 nv_mask(priv, ctrl, 0x00000008, 0x00000000); 368 disable_clk_src(priv, src1); 369 } else { 370 nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); 371 nv_mask(priv, ctrl, 0x00000018, 0x00000018); 372 udelay(20); 373 nv_mask(priv, ctrl, 0x00000001, 0x00000000); 374 disable_clk_src(priv, src0); 375 } 376 } 377 378 static void 379 prog_clk(struct gt215_clk_priv *priv, int clk, int idx) 380 { 381 struct gt215_clk_info *info = &priv->eng[idx]; 382 nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); 383 } 384 385 static void 386 prog_host(struct gt215_clk_priv *priv) 387 { 388 struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; 389 u32 hsrc = (nv_rd32(priv, 0xc040)); 390 391 switch (info->host_out) { 392 case NVA3_HOST_277: 393 if ((hsrc & 0x30000000) == 0) { 394 nv_wr32(priv, 0xc040, hsrc | 0x20000000); 395 disable_clk_src(priv, 0x4194); 396 } 397 break; 398 case NVA3_HOST_CLK: 399 prog_clk(priv, 0x1d, nv_clk_src_host); 400 if ((hsrc & 0x30000000) >= 0x20000000) { 401 nv_wr32(priv, 0xc040, hsrc & ~0x30000000); 402 } 403 break; 404 default: 405 break; 406 } 407 408 /* This seems to be a clock gating factor on idle, always set to 64 */ 409 nv_wr32(priv, 0xc044, 0x3e); 410 } 411 412 static void 413 prog_core(struct gt215_clk_priv *priv, int idx) 414 { 415 struct gt215_clk_info *info = &priv->eng[idx]; 416 u32 fb_delay = nv_rd32(priv, 0x10002c); 417 418 if (fb_delay < info->fb_delay) 419 nv_wr32(priv, 0x10002c, info->fb_delay); 420 421 prog_pll(priv, 0x00, 0x004200, idx); 422 423 if (fb_delay > info->fb_delay) 424 nv_wr32(priv, 0x10002c, info->fb_delay); 425 } 426 427 static int 428 gt215_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) 429 { 430 struct gt215_clk_priv *priv = (void *)clk; 431 struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; 432 int ret; 433 434 if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || 435 (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || 436 (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || 437 (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || 438 (ret = calc_host(priv, cstate))) 439 return ret; 440 441 /* XXX: Should be reading the highest bit in the VBIOS clock to decide 442 * whether to use a PLL or not... but using a PLL defeats the purpose */ 443 if (core->pll) { 444 ret = gt215_clk_info(clk, 0x10, 445 cstate->domain[nv_clk_src_core_intm], 446 &priv->eng[nv_clk_src_core_intm]); 447 if (ret < 0) 448 return ret; 449 } 450 451 return 0; 452 } 453 454 static int 455 gt215_clk_prog(struct nvkm_clk *clk) 456 { 457 struct gt215_clk_priv *priv = (void *)clk; 458 struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; 459 int ret = 0; 460 unsigned long flags; 461 unsigned long *f = &flags; 462 463 ret = gt215_clk_pre(clk, f); 464 if (ret) 465 goto out; 466 467 if (core->pll) 468 prog_core(priv, nv_clk_src_core_intm); 469 470 prog_core(priv, nv_clk_src_core); 471 prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); 472 prog_clk(priv, 0x20, nv_clk_src_disp); 473 prog_clk(priv, 0x21, nv_clk_src_vdec); 474 prog_host(priv); 475 476 out: 477 if (ret == -EBUSY) 478 f = NULL; 479 480 gt215_clk_post(clk, f); 481 return ret; 482 } 483 484 static void 485 gt215_clk_tidy(struct nvkm_clk *clk) 486 { 487 } 488 489 static struct nvkm_domain 490 gt215_domain[] = { 491 { nv_clk_src_crystal , 0xff }, 492 { nv_clk_src_core , 0x00, 0, "core", 1000 }, 493 { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, 494 { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, 495 { nv_clk_src_vdec , 0x03 }, 496 { nv_clk_src_disp , 0x04 }, 497 { nv_clk_src_host , 0x05 }, 498 { nv_clk_src_core_intm, 0x06 }, 499 { nv_clk_src_max } 500 }; 501 502 static int 503 gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 504 struct nvkm_oclass *oclass, void *data, u32 size, 505 struct nvkm_object **pobject) 506 { 507 struct gt215_clk_priv *priv; 508 int ret; 509 510 ret = nvkm_clk_create(parent, engine, oclass, gt215_domain, 511 NULL, 0, true, &priv); 512 *pobject = nv_object(priv); 513 if (ret) 514 return ret; 515 516 priv->base.read = gt215_clk_read; 517 priv->base.calc = gt215_clk_calc; 518 priv->base.prog = gt215_clk_prog; 519 priv->base.tidy = gt215_clk_tidy; 520 return 0; 521 } 522 523 struct nvkm_oclass 524 gt215_clk_oclass = { 525 .handle = NV_SUBDEV(CLK, 0xa3), 526 .ofuncs = &(struct nvkm_ofuncs) { 527 .ctor = gt215_clk_ctor, 528 .dtor = _nvkm_clk_dtor, 529 .init = _nvkm_clk_init, 530 .fini = _nvkm_clk_fini, 531 }, 532 }; 533