1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * Roy Spliet 24 */ 25 #include "gt215.h" 26 #include "pll.h" 27 28 #include <engine/fifo.h> 29 #include <subdev/bios.h> 30 #include <subdev/bios/pll.h> 31 #include <subdev/timer.h> 32 33 struct gt215_clk { 34 struct nvkm_clk base; 35 struct gt215_clk_info eng[nv_clk_src_max]; 36 }; 37 38 static u32 read_clk(struct gt215_clk *, int, bool); 39 static u32 read_pll(struct gt215_clk *, int, u32); 40 41 static u32 42 read_vco(struct gt215_clk *clk, int idx) 43 { 44 struct nvkm_device *device = clk->base.subdev.device; 45 u32 sctl = nvkm_rd32(device, 0x4120 + (idx * 4)); 46 47 switch (sctl & 0x00000030) { 48 case 0x00000000: 49 return device->crystal; 50 case 0x00000020: 51 return read_pll(clk, 0x41, 0x00e820); 52 case 0x00000030: 53 return read_pll(clk, 0x42, 0x00e8a0); 54 default: 55 return 0; 56 } 57 } 58 59 static u32 60 read_clk(struct gt215_clk *clk, int idx, bool ignore_en) 61 { 62 struct nvkm_device *device = clk->base.subdev.device; 63 u32 sctl, sdiv, sclk; 64 65 /* refclk for the 0xe8xx plls is a fixed frequency */ 66 if (idx >= 0x40) { 67 if (device->chipset == 0xaf) { 68 /* no joke.. seriously.. sigh.. */ 69 return nvkm_rd32(device, 0x00471c) * 1000; 70 } 71 72 return device->crystal; 73 } 74 75 sctl = nvkm_rd32(device, 0x4120 + (idx * 4)); 76 if (!ignore_en && !(sctl & 0x00000100)) 77 return 0; 78 79 /* out_alt */ 80 if (sctl & 0x00000400) 81 return 108000; 82 83 /* vco_out */ 84 switch (sctl & 0x00003000) { 85 case 0x00000000: 86 if (!(sctl & 0x00000200)) 87 return device->crystal; 88 return 0; 89 case 0x00002000: 90 if (sctl & 0x00000040) 91 return 108000; 92 return 100000; 93 case 0x00003000: 94 /* vco_enable */ 95 if (!(sctl & 0x00000001)) 96 return 0; 97 98 sclk = read_vco(clk, idx); 99 sdiv = ((sctl & 0x003f0000) >> 16) + 2; 100 return (sclk * 2) / sdiv; 101 default: 102 return 0; 103 } 104 } 105 106 static u32 107 read_pll(struct gt215_clk *clk, int idx, u32 pll) 108 { 109 struct nvkm_device *device = clk->base.subdev.device; 110 u32 ctrl = nvkm_rd32(device, pll + 0); 111 u32 sclk = 0, P = 1, N = 1, M = 1; 112 113 if (!(ctrl & 0x00000008)) { 114 if (ctrl & 0x00000001) { 115 u32 coef = nvkm_rd32(device, pll + 4); 116 M = (coef & 0x000000ff) >> 0; 117 N = (coef & 0x0000ff00) >> 8; 118 P = (coef & 0x003f0000) >> 16; 119 120 /* no post-divider on these.. 121 * XXX: it looks more like two post-"dividers" that 122 * cross each other out in the default RPLL config */ 123 if ((pll & 0x00ff00) == 0x00e800) 124 P = 1; 125 126 sclk = read_clk(clk, 0x00 + idx, false); 127 } 128 } else { 129 sclk = read_clk(clk, 0x10 + idx, false); 130 } 131 132 if (M * P) 133 return sclk * N / (M * P); 134 135 return 0; 136 } 137 138 static int 139 gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 140 { 141 struct gt215_clk *clk = container_of(obj, typeof(*clk), base); 142 struct nvkm_device *device = clk->base.subdev.device; 143 u32 hsrc; 144 145 switch (src) { 146 case nv_clk_src_crystal: 147 return device->crystal; 148 case nv_clk_src_core: 149 case nv_clk_src_core_intm: 150 return read_pll(clk, 0x00, 0x4200); 151 case nv_clk_src_shader: 152 return read_pll(clk, 0x01, 0x4220); 153 case nv_clk_src_mem: 154 return read_pll(clk, 0x02, 0x4000); 155 case nv_clk_src_disp: 156 return read_clk(clk, 0x20, false); 157 case nv_clk_src_vdec: 158 return read_clk(clk, 0x21, false); 159 case nv_clk_src_daemon: 160 return read_clk(clk, 0x25, false); 161 case nv_clk_src_host: 162 hsrc = (nvkm_rd32(device, 0xc040) & 0x30000000) >> 28; 163 switch (hsrc) { 164 case 0: 165 return read_clk(clk, 0x1d, false); 166 case 2: 167 case 3: 168 return 277000; 169 default: 170 nv_error(clk, "unknown HOST clock source %d\n", hsrc); 171 return -EINVAL; 172 } 173 default: 174 nv_error(clk, "invalid clock source %d\n", src); 175 return -EINVAL; 176 } 177 178 return 0; 179 } 180 181 int 182 gt215_clk_info(struct nvkm_clk *obj, int idx, u32 khz, 183 struct gt215_clk_info *info) 184 { 185 struct gt215_clk *clk = container_of(obj, typeof(*clk), base); 186 u32 oclk, sclk, sdiv; 187 s32 diff; 188 189 info->clk = 0; 190 191 switch (khz) { 192 case 27000: 193 info->clk = 0x00000100; 194 return khz; 195 case 100000: 196 info->clk = 0x00002100; 197 return khz; 198 case 108000: 199 info->clk = 0x00002140; 200 return khz; 201 default: 202 sclk = read_vco(clk, idx); 203 sdiv = min((sclk * 2) / khz, (u32)65); 204 oclk = (sclk * 2) / sdiv; 205 diff = ((khz + 3000) - oclk); 206 207 /* When imprecise, play it safe and aim for a clock lower than 208 * desired rather than higher */ 209 if (diff < 0) { 210 sdiv++; 211 oclk = (sclk * 2) / sdiv; 212 } 213 214 /* divider can go as low as 2, limited here because NVIDIA 215 * and the VBIOS on my NVA8 seem to prefer using the PLL 216 * for 810MHz - is there a good reason? 217 * XXX: PLLs with refclk 810MHz? */ 218 if (sdiv > 4) { 219 info->clk = (((sdiv - 2) << 16) | 0x00003100); 220 return oclk; 221 } 222 223 break; 224 } 225 226 return -ERANGE; 227 } 228 229 int 230 gt215_pll_info(struct nvkm_clk *clock, int idx, u32 pll, u32 khz, 231 struct gt215_clk_info *info) 232 { 233 struct nvkm_bios *bios = nvkm_bios(clock); 234 struct gt215_clk *clk = (void *)clock; 235 struct nvbios_pll limits; 236 int P, N, M, diff; 237 int ret; 238 239 info->pll = 0; 240 241 /* If we can get a within [-2, 3) MHz of a divider, we'll disable the 242 * PLL and use the divider instead. */ 243 ret = gt215_clk_info(clock, idx, khz, info); 244 diff = khz - ret; 245 if (!pll || (diff >= -2000 && diff < 3000)) { 246 goto out; 247 } 248 249 /* Try with PLL */ 250 ret = nvbios_pll_parse(bios, pll, &limits); 251 if (ret) 252 return ret; 253 254 ret = gt215_clk_info(clock, idx - 0x10, limits.refclk, info); 255 if (ret != limits.refclk) 256 return -EINVAL; 257 258 ret = gt215_pll_calc(nv_subdev(clk), &limits, khz, &N, NULL, &M, &P); 259 if (ret >= 0) { 260 info->pll = (P << 16) | (N << 8) | M; 261 } 262 263 out: 264 info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); 265 return ret ? ret : -ERANGE; 266 } 267 268 static int 269 calc_clk(struct gt215_clk *clk, struct nvkm_cstate *cstate, 270 int idx, u32 pll, int dom) 271 { 272 int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom], 273 &clk->eng[dom]); 274 if (ret >= 0) 275 return 0; 276 return ret; 277 } 278 279 static int 280 calc_host(struct gt215_clk *clk, struct nvkm_cstate *cstate) 281 { 282 int ret = 0; 283 u32 kHz = cstate->domain[nv_clk_src_host]; 284 struct gt215_clk_info *info = &clk->eng[nv_clk_src_host]; 285 286 if (kHz == 277000) { 287 info->clk = 0; 288 info->host_out = NVA3_HOST_277; 289 return 0; 290 } 291 292 info->host_out = NVA3_HOST_CLK; 293 294 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); 295 if (ret >= 0) 296 return 0; 297 298 return ret; 299 } 300 301 int 302 gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) 303 { 304 struct nvkm_device *device = clk->subdev.device; 305 struct nvkm_fifo *fifo = device->fifo; 306 307 /* halt and idle execution engines */ 308 nvkm_mask(device, 0x020060, 0x00070000, 0x00000000); 309 nvkm_mask(device, 0x002504, 0x00000001, 0x00000001); 310 /* Wait until the interrupt handler is finished */ 311 if (nvkm_msec(device, 2000, 312 if (!nvkm_rd32(device, 0x000100)) 313 break; 314 ) < 0) 315 return -EBUSY; 316 317 if (fifo) 318 fifo->pause(fifo, flags); 319 320 if (nvkm_msec(device, 2000, 321 if (nvkm_rd32(device, 0x002504) & 0x00000010) 322 break; 323 ) < 0) 324 return -EIO; 325 326 if (nvkm_msec(device, 2000, 327 u32 tmp = nvkm_rd32(device, 0x002504) & 0x0000003f; 328 if (tmp == 0x0000003f) 329 break; 330 ) < 0) 331 return -EIO; 332 333 return 0; 334 } 335 336 void 337 gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) 338 { 339 struct nvkm_device *device = clk->subdev.device; 340 struct nvkm_fifo *fifo = nvkm_fifo(clk); 341 342 if (fifo && flags) 343 fifo->start(fifo, flags); 344 345 nvkm_mask(device, 0x002504, 0x00000001, 0x00000000); 346 nvkm_mask(device, 0x020060, 0x00070000, 0x00040000); 347 } 348 349 static void 350 disable_clk_src(struct gt215_clk *clk, u32 src) 351 { 352 struct nvkm_device *device = clk->base.subdev.device; 353 nvkm_mask(device, src, 0x00000100, 0x00000000); 354 nvkm_mask(device, src, 0x00000001, 0x00000000); 355 } 356 357 static void 358 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) 359 { 360 struct gt215_clk_info *info = &clk->eng[dom]; 361 struct nvkm_device *device = clk->base.subdev.device; 362 const u32 src0 = 0x004120 + (idx * 4); 363 const u32 src1 = 0x004160 + (idx * 4); 364 const u32 ctrl = pll + 0; 365 const u32 coef = pll + 4; 366 u32 bypass; 367 368 if (info->pll) { 369 /* Always start from a non-PLL clock */ 370 bypass = nvkm_rd32(device, ctrl) & 0x00000008; 371 if (!bypass) { 372 nvkm_mask(device, src1, 0x00000101, 0x00000101); 373 nvkm_mask(device, ctrl, 0x00000008, 0x00000008); 374 udelay(20); 375 } 376 377 nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk); 378 nvkm_wr32(device, coef, info->pll); 379 nvkm_mask(device, ctrl, 0x00000015, 0x00000015); 380 nvkm_mask(device, ctrl, 0x00000010, 0x00000000); 381 if (nvkm_msec(device, 2000, 382 if (nvkm_rd32(device, ctrl) & 0x00020000) 383 break; 384 ) < 0) { 385 nvkm_mask(device, ctrl, 0x00000010, 0x00000010); 386 nvkm_mask(device, src0, 0x00000101, 0x00000000); 387 return; 388 } 389 nvkm_mask(device, ctrl, 0x00000010, 0x00000010); 390 nvkm_mask(device, ctrl, 0x00000008, 0x00000000); 391 disable_clk_src(clk, src1); 392 } else { 393 nvkm_mask(device, src1, 0x003f3141, 0x00000101 | info->clk); 394 nvkm_mask(device, ctrl, 0x00000018, 0x00000018); 395 udelay(20); 396 nvkm_mask(device, ctrl, 0x00000001, 0x00000000); 397 disable_clk_src(clk, src0); 398 } 399 } 400 401 static void 402 prog_clk(struct gt215_clk *clk, int idx, int dom) 403 { 404 struct gt215_clk_info *info = &clk->eng[dom]; 405 struct nvkm_device *device = clk->base.subdev.device; 406 nvkm_mask(device, 0x004120 + (idx * 4), 0x003f3141, 0x00000101 | info->clk); 407 } 408 409 static void 410 prog_host(struct gt215_clk *clk) 411 { 412 struct gt215_clk_info *info = &clk->eng[nv_clk_src_host]; 413 struct nvkm_device *device = clk->base.subdev.device; 414 u32 hsrc = (nvkm_rd32(device, 0xc040)); 415 416 switch (info->host_out) { 417 case NVA3_HOST_277: 418 if ((hsrc & 0x30000000) == 0) { 419 nvkm_wr32(device, 0xc040, hsrc | 0x20000000); 420 disable_clk_src(clk, 0x4194); 421 } 422 break; 423 case NVA3_HOST_CLK: 424 prog_clk(clk, 0x1d, nv_clk_src_host); 425 if ((hsrc & 0x30000000) >= 0x20000000) { 426 nvkm_wr32(device, 0xc040, hsrc & ~0x30000000); 427 } 428 break; 429 default: 430 break; 431 } 432 433 /* This seems to be a clock gating factor on idle, always set to 64 */ 434 nvkm_wr32(device, 0xc044, 0x3e); 435 } 436 437 static void 438 prog_core(struct gt215_clk *clk, int dom) 439 { 440 struct gt215_clk_info *info = &clk->eng[dom]; 441 struct nvkm_device *device = clk->base.subdev.device; 442 u32 fb_delay = nvkm_rd32(device, 0x10002c); 443 444 if (fb_delay < info->fb_delay) 445 nvkm_wr32(device, 0x10002c, info->fb_delay); 446 447 prog_pll(clk, 0x00, 0x004200, dom); 448 449 if (fb_delay > info->fb_delay) 450 nvkm_wr32(device, 0x10002c, info->fb_delay); 451 } 452 453 static int 454 gt215_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 455 { 456 struct gt215_clk *clk = container_of(obj, typeof(*clk), base); 457 struct gt215_clk_info *core = &clk->eng[nv_clk_src_core]; 458 int ret; 459 460 if ((ret = calc_clk(clk, cstate, 0x10, 0x4200, nv_clk_src_core)) || 461 (ret = calc_clk(clk, cstate, 0x11, 0x4220, nv_clk_src_shader)) || 462 (ret = calc_clk(clk, cstate, 0x20, 0x0000, nv_clk_src_disp)) || 463 (ret = calc_clk(clk, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || 464 (ret = calc_host(clk, cstate))) 465 return ret; 466 467 /* XXX: Should be reading the highest bit in the VBIOS clock to decide 468 * whether to use a PLL or not... but using a PLL defeats the purpose */ 469 if (core->pll) { 470 ret = gt215_clk_info(&clk->base, 0x10, 471 cstate->domain[nv_clk_src_core_intm], 472 &clk->eng[nv_clk_src_core_intm]); 473 if (ret < 0) 474 return ret; 475 } 476 477 return 0; 478 } 479 480 static int 481 gt215_clk_prog(struct nvkm_clk *obj) 482 { 483 struct gt215_clk *clk = container_of(obj, typeof(*clk), base); 484 struct gt215_clk_info *core = &clk->eng[nv_clk_src_core]; 485 int ret = 0; 486 unsigned long flags; 487 unsigned long *f = &flags; 488 489 ret = gt215_clk_pre(&clk->base, f); 490 if (ret) 491 goto out; 492 493 if (core->pll) 494 prog_core(clk, nv_clk_src_core_intm); 495 496 prog_core(clk, nv_clk_src_core); 497 prog_pll(clk, 0x01, 0x004220, nv_clk_src_shader); 498 prog_clk(clk, 0x20, nv_clk_src_disp); 499 prog_clk(clk, 0x21, nv_clk_src_vdec); 500 prog_host(clk); 501 502 out: 503 if (ret == -EBUSY) 504 f = NULL; 505 506 gt215_clk_post(&clk->base, f); 507 return ret; 508 } 509 510 static void 511 gt215_clk_tidy(struct nvkm_clk *obj) 512 { 513 } 514 515 static struct nvkm_domain 516 gt215_domain[] = { 517 { nv_clk_src_crystal , 0xff }, 518 { nv_clk_src_core , 0x00, 0, "core", 1000 }, 519 { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, 520 { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, 521 { nv_clk_src_vdec , 0x03 }, 522 { nv_clk_src_disp , 0x04 }, 523 { nv_clk_src_host , 0x05 }, 524 { nv_clk_src_core_intm, 0x06 }, 525 { nv_clk_src_max } 526 }; 527 528 static int 529 gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 530 struct nvkm_oclass *oclass, void *data, u32 size, 531 struct nvkm_object **pobject) 532 { 533 struct gt215_clk *clk; 534 int ret; 535 536 ret = nvkm_clk_create(parent, engine, oclass, gt215_domain, 537 NULL, 0, true, &clk); 538 *pobject = nv_object(clk); 539 if (ret) 540 return ret; 541 542 clk->base.read = gt215_clk_read; 543 clk->base.calc = gt215_clk_calc; 544 clk->base.prog = gt215_clk_prog; 545 clk->base.tidy = gt215_clk_tidy; 546 return 0; 547 } 548 549 struct nvkm_oclass 550 gt215_clk_oclass = { 551 .handle = NV_SUBDEV(CLK, 0xa3), 552 .ofuncs = &(struct nvkm_ofuncs) { 553 .ctor = gt215_clk_ctor, 554 .dtor = _nvkm_clk_dtor, 555 .init = _nvkm_clk_init, 556 .fini = _nvkm_clk_fini, 557 }, 558 }; 559