1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #include <subdev/clk.h> 26 #include <subdev/timer.h> 27 28 #ifdef __KERNEL__ 29 #include <nouveau_platform.h> 30 #endif 31 32 #define MHZ (1000 * 1000) 33 34 #define MASK(w) ((1 << w) - 1) 35 36 #define SYS_GPCPLL_CFG_BASE 0x00137000 37 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 38 39 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 40 #define GPCPLL_CFG_ENABLE BIT(0) 41 #define GPCPLL_CFG_IDDQ BIT(1) 42 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 43 #define GPCPLL_CFG_LOCK BIT(17) 44 45 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 46 #define GPCPLL_COEFF_M_SHIFT 0 47 #define GPCPLL_COEFF_M_WIDTH 8 48 #define GPCPLL_COEFF_N_SHIFT 8 49 #define GPCPLL_COEFF_N_WIDTH 8 50 #define GPCPLL_COEFF_P_SHIFT 16 51 #define GPCPLL_COEFF_P_WIDTH 6 52 53 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 54 #define GPCPLL_CFG2_SETUP2_SHIFT 16 55 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 56 57 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 58 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 59 60 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 61 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 62 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 63 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 64 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 65 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 66 67 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 68 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 69 70 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 71 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 72 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 73 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 74 #define GPC2CLK_OUT_VCODIV_WIDTH 6 75 #define GPC2CLK_OUT_VCODIV_SHIFT 8 76 #define GPC2CLK_OUT_VCODIV1 0 77 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 78 GPC2CLK_OUT_VCODIV_SHIFT) 79 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 80 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 81 #define GPC2CLK_OUT_BYPDIV31 0x3c 82 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 83 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 84 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 85 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 86 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 87 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 88 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 89 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 90 91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 94 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 95 96 static const u8 pl_to_div[] = { 97 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 98 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 99 }; 100 101 /* All frequencies in Mhz */ 102 struct gk20a_clk_pllg_params { 103 u32 min_vco, max_vco; 104 u32 min_u, max_u; 105 u32 min_m, max_m; 106 u32 min_n, max_n; 107 u32 min_pl, max_pl; 108 }; 109 110 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 111 .min_vco = 1000, .max_vco = 2064, 112 .min_u = 12, .max_u = 38, 113 .min_m = 1, .max_m = 255, 114 .min_n = 8, .max_n = 255, 115 .min_pl = 1, .max_pl = 32, 116 }; 117 118 struct gk20a_clk { 119 struct nvkm_clk base; 120 const struct gk20a_clk_pllg_params *params; 121 u32 m, n, pl; 122 u32 parent_rate; 123 }; 124 #define to_gk20a_clk(base) container_of(base, struct gk20a_clk, base) 125 126 static void 127 gk20a_pllg_read_mnp(struct gk20a_clk *clk) 128 { 129 u32 val; 130 131 val = nv_rd32(clk, GPCPLL_COEFF); 132 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 133 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 134 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 135 } 136 137 static u32 138 gk20a_pllg_calc_rate(struct gk20a_clk *clk) 139 { 140 u32 rate; 141 u32 divider; 142 143 rate = clk->parent_rate * clk->n; 144 divider = clk->m * pl_to_div[clk->pl]; 145 do_div(rate, divider); 146 147 return rate / 2; 148 } 149 150 static int 151 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) 152 { 153 u32 target_clk_f, ref_clk_f, target_freq; 154 u32 min_vco_f, max_vco_f; 155 u32 low_pl, high_pl, best_pl; 156 u32 target_vco_f, vco_f; 157 u32 best_m, best_n; 158 u32 u_f; 159 u32 m, n, n2; 160 u32 delta, lwv, best_delta = ~0; 161 u32 pl; 162 163 target_clk_f = rate * 2 / MHZ; 164 ref_clk_f = clk->parent_rate / MHZ; 165 166 max_vco_f = clk->params->max_vco; 167 min_vco_f = clk->params->min_vco; 168 best_m = clk->params->max_m; 169 best_n = clk->params->min_n; 170 best_pl = clk->params->min_pl; 171 172 target_vco_f = target_clk_f + target_clk_f / 50; 173 if (max_vco_f < target_vco_f) 174 max_vco_f = target_vco_f; 175 176 /* min_pl <= high_pl <= max_pl */ 177 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 178 high_pl = min(high_pl, clk->params->max_pl); 179 high_pl = max(high_pl, clk->params->min_pl); 180 181 /* min_pl <= low_pl <= max_pl */ 182 low_pl = min_vco_f / target_vco_f; 183 low_pl = min(low_pl, clk->params->max_pl); 184 low_pl = max(low_pl, clk->params->min_pl); 185 186 /* Find Indices of high_pl and low_pl */ 187 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 188 if (pl_to_div[pl] >= low_pl) { 189 low_pl = pl; 190 break; 191 } 192 } 193 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 194 if (pl_to_div[pl] >= high_pl) { 195 high_pl = pl; 196 break; 197 } 198 } 199 200 nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 201 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); 202 203 /* Select lowest possible VCO */ 204 for (pl = low_pl; pl <= high_pl; pl++) { 205 target_vco_f = target_clk_f * pl_to_div[pl]; 206 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 207 u_f = ref_clk_f / m; 208 209 if (u_f < clk->params->min_u) 210 break; 211 if (u_f > clk->params->max_u) 212 continue; 213 214 n = (target_vco_f * m) / ref_clk_f; 215 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 216 217 if (n > clk->params->max_n) 218 break; 219 220 for (; n <= n2; n++) { 221 if (n < clk->params->min_n) 222 continue; 223 if (n > clk->params->max_n) 224 break; 225 226 vco_f = ref_clk_f * n / m; 227 228 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 229 lwv = (vco_f + (pl_to_div[pl] / 2)) 230 / pl_to_div[pl]; 231 delta = abs(lwv - target_clk_f); 232 233 if (delta < best_delta) { 234 best_delta = delta; 235 best_m = m; 236 best_n = n; 237 best_pl = pl; 238 239 if (best_delta == 0) 240 goto found_match; 241 } 242 } 243 } 244 } 245 } 246 247 found_match: 248 WARN_ON(best_delta == ~0); 249 250 if (best_delta != 0) 251 nv_debug(clk, "no best match for target @ %dMHz on gpc_pll", 252 target_clk_f); 253 254 clk->m = best_m; 255 clk->n = best_n; 256 clk->pl = best_pl; 257 258 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; 259 260 nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 261 target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); 262 return 0; 263 } 264 265 static int 266 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 267 { 268 u32 val; 269 int ramp_timeout; 270 271 /* get old coefficients */ 272 val = nv_rd32(clk, GPCPLL_COEFF); 273 /* do nothing if NDIV is the same */ 274 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 275 return 0; 276 277 /* setup */ 278 nv_mask(clk, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 279 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 280 nv_mask(clk, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 281 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 282 283 /* pll slowdown mode */ 284 nv_mask(clk, GPCPLL_NDIV_SLOWDOWN, 285 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 286 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 287 288 /* new ndiv ready for ramp */ 289 val = nv_rd32(clk, GPCPLL_COEFF); 290 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 291 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 292 udelay(1); 293 nv_wr32(clk, GPCPLL_COEFF, val); 294 295 /* dynamic ramp to new ndiv */ 296 val = nv_rd32(clk, GPCPLL_NDIV_SLOWDOWN); 297 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 298 udelay(1); 299 nv_wr32(clk, GPCPLL_NDIV_SLOWDOWN, val); 300 301 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 302 udelay(1); 303 val = nv_rd32(clk, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 304 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 305 break; 306 } 307 308 /* exit slowdown mode */ 309 nv_mask(clk, GPCPLL_NDIV_SLOWDOWN, 310 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 311 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 312 nv_rd32(clk, GPCPLL_NDIV_SLOWDOWN); 313 314 if (ramp_timeout <= 0) { 315 nv_error(clk, "gpcpll dynamic ramp timeout\n"); 316 return -ETIMEDOUT; 317 } 318 319 return 0; 320 } 321 322 static void 323 _gk20a_pllg_enable(struct gk20a_clk *clk) 324 { 325 nv_mask(clk, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 326 nv_rd32(clk, GPCPLL_CFG); 327 } 328 329 static void 330 _gk20a_pllg_disable(struct gk20a_clk *clk) 331 { 332 nv_mask(clk, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 333 nv_rd32(clk, GPCPLL_CFG); 334 } 335 336 static int 337 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) 338 { 339 u32 val, cfg; 340 u32 m_old, pl_old, n_lo; 341 342 /* get old coefficients */ 343 val = nv_rd32(clk, GPCPLL_COEFF); 344 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 345 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 346 347 /* do NDIV slide if there is no change in M and PL */ 348 cfg = nv_rd32(clk, GPCPLL_CFG); 349 if (allow_slide && clk->m == m_old && clk->pl == pl_old && 350 (cfg & GPCPLL_CFG_ENABLE)) { 351 return gk20a_pllg_slide(clk, clk->n); 352 } 353 354 /* slide down to NDIV_LO */ 355 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, 356 clk->parent_rate / MHZ); 357 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 358 int ret = gk20a_pllg_slide(clk, n_lo); 359 360 if (ret) 361 return ret; 362 } 363 364 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 365 nv_mask(clk, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 366 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 367 368 /* put PLL in bypass before programming it */ 369 val = nv_rd32(clk, SEL_VCO); 370 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 371 udelay(2); 372 nv_wr32(clk, SEL_VCO, val); 373 374 /* get out from IDDQ */ 375 val = nv_rd32(clk, GPCPLL_CFG); 376 if (val & GPCPLL_CFG_IDDQ) { 377 val &= ~GPCPLL_CFG_IDDQ; 378 nv_wr32(clk, GPCPLL_CFG, val); 379 nv_rd32(clk, GPCPLL_CFG); 380 udelay(2); 381 } 382 383 _gk20a_pllg_disable(clk); 384 385 nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n, 386 clk->pl); 387 388 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, 389 clk->parent_rate / MHZ); 390 val = clk->m << GPCPLL_COEFF_M_SHIFT; 391 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; 392 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; 393 nv_wr32(clk, GPCPLL_COEFF, val); 394 395 _gk20a_pllg_enable(clk); 396 397 val = nv_rd32(clk, GPCPLL_CFG); 398 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 399 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 400 nv_wr32(clk, GPCPLL_CFG, val); 401 } 402 403 if (!nvkm_timer_wait_eq(clk, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, 404 GPCPLL_CFG_LOCK)) { 405 nv_error(clk, "%s: timeout waiting for pllg lock\n", __func__); 406 return -ETIMEDOUT; 407 } 408 409 /* switch to VCO mode */ 410 nv_mask(clk, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 411 412 /* restore out divider 1:1 */ 413 val = nv_rd32(clk, GPC2CLK_OUT); 414 val &= ~GPC2CLK_OUT_VCODIV_MASK; 415 udelay(2); 416 nv_wr32(clk, GPC2CLK_OUT, val); 417 418 /* slide up to new NDIV */ 419 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; 420 } 421 422 static int 423 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 424 { 425 int err; 426 427 err = _gk20a_pllg_program_mnp(clk, true); 428 if (err) 429 err = _gk20a_pllg_program_mnp(clk, false); 430 431 return err; 432 } 433 434 static void 435 gk20a_pllg_disable(struct gk20a_clk *clk) 436 { 437 u32 val; 438 439 /* slide to VCO min */ 440 val = nv_rd32(clk, GPCPLL_CFG); 441 if (val & GPCPLL_CFG_ENABLE) { 442 u32 coeff, m, n_lo; 443 444 coeff = nv_rd32(clk, GPCPLL_COEFF); 445 m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 446 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, 447 clk->parent_rate / MHZ); 448 gk20a_pllg_slide(clk, n_lo); 449 } 450 451 /* put PLL in bypass before disabling it */ 452 nv_mask(clk, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 453 454 _gk20a_pllg_disable(clk); 455 } 456 457 #define GK20A_CLK_GPC_MDIV 1000 458 459 static struct nvkm_domain 460 gk20a_domains[] = { 461 { nv_clk_src_crystal, 0xff }, 462 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 463 { nv_clk_src_max } 464 }; 465 466 static struct nvkm_pstate 467 gk20a_pstates[] = { 468 { 469 .base = { 470 .domain[nv_clk_src_gpc] = 72000, 471 .voltage = 0, 472 }, 473 }, 474 { 475 .base = { 476 .domain[nv_clk_src_gpc] = 108000, 477 .voltage = 1, 478 }, 479 }, 480 { 481 .base = { 482 .domain[nv_clk_src_gpc] = 180000, 483 .voltage = 2, 484 }, 485 }, 486 { 487 .base = { 488 .domain[nv_clk_src_gpc] = 252000, 489 .voltage = 3, 490 }, 491 }, 492 { 493 .base = { 494 .domain[nv_clk_src_gpc] = 324000, 495 .voltage = 4, 496 }, 497 }, 498 { 499 .base = { 500 .domain[nv_clk_src_gpc] = 396000, 501 .voltage = 5, 502 }, 503 }, 504 { 505 .base = { 506 .domain[nv_clk_src_gpc] = 468000, 507 .voltage = 6, 508 }, 509 }, 510 { 511 .base = { 512 .domain[nv_clk_src_gpc] = 540000, 513 .voltage = 7, 514 }, 515 }, 516 { 517 .base = { 518 .domain[nv_clk_src_gpc] = 612000, 519 .voltage = 8, 520 }, 521 }, 522 { 523 .base = { 524 .domain[nv_clk_src_gpc] = 648000, 525 .voltage = 9, 526 }, 527 }, 528 { 529 .base = { 530 .domain[nv_clk_src_gpc] = 684000, 531 .voltage = 10, 532 }, 533 }, 534 { 535 .base = { 536 .domain[nv_clk_src_gpc] = 708000, 537 .voltage = 11, 538 }, 539 }, 540 { 541 .base = { 542 .domain[nv_clk_src_gpc] = 756000, 543 .voltage = 12, 544 }, 545 }, 546 { 547 .base = { 548 .domain[nv_clk_src_gpc] = 804000, 549 .voltage = 13, 550 }, 551 }, 552 { 553 .base = { 554 .domain[nv_clk_src_gpc] = 852000, 555 .voltage = 14, 556 }, 557 }, 558 }; 559 560 static int 561 gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 562 { 563 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 564 565 switch (src) { 566 case nv_clk_src_crystal: 567 return nv_device(clk)->crystal; 568 case nv_clk_src_gpc: 569 gk20a_pllg_read_mnp(clk); 570 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; 571 default: 572 nv_error(clk, "invalid clock source %d\n", src); 573 return -EINVAL; 574 } 575 } 576 577 static int 578 gk20a_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 579 { 580 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 581 582 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 583 GK20A_CLK_GPC_MDIV); 584 } 585 586 static int 587 gk20a_clk_prog(struct nvkm_clk *obj) 588 { 589 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 590 591 return gk20a_pllg_program_mnp(clk); 592 } 593 594 static void 595 gk20a_clk_tidy(struct nvkm_clk *obj) 596 { 597 } 598 599 static int 600 gk20a_clk_fini(struct nvkm_object *object, bool suspend) 601 { 602 struct gk20a_clk *clk = (void *)object; 603 int ret; 604 605 ret = nvkm_clk_fini(&clk->base, false); 606 607 gk20a_pllg_disable(clk); 608 609 return ret; 610 } 611 612 static int 613 gk20a_clk_init(struct nvkm_object *object) 614 { 615 struct gk20a_clk *clk = (void *)object; 616 int ret; 617 618 nv_mask(clk, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 619 620 ret = nvkm_clk_init(&clk->base); 621 if (ret) 622 return ret; 623 624 ret = gk20a_clk_prog(&clk->base); 625 if (ret) { 626 nv_error(clk, "cannot initialize clock\n"); 627 return ret; 628 } 629 630 return 0; 631 } 632 633 static int 634 gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 635 struct nvkm_oclass *oclass, void *data, u32 size, 636 struct nvkm_object **pobject) 637 { 638 struct gk20a_clk *clk; 639 struct nouveau_platform_device *plat; 640 int ret; 641 int i; 642 643 /* Finish initializing the pstates */ 644 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { 645 INIT_LIST_HEAD(&gk20a_pstates[i].list); 646 gk20a_pstates[i].pstate = i + 1; 647 } 648 649 ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains, 650 gk20a_pstates, ARRAY_SIZE(gk20a_pstates), 651 true, &clk); 652 *pobject = nv_object(clk); 653 if (ret) 654 return ret; 655 656 clk->params = &gk20a_pllg_params; 657 658 plat = nv_device_to_platform(nv_device(parent)); 659 clk->parent_rate = clk_get_rate(plat->gpu->clk); 660 nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ); 661 662 clk->base.read = gk20a_clk_read; 663 clk->base.calc = gk20a_clk_calc; 664 clk->base.prog = gk20a_clk_prog; 665 clk->base.tidy = gk20a_clk_tidy; 666 return 0; 667 } 668 669 struct nvkm_oclass 670 gk20a_clk_oclass = { 671 .handle = NV_SUBDEV(CLK, 0xea), 672 .ofuncs = &(struct nvkm_ofuncs) { 673 .ctor = gk20a_clk_ctor, 674 .dtor = _nvkm_subdev_dtor, 675 .init = gk20a_clk_init, 676 .fini = gk20a_clk_fini, 677 }, 678 }; 679