1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #include <subdev/clk.h> 26 #include <subdev/timer.h> 27 28 #ifdef __KERNEL__ 29 #include <nouveau_platform.h> 30 #endif 31 32 #define MHZ (1000 * 1000) 33 34 #define MASK(w) ((1 << w) - 1) 35 36 #define SYS_GPCPLL_CFG_BASE 0x00137000 37 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 38 39 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 40 #define GPCPLL_CFG_ENABLE BIT(0) 41 #define GPCPLL_CFG_IDDQ BIT(1) 42 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 43 #define GPCPLL_CFG_LOCK BIT(17) 44 45 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 46 #define GPCPLL_COEFF_M_SHIFT 0 47 #define GPCPLL_COEFF_M_WIDTH 8 48 #define GPCPLL_COEFF_N_SHIFT 8 49 #define GPCPLL_COEFF_N_WIDTH 8 50 #define GPCPLL_COEFF_P_SHIFT 16 51 #define GPCPLL_COEFF_P_WIDTH 6 52 53 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 54 #define GPCPLL_CFG2_SETUP2_SHIFT 16 55 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 56 57 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 58 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 59 60 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 61 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 62 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 63 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 64 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 65 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 66 67 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 68 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 69 70 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 71 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 72 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 73 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 74 #define GPC2CLK_OUT_VCODIV_WIDTH 6 75 #define GPC2CLK_OUT_VCODIV_SHIFT 8 76 #define GPC2CLK_OUT_VCODIV1 0 77 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 78 GPC2CLK_OUT_VCODIV_SHIFT) 79 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 80 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 81 #define GPC2CLK_OUT_BYPDIV31 0x3c 82 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 83 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 84 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 85 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 86 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 87 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 88 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 89 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 90 91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 94 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 95 96 static const u8 pl_to_div[] = { 97 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 98 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 99 }; 100 101 /* All frequencies in Mhz */ 102 struct gk20a_clk_pllg_params { 103 u32 min_vco, max_vco; 104 u32 min_u, max_u; 105 u32 min_m, max_m; 106 u32 min_n, max_n; 107 u32 min_pl, max_pl; 108 }; 109 110 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 111 .min_vco = 1000, .max_vco = 2064, 112 .min_u = 12, .max_u = 38, 113 .min_m = 1, .max_m = 255, 114 .min_n = 8, .max_n = 255, 115 .min_pl = 1, .max_pl = 32, 116 }; 117 118 struct gk20a_clk { 119 struct nvkm_clk base; 120 const struct gk20a_clk_pllg_params *params; 121 u32 m, n, pl; 122 u32 parent_rate; 123 }; 124 #define to_gk20a_clk(base) container_of(base, struct gk20a_clk, base) 125 126 static void 127 gk20a_pllg_read_mnp(struct gk20a_clk *clk) 128 { 129 struct nvkm_device *device = clk->base.subdev.device; 130 u32 val; 131 132 val = nvkm_rd32(device, GPCPLL_COEFF); 133 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 134 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 135 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 136 } 137 138 static u32 139 gk20a_pllg_calc_rate(struct gk20a_clk *clk) 140 { 141 u32 rate; 142 u32 divider; 143 144 rate = clk->parent_rate * clk->n; 145 divider = clk->m * pl_to_div[clk->pl]; 146 do_div(rate, divider); 147 148 return rate / 2; 149 } 150 151 static int 152 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) 153 { 154 u32 target_clk_f, ref_clk_f, target_freq; 155 u32 min_vco_f, max_vco_f; 156 u32 low_pl, high_pl, best_pl; 157 u32 target_vco_f, vco_f; 158 u32 best_m, best_n; 159 u32 u_f; 160 u32 m, n, n2; 161 u32 delta, lwv, best_delta = ~0; 162 u32 pl; 163 164 target_clk_f = rate * 2 / MHZ; 165 ref_clk_f = clk->parent_rate / MHZ; 166 167 max_vco_f = clk->params->max_vco; 168 min_vco_f = clk->params->min_vco; 169 best_m = clk->params->max_m; 170 best_n = clk->params->min_n; 171 best_pl = clk->params->min_pl; 172 173 target_vco_f = target_clk_f + target_clk_f / 50; 174 if (max_vco_f < target_vco_f) 175 max_vco_f = target_vco_f; 176 177 /* min_pl <= high_pl <= max_pl */ 178 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 179 high_pl = min(high_pl, clk->params->max_pl); 180 high_pl = max(high_pl, clk->params->min_pl); 181 182 /* min_pl <= low_pl <= max_pl */ 183 low_pl = min_vco_f / target_vco_f; 184 low_pl = min(low_pl, clk->params->max_pl); 185 low_pl = max(low_pl, clk->params->min_pl); 186 187 /* Find Indices of high_pl and low_pl */ 188 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 189 if (pl_to_div[pl] >= low_pl) { 190 low_pl = pl; 191 break; 192 } 193 } 194 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 195 if (pl_to_div[pl] >= high_pl) { 196 high_pl = pl; 197 break; 198 } 199 } 200 201 nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 202 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); 203 204 /* Select lowest possible VCO */ 205 for (pl = low_pl; pl <= high_pl; pl++) { 206 target_vco_f = target_clk_f * pl_to_div[pl]; 207 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 208 u_f = ref_clk_f / m; 209 210 if (u_f < clk->params->min_u) 211 break; 212 if (u_f > clk->params->max_u) 213 continue; 214 215 n = (target_vco_f * m) / ref_clk_f; 216 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 217 218 if (n > clk->params->max_n) 219 break; 220 221 for (; n <= n2; n++) { 222 if (n < clk->params->min_n) 223 continue; 224 if (n > clk->params->max_n) 225 break; 226 227 vco_f = ref_clk_f * n / m; 228 229 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 230 lwv = (vco_f + (pl_to_div[pl] / 2)) 231 / pl_to_div[pl]; 232 delta = abs(lwv - target_clk_f); 233 234 if (delta < best_delta) { 235 best_delta = delta; 236 best_m = m; 237 best_n = n; 238 best_pl = pl; 239 240 if (best_delta == 0) 241 goto found_match; 242 } 243 } 244 } 245 } 246 } 247 248 found_match: 249 WARN_ON(best_delta == ~0); 250 251 if (best_delta != 0) 252 nv_debug(clk, "no best match for target @ %dMHz on gpc_pll", 253 target_clk_f); 254 255 clk->m = best_m; 256 clk->n = best_n; 257 clk->pl = best_pl; 258 259 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; 260 261 nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 262 target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); 263 return 0; 264 } 265 266 static int 267 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 268 { 269 struct nvkm_device *device = clk->base.subdev.device; 270 u32 val; 271 int ramp_timeout; 272 273 /* get old coefficients */ 274 val = nvkm_rd32(device, GPCPLL_COEFF); 275 /* do nothing if NDIV is the same */ 276 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 277 return 0; 278 279 /* setup */ 280 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 281 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 282 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 283 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 284 285 /* pll slowdown mode */ 286 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 287 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 288 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 289 290 /* new ndiv ready for ramp */ 291 val = nvkm_rd32(device, GPCPLL_COEFF); 292 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 293 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 294 udelay(1); 295 nvkm_wr32(device, GPCPLL_COEFF, val); 296 297 /* dynamic ramp to new ndiv */ 298 val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 299 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 300 udelay(1); 301 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val); 302 303 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 304 udelay(1); 305 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 306 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 307 break; 308 } 309 310 /* exit slowdown mode */ 311 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 312 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 313 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 314 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 315 316 if (ramp_timeout <= 0) { 317 nv_error(clk, "gpcpll dynamic ramp timeout\n"); 318 return -ETIMEDOUT; 319 } 320 321 return 0; 322 } 323 324 static void 325 _gk20a_pllg_enable(struct gk20a_clk *clk) 326 { 327 struct nvkm_device *device = clk->base.subdev.device; 328 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 329 nvkm_rd32(device, GPCPLL_CFG); 330 } 331 332 static void 333 _gk20a_pllg_disable(struct gk20a_clk *clk) 334 { 335 struct nvkm_device *device = clk->base.subdev.device; 336 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 337 nvkm_rd32(device, GPCPLL_CFG); 338 } 339 340 static int 341 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) 342 { 343 struct nvkm_device *device = clk->base.subdev.device; 344 u32 val, cfg; 345 u32 m_old, pl_old, n_lo; 346 347 /* get old coefficients */ 348 val = nvkm_rd32(device, GPCPLL_COEFF); 349 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 350 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 351 352 /* do NDIV slide if there is no change in M and PL */ 353 cfg = nvkm_rd32(device, GPCPLL_CFG); 354 if (allow_slide && clk->m == m_old && clk->pl == pl_old && 355 (cfg & GPCPLL_CFG_ENABLE)) { 356 return gk20a_pllg_slide(clk, clk->n); 357 } 358 359 /* slide down to NDIV_LO */ 360 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, 361 clk->parent_rate / MHZ); 362 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 363 int ret = gk20a_pllg_slide(clk, n_lo); 364 365 if (ret) 366 return ret; 367 } 368 369 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 370 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 371 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 372 373 /* put PLL in bypass before programming it */ 374 val = nvkm_rd32(device, SEL_VCO); 375 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 376 udelay(2); 377 nvkm_wr32(device, SEL_VCO, val); 378 379 /* get out from IDDQ */ 380 val = nvkm_rd32(device, GPCPLL_CFG); 381 if (val & GPCPLL_CFG_IDDQ) { 382 val &= ~GPCPLL_CFG_IDDQ; 383 nvkm_wr32(device, GPCPLL_CFG, val); 384 nvkm_rd32(device, GPCPLL_CFG); 385 udelay(2); 386 } 387 388 _gk20a_pllg_disable(clk); 389 390 nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n, 391 clk->pl); 392 393 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, 394 clk->parent_rate / MHZ); 395 val = clk->m << GPCPLL_COEFF_M_SHIFT; 396 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; 397 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; 398 nvkm_wr32(device, GPCPLL_COEFF, val); 399 400 _gk20a_pllg_enable(clk); 401 402 val = nvkm_rd32(device, GPCPLL_CFG); 403 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 404 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 405 nvkm_wr32(device, GPCPLL_CFG, val); 406 } 407 408 if (!nvkm_timer_wait_eq(clk, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, 409 GPCPLL_CFG_LOCK)) { 410 nv_error(clk, "%s: timeout waiting for pllg lock\n", __func__); 411 return -ETIMEDOUT; 412 } 413 414 /* switch to VCO mode */ 415 nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 416 417 /* restore out divider 1:1 */ 418 val = nvkm_rd32(device, GPC2CLK_OUT); 419 val &= ~GPC2CLK_OUT_VCODIV_MASK; 420 udelay(2); 421 nvkm_wr32(device, GPC2CLK_OUT, val); 422 423 /* slide up to new NDIV */ 424 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; 425 } 426 427 static int 428 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 429 { 430 int err; 431 432 err = _gk20a_pllg_program_mnp(clk, true); 433 if (err) 434 err = _gk20a_pllg_program_mnp(clk, false); 435 436 return err; 437 } 438 439 static void 440 gk20a_pllg_disable(struct gk20a_clk *clk) 441 { 442 struct nvkm_device *device = clk->base.subdev.device; 443 u32 val; 444 445 /* slide to VCO min */ 446 val = nvkm_rd32(device, GPCPLL_CFG); 447 if (val & GPCPLL_CFG_ENABLE) { 448 u32 coeff, m, n_lo; 449 450 coeff = nvkm_rd32(device, GPCPLL_COEFF); 451 m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 452 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, 453 clk->parent_rate / MHZ); 454 gk20a_pllg_slide(clk, n_lo); 455 } 456 457 /* put PLL in bypass before disabling it */ 458 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 459 460 _gk20a_pllg_disable(clk); 461 } 462 463 #define GK20A_CLK_GPC_MDIV 1000 464 465 static struct nvkm_domain 466 gk20a_domains[] = { 467 { nv_clk_src_crystal, 0xff }, 468 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 469 { nv_clk_src_max } 470 }; 471 472 static struct nvkm_pstate 473 gk20a_pstates[] = { 474 { 475 .base = { 476 .domain[nv_clk_src_gpc] = 72000, 477 .voltage = 0, 478 }, 479 }, 480 { 481 .base = { 482 .domain[nv_clk_src_gpc] = 108000, 483 .voltage = 1, 484 }, 485 }, 486 { 487 .base = { 488 .domain[nv_clk_src_gpc] = 180000, 489 .voltage = 2, 490 }, 491 }, 492 { 493 .base = { 494 .domain[nv_clk_src_gpc] = 252000, 495 .voltage = 3, 496 }, 497 }, 498 { 499 .base = { 500 .domain[nv_clk_src_gpc] = 324000, 501 .voltage = 4, 502 }, 503 }, 504 { 505 .base = { 506 .domain[nv_clk_src_gpc] = 396000, 507 .voltage = 5, 508 }, 509 }, 510 { 511 .base = { 512 .domain[nv_clk_src_gpc] = 468000, 513 .voltage = 6, 514 }, 515 }, 516 { 517 .base = { 518 .domain[nv_clk_src_gpc] = 540000, 519 .voltage = 7, 520 }, 521 }, 522 { 523 .base = { 524 .domain[nv_clk_src_gpc] = 612000, 525 .voltage = 8, 526 }, 527 }, 528 { 529 .base = { 530 .domain[nv_clk_src_gpc] = 648000, 531 .voltage = 9, 532 }, 533 }, 534 { 535 .base = { 536 .domain[nv_clk_src_gpc] = 684000, 537 .voltage = 10, 538 }, 539 }, 540 { 541 .base = { 542 .domain[nv_clk_src_gpc] = 708000, 543 .voltage = 11, 544 }, 545 }, 546 { 547 .base = { 548 .domain[nv_clk_src_gpc] = 756000, 549 .voltage = 12, 550 }, 551 }, 552 { 553 .base = { 554 .domain[nv_clk_src_gpc] = 804000, 555 .voltage = 13, 556 }, 557 }, 558 { 559 .base = { 560 .domain[nv_clk_src_gpc] = 852000, 561 .voltage = 14, 562 }, 563 }, 564 }; 565 566 static int 567 gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 568 { 569 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 570 struct nvkm_device *device = clk->base.subdev.device; 571 572 switch (src) { 573 case nv_clk_src_crystal: 574 return device->crystal; 575 case nv_clk_src_gpc: 576 gk20a_pllg_read_mnp(clk); 577 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; 578 default: 579 nv_error(clk, "invalid clock source %d\n", src); 580 return -EINVAL; 581 } 582 } 583 584 static int 585 gk20a_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 586 { 587 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 588 589 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 590 GK20A_CLK_GPC_MDIV); 591 } 592 593 static int 594 gk20a_clk_prog(struct nvkm_clk *obj) 595 { 596 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 597 598 return gk20a_pllg_program_mnp(clk); 599 } 600 601 static void 602 gk20a_clk_tidy(struct nvkm_clk *obj) 603 { 604 } 605 606 static int 607 gk20a_clk_fini(struct nvkm_object *object, bool suspend) 608 { 609 struct gk20a_clk *clk = (void *)object; 610 int ret; 611 612 ret = nvkm_clk_fini(&clk->base, false); 613 614 gk20a_pllg_disable(clk); 615 616 return ret; 617 } 618 619 static int 620 gk20a_clk_init(struct nvkm_object *object) 621 { 622 struct gk20a_clk *clk = (void *)object; 623 struct nvkm_device *device = clk->base.subdev.device; 624 int ret; 625 626 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 627 628 ret = nvkm_clk_init(&clk->base); 629 if (ret) 630 return ret; 631 632 ret = gk20a_clk_prog(&clk->base); 633 if (ret) { 634 nv_error(clk, "cannot initialize clock\n"); 635 return ret; 636 } 637 638 return 0; 639 } 640 641 static int 642 gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 643 struct nvkm_oclass *oclass, void *data, u32 size, 644 struct nvkm_object **pobject) 645 { 646 struct gk20a_clk *clk; 647 struct nouveau_platform_device *plat; 648 int ret; 649 int i; 650 651 /* Finish initializing the pstates */ 652 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { 653 INIT_LIST_HEAD(&gk20a_pstates[i].list); 654 gk20a_pstates[i].pstate = i + 1; 655 } 656 657 ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains, 658 gk20a_pstates, ARRAY_SIZE(gk20a_pstates), 659 true, &clk); 660 *pobject = nv_object(clk); 661 if (ret) 662 return ret; 663 664 clk->params = &gk20a_pllg_params; 665 666 plat = nv_device_to_platform(nv_device(parent)); 667 clk->parent_rate = clk_get_rate(plat->gpu->clk); 668 nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ); 669 670 clk->base.read = gk20a_clk_read; 671 clk->base.calc = gk20a_clk_calc; 672 clk->base.prog = gk20a_clk_prog; 673 clk->base.tidy = gk20a_clk_tidy; 674 return 0; 675 } 676 677 struct nvkm_oclass 678 gk20a_clk_oclass = { 679 .handle = NV_SUBDEV(CLK, 0xea), 680 .ofuncs = &(struct nvkm_ofuncs) { 681 .ctor = gk20a_clk_ctor, 682 .dtor = _nvkm_subdev_dtor, 683 .init = gk20a_clk_init, 684 .fini = gk20a_clk_fini, 685 }, 686 }; 687