1 /* 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #include "priv.h" 26 #include "gk20a.h" 27 28 #include <core/tegra.h> 29 #include <subdev/timer.h> 30 31 #define KHZ (1000) 32 #define MHZ (KHZ * 1000) 33 34 #define MASK(w) ((1 << (w)) - 1) 35 36 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 37 #define GPCPLL_CFG_ENABLE BIT(0) 38 #define GPCPLL_CFG_IDDQ BIT(1) 39 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 40 #define GPCPLL_CFG_LOCK BIT(17) 41 42 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 43 #define GPCPLL_COEFF_M_SHIFT 0 44 #define GPCPLL_COEFF_M_WIDTH 8 45 #define GPCPLL_COEFF_N_SHIFT 8 46 #define GPCPLL_COEFF_N_WIDTH 8 47 #define GPCPLL_COEFF_P_SHIFT 16 48 #define GPCPLL_COEFF_P_WIDTH 6 49 50 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 51 #define GPCPLL_CFG2_SETUP2_SHIFT 16 52 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 53 54 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 55 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 56 57 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 58 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 59 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 60 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 61 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 62 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 63 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 64 65 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 66 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 67 68 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 69 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 70 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 71 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 72 #define GPC2CLK_OUT_VCODIV_WIDTH 6 73 #define GPC2CLK_OUT_VCODIV_SHIFT 8 74 #define GPC2CLK_OUT_VCODIV1 0 75 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 76 GPC2CLK_OUT_VCODIV_SHIFT) 77 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 78 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 79 #define GPC2CLK_OUT_BYPDIV31 0x3c 80 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 81 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 82 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 83 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 84 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 85 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 86 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 87 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 88 89 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 90 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 92 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 93 94 static const u8 _pl_to_div[] = { 95 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 96 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 97 }; 98 99 static u32 pl_to_div(u32 pl) 100 { 101 if (pl >= ARRAY_SIZE(_pl_to_div)) 102 return 1; 103 104 return _pl_to_div[pl]; 105 } 106 107 static u32 div_to_pl(u32 div) 108 { 109 u32 pl; 110 111 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { 112 if (_pl_to_div[pl] >= div) 113 return pl; 114 } 115 116 return ARRAY_SIZE(_pl_to_div) - 1; 117 } 118 119 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 120 .min_vco = 1000000, .max_vco = 2064000, 121 .min_u = 12000, .max_u = 38000, 122 .min_m = 1, .max_m = 255, 123 .min_n = 8, .max_n = 255, 124 .min_pl = 1, .max_pl = 32, 125 }; 126 127 static void 128 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) 129 { 130 struct nvkm_device *device = clk->base.subdev.device; 131 u32 val; 132 133 val = nvkm_rd32(device, GPCPLL_COEFF); 134 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 135 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 136 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 137 } 138 139 static void 140 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) 141 { 142 struct nvkm_device *device = clk->base.subdev.device; 143 u32 val; 144 145 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; 146 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 147 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; 148 nvkm_wr32(device, GPCPLL_COEFF, val); 149 } 150 151 static u32 152 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) 153 { 154 u32 rate; 155 u32 divider; 156 157 rate = clk->parent_rate * pll->n; 158 divider = pll->m * clk->pl_to_div(pll->pl); 159 160 return rate / divider / 2; 161 } 162 163 static int 164 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate, 165 struct gk20a_pll *pll) 166 { 167 struct nvkm_subdev *subdev = &clk->base.subdev; 168 u32 target_clk_f, ref_clk_f, target_freq; 169 u32 min_vco_f, max_vco_f; 170 u32 low_pl, high_pl, best_pl; 171 u32 target_vco_f; 172 u32 best_m, best_n; 173 u32 best_delta = ~0; 174 u32 pl; 175 176 target_clk_f = rate * 2 / KHZ; 177 ref_clk_f = clk->parent_rate / KHZ; 178 179 target_vco_f = target_clk_f + target_clk_f / 50; 180 max_vco_f = max(clk->params->max_vco, target_vco_f); 181 min_vco_f = clk->params->min_vco; 182 best_m = clk->params->max_m; 183 best_n = clk->params->min_n; 184 best_pl = clk->params->min_pl; 185 186 /* min_pl <= high_pl <= max_pl */ 187 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 188 high_pl = min(high_pl, clk->params->max_pl); 189 high_pl = max(high_pl, clk->params->min_pl); 190 high_pl = clk->div_to_pl(high_pl); 191 192 /* min_pl <= low_pl <= max_pl */ 193 low_pl = min_vco_f / target_vco_f; 194 low_pl = min(low_pl, clk->params->max_pl); 195 low_pl = max(low_pl, clk->params->min_pl); 196 low_pl = clk->div_to_pl(low_pl); 197 198 nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 199 clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl)); 200 201 /* Select lowest possible VCO */ 202 for (pl = low_pl; pl <= high_pl; pl++) { 203 u32 m, n, n2; 204 205 target_vco_f = target_clk_f * clk->pl_to_div(pl); 206 207 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 208 u32 u_f = ref_clk_f / m; 209 210 if (u_f < clk->params->min_u) 211 break; 212 if (u_f > clk->params->max_u) 213 continue; 214 215 n = (target_vco_f * m) / ref_clk_f; 216 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 217 218 if (n > clk->params->max_n) 219 break; 220 221 for (; n <= n2; n++) { 222 u32 vco_f; 223 224 if (n < clk->params->min_n) 225 continue; 226 if (n > clk->params->max_n) 227 break; 228 229 vco_f = ref_clk_f * n / m; 230 231 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 232 u32 delta, lwv; 233 234 lwv = (vco_f + (clk->pl_to_div(pl) / 2)) 235 / clk->pl_to_div(pl); 236 delta = abs(lwv - target_clk_f); 237 238 if (delta < best_delta) { 239 best_delta = delta; 240 best_m = m; 241 best_n = n; 242 best_pl = pl; 243 244 if (best_delta == 0) 245 goto found_match; 246 } 247 } 248 } 249 } 250 } 251 252 found_match: 253 WARN_ON(best_delta == ~0); 254 255 if (best_delta != 0) 256 nvkm_debug(subdev, 257 "no best match for target @ %dMHz on gpc_pll", 258 target_clk_f / KHZ); 259 260 pll->m = best_m; 261 pll->n = best_n; 262 pll->pl = best_pl; 263 264 target_freq = gk20a_pllg_calc_rate(clk, pll); 265 266 nvkm_debug(subdev, 267 "actual target freq %d KHz, M %d, N %d, PL %d(div%d)\n", 268 target_freq / KHZ, pll->m, pll->n, pll->pl, 269 clk->pl_to_div(pll->pl)); 270 return 0; 271 } 272 273 static int 274 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 275 { 276 struct nvkm_subdev *subdev = &clk->base.subdev; 277 struct nvkm_device *device = subdev->device; 278 struct gk20a_pll pll; 279 int ret = 0; 280 281 /* get old coefficients */ 282 gk20a_pllg_read_mnp(clk, &pll); 283 /* do nothing if NDIV is the same */ 284 if (n == pll.n) 285 return 0; 286 287 /* pll slowdown mode */ 288 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 289 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 290 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 291 292 /* new ndiv ready for ramp */ 293 pll.n = n; 294 udelay(1); 295 gk20a_pllg_write_mnp(clk, &pll); 296 297 /* dynamic ramp to new ndiv */ 298 udelay(1); 299 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 300 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 301 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT)); 302 303 /* wait for ramping to complete */ 304 if (nvkm_wait_usec(device, 500, GPC_BCAST_NDIV_SLOWDOWN_DEBUG, 305 GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK, 306 GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) < 0) 307 ret = -ETIMEDOUT; 308 309 /* exit slowdown mode */ 310 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 311 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 312 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 313 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 314 315 return ret; 316 } 317 318 static void 319 gk20a_pllg_enable(struct gk20a_clk *clk) 320 { 321 struct nvkm_device *device = clk->base.subdev.device; 322 323 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 324 nvkm_rd32(device, GPCPLL_CFG); 325 } 326 327 static void 328 gk20a_pllg_disable(struct gk20a_clk *clk) 329 { 330 struct nvkm_device *device = clk->base.subdev.device; 331 332 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 333 nvkm_rd32(device, GPCPLL_CFG); 334 } 335 336 static int 337 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll, 338 bool allow_slide) 339 { 340 struct nvkm_subdev *subdev = &clk->base.subdev; 341 struct nvkm_device *device = subdev->device; 342 u32 val, cfg; 343 struct gk20a_pll old_pll; 344 u32 n_lo; 345 346 /* get old coefficients */ 347 gk20a_pllg_read_mnp(clk, &old_pll); 348 349 /* do NDIV slide if there is no change in M and PL */ 350 cfg = nvkm_rd32(device, GPCPLL_CFG); 351 if (allow_slide && pll->m == old_pll.m && 352 pll->pl == old_pll.pl && (cfg & GPCPLL_CFG_ENABLE)) { 353 return gk20a_pllg_slide(clk, pll->n); 354 } 355 356 /* slide down to NDIV_LO */ 357 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 358 int ret; 359 360 n_lo = DIV_ROUND_UP(old_pll.m * clk->params->min_vco, 361 clk->parent_rate / KHZ); 362 ret = gk20a_pllg_slide(clk, n_lo); 363 364 if (ret) 365 return ret; 366 } 367 368 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 369 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 370 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 371 372 /* put PLL in bypass before programming it */ 373 val = nvkm_rd32(device, SEL_VCO); 374 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 375 udelay(2); 376 nvkm_wr32(device, SEL_VCO, val); 377 378 /* get out from IDDQ */ 379 val = nvkm_rd32(device, GPCPLL_CFG); 380 if (val & GPCPLL_CFG_IDDQ) { 381 val &= ~GPCPLL_CFG_IDDQ; 382 nvkm_wr32(device, GPCPLL_CFG, val); 383 nvkm_rd32(device, GPCPLL_CFG); 384 udelay(2); 385 } 386 387 gk20a_pllg_disable(clk); 388 389 nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, 390 pll->m, pll->n, pll->pl); 391 392 old_pll = *pll; 393 if (allow_slide) 394 old_pll.n = DIV_ROUND_UP(pll->m * clk->params->min_vco, 395 clk->parent_rate / KHZ); 396 gk20a_pllg_write_mnp(clk, &old_pll); 397 398 gk20a_pllg_enable(clk); 399 400 val = nvkm_rd32(device, GPCPLL_CFG); 401 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 402 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 403 nvkm_wr32(device, GPCPLL_CFG, val); 404 } 405 406 if (nvkm_usec(device, 300, 407 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK) 408 break; 409 ) < 0) 410 return -ETIMEDOUT; 411 412 /* switch to VCO mode */ 413 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 414 BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 415 416 /* restore out divider 1:1 */ 417 val = nvkm_rd32(device, GPC2CLK_OUT); 418 if ((val & GPC2CLK_OUT_VCODIV_MASK) != 419 (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT)) { 420 val &= ~GPC2CLK_OUT_VCODIV_MASK; 421 val |= GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT; 422 udelay(2); 423 nvkm_wr32(device, GPC2CLK_OUT, val); 424 /* Intentional 2nd write to assure linear divider operation */ 425 nvkm_wr32(device, GPC2CLK_OUT, val); 426 nvkm_rd32(device, GPC2CLK_OUT); 427 } 428 429 /* slide up to new NDIV */ 430 return allow_slide ? gk20a_pllg_slide(clk, pll->n) : 0; 431 } 432 433 static int 434 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 435 { 436 int err; 437 438 err = _gk20a_pllg_program_mnp(clk, &clk->pll, true); 439 if (err) 440 err = _gk20a_pllg_program_mnp(clk, &clk->pll, false); 441 442 return err; 443 } 444 445 static struct nvkm_pstate 446 gk20a_pstates[] = { 447 { 448 .base = { 449 .domain[nv_clk_src_gpc] = 72000, 450 .voltage = 0, 451 }, 452 }, 453 { 454 .base = { 455 .domain[nv_clk_src_gpc] = 108000, 456 .voltage = 1, 457 }, 458 }, 459 { 460 .base = { 461 .domain[nv_clk_src_gpc] = 180000, 462 .voltage = 2, 463 }, 464 }, 465 { 466 .base = { 467 .domain[nv_clk_src_gpc] = 252000, 468 .voltage = 3, 469 }, 470 }, 471 { 472 .base = { 473 .domain[nv_clk_src_gpc] = 324000, 474 .voltage = 4, 475 }, 476 }, 477 { 478 .base = { 479 .domain[nv_clk_src_gpc] = 396000, 480 .voltage = 5, 481 }, 482 }, 483 { 484 .base = { 485 .domain[nv_clk_src_gpc] = 468000, 486 .voltage = 6, 487 }, 488 }, 489 { 490 .base = { 491 .domain[nv_clk_src_gpc] = 540000, 492 .voltage = 7, 493 }, 494 }, 495 { 496 .base = { 497 .domain[nv_clk_src_gpc] = 612000, 498 .voltage = 8, 499 }, 500 }, 501 { 502 .base = { 503 .domain[nv_clk_src_gpc] = 648000, 504 .voltage = 9, 505 }, 506 }, 507 { 508 .base = { 509 .domain[nv_clk_src_gpc] = 684000, 510 .voltage = 10, 511 }, 512 }, 513 { 514 .base = { 515 .domain[nv_clk_src_gpc] = 708000, 516 .voltage = 11, 517 }, 518 }, 519 { 520 .base = { 521 .domain[nv_clk_src_gpc] = 756000, 522 .voltage = 12, 523 }, 524 }, 525 { 526 .base = { 527 .domain[nv_clk_src_gpc] = 804000, 528 .voltage = 13, 529 }, 530 }, 531 { 532 .base = { 533 .domain[nv_clk_src_gpc] = 852000, 534 .voltage = 14, 535 }, 536 }, 537 }; 538 539 int 540 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) 541 { 542 struct gk20a_clk *clk = gk20a_clk(base); 543 struct nvkm_subdev *subdev = &clk->base.subdev; 544 struct nvkm_device *device = subdev->device; 545 struct gk20a_pll pll; 546 547 switch (src) { 548 case nv_clk_src_crystal: 549 return device->crystal; 550 case nv_clk_src_gpc: 551 gk20a_pllg_read_mnp(clk, &pll); 552 return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV; 553 default: 554 nvkm_error(subdev, "invalid clock source %d\n", src); 555 return -EINVAL; 556 } 557 } 558 559 int 560 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) 561 { 562 struct gk20a_clk *clk = gk20a_clk(base); 563 564 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 565 GK20A_CLK_GPC_MDIV, &clk->pll); 566 } 567 568 int 569 gk20a_clk_prog(struct nvkm_clk *base) 570 { 571 struct gk20a_clk *clk = gk20a_clk(base); 572 573 return gk20a_pllg_program_mnp(clk); 574 } 575 576 void 577 gk20a_clk_tidy(struct nvkm_clk *base) 578 { 579 } 580 581 int 582 gk20a_clk_setup_slide(struct gk20a_clk *clk) 583 { 584 struct nvkm_subdev *subdev = &clk->base.subdev; 585 struct nvkm_device *device = subdev->device; 586 u32 step_a, step_b; 587 588 switch (clk->parent_rate) { 589 case 12000000: 590 case 12800000: 591 case 13000000: 592 step_a = 0x2b; 593 step_b = 0x0b; 594 break; 595 case 19200000: 596 step_a = 0x12; 597 step_b = 0x08; 598 break; 599 case 38400000: 600 step_a = 0x04; 601 step_b = 0x05; 602 break; 603 default: 604 nvkm_error(subdev, "invalid parent clock rate %u KHz", 605 clk->parent_rate / KHZ); 606 return -EINVAL; 607 } 608 609 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 610 step_a << GPCPLL_CFG2_PLL_STEPA_SHIFT); 611 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 612 step_b << GPCPLL_CFG3_PLL_STEPB_SHIFT); 613 614 return 0; 615 } 616 617 void 618 gk20a_clk_fini(struct nvkm_clk *base) 619 { 620 struct nvkm_device *device = base->subdev.device; 621 struct gk20a_clk *clk = gk20a_clk(base); 622 u32 val; 623 624 /* slide to VCO min */ 625 val = nvkm_rd32(device, GPCPLL_CFG); 626 if (val & GPCPLL_CFG_ENABLE) { 627 struct gk20a_pll pll; 628 u32 n_lo; 629 630 gk20a_pllg_read_mnp(clk, &pll); 631 n_lo = DIV_ROUND_UP(pll.m * clk->params->min_vco, 632 clk->parent_rate / KHZ); 633 gk20a_pllg_slide(clk, n_lo); 634 } 635 636 /* put PLL in bypass before disabling it */ 637 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 638 639 gk20a_pllg_disable(clk); 640 } 641 642 static int 643 gk20a_clk_init(struct nvkm_clk *base) 644 { 645 struct gk20a_clk *clk = gk20a_clk(base); 646 struct nvkm_subdev *subdev = &clk->base.subdev; 647 struct nvkm_device *device = subdev->device; 648 int ret; 649 650 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, 651 GPC2CLK_OUT_INIT_VAL); 652 653 ret = gk20a_clk_setup_slide(clk); 654 if (ret) 655 return ret; 656 657 /* Start with lowest frequency */ 658 base->func->calc(base, &base->func->pstates[0].base); 659 ret = base->func->prog(&clk->base); 660 if (ret) { 661 nvkm_error(subdev, "cannot initialize clock\n"); 662 return ret; 663 } 664 665 return 0; 666 } 667 668 static const struct nvkm_clk_func 669 gk20a_clk = { 670 .init = gk20a_clk_init, 671 .fini = gk20a_clk_fini, 672 .read = gk20a_clk_read, 673 .calc = gk20a_clk_calc, 674 .prog = gk20a_clk_prog, 675 .tidy = gk20a_clk_tidy, 676 .pstates = gk20a_pstates, 677 .nr_pstates = ARRAY_SIZE(gk20a_pstates), 678 .domains = { 679 { nv_clk_src_crystal, 0xff }, 680 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 681 { nv_clk_src_max } 682 } 683 }; 684 685 int 686 _gk20a_clk_ctor(struct nvkm_device *device, int index, 687 const struct nvkm_clk_func *func, 688 const struct gk20a_clk_pllg_params *params, 689 struct gk20a_clk *clk) 690 { 691 struct nvkm_device_tegra *tdev = device->func->tegra(device); 692 int ret; 693 int i; 694 695 /* Finish initializing the pstates */ 696 for (i = 0; i < func->nr_pstates; i++) { 697 INIT_LIST_HEAD(&func->pstates[i].list); 698 func->pstates[i].pstate = i + 1; 699 } 700 701 clk->params = params; 702 clk->parent_rate = clk_get_rate(tdev->clk); 703 704 ret = nvkm_clk_ctor(func, device, index, true, &clk->base); 705 if (ret) 706 return ret; 707 708 nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n", 709 clk->parent_rate / KHZ); 710 711 return 0; 712 } 713 714 int 715 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) 716 { 717 struct gk20a_clk *clk; 718 int ret; 719 720 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 721 if (!clk) 722 return -ENOMEM; 723 *pclk = &clk->base; 724 725 ret = _gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params, 726 clk); 727 728 clk->pl_to_div = pl_to_div; 729 clk->div_to_pl = div_to_pl; 730 731 return ret; 732 } 733