1 /*
2  * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  *
22  * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
23  *
24  */
25 #include "priv.h"
26 #include "gk20a.h"
27 
28 #include <core/tegra.h>
29 #include <subdev/timer.h>
30 
31 #define KHZ (1000)
32 #define MHZ (KHZ * 1000)
33 
34 #define MASK(w)	((1 << (w)) - 1)
35 
36 #define GPCPLL_CFG		(SYS_GPCPLL_CFG_BASE + 0)
37 #define GPCPLL_CFG_ENABLE	BIT(0)
38 #define GPCPLL_CFG_IDDQ		BIT(1)
39 #define GPCPLL_CFG_LOCK_DET_OFF	BIT(4)
40 #define GPCPLL_CFG_LOCK		BIT(17)
41 
42 #define GPCPLL_COEFF		(SYS_GPCPLL_CFG_BASE + 4)
43 #define GPCPLL_COEFF_M_SHIFT	0
44 #define GPCPLL_COEFF_M_WIDTH	8
45 #define GPCPLL_COEFF_N_SHIFT	8
46 #define GPCPLL_COEFF_N_WIDTH	8
47 #define GPCPLL_COEFF_P_SHIFT	16
48 #define GPCPLL_COEFF_P_WIDTH	6
49 
50 #define GPCPLL_CFG2			(SYS_GPCPLL_CFG_BASE + 0xc)
51 #define GPCPLL_CFG2_SETUP2_SHIFT	16
52 #define GPCPLL_CFG2_PLL_STEPA_SHIFT	24
53 
54 #define GPCPLL_CFG3			(SYS_GPCPLL_CFG_BASE + 0x18)
55 #define GPCPLL_CFG3_PLL_STEPB_SHIFT	16
56 
57 #define GPC_BCASE_GPCPLL_CFG_BASE		0x00132800
58 #define GPCPLL_NDIV_SLOWDOWN			(SYS_GPCPLL_CFG_BASE + 0x1c)
59 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT	0
60 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT	8
61 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT	16
62 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT	22
63 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT	31
64 
65 #define SEL_VCO				(SYS_GPCPLL_CFG_BASE + 0x100)
66 #define SEL_VCO_GPC2CLK_OUT_SHIFT	0
67 
68 #define GPC2CLK_OUT			(SYS_GPCPLL_CFG_BASE + 0x250)
69 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH	1
70 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT	31
71 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE	1
72 #define GPC2CLK_OUT_VCODIV_WIDTH	6
73 #define GPC2CLK_OUT_VCODIV_SHIFT	8
74 #define GPC2CLK_OUT_VCODIV1		0
75 #define GPC2CLK_OUT_VCODIV2		2
76 #define GPC2CLK_OUT_VCODIV_MASK		(MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
77 					GPC2CLK_OUT_VCODIV_SHIFT)
78 #define GPC2CLK_OUT_BYPDIV_WIDTH	6
79 #define GPC2CLK_OUT_BYPDIV_SHIFT	0
80 #define GPC2CLK_OUT_BYPDIV31		0x3c
81 #define GPC2CLK_OUT_INIT_MASK	((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
82 		GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
83 		| (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
84 		| (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
85 #define GPC2CLK_OUT_INIT_VAL	((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
86 		GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
87 		| (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
88 		| (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
89 
90 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG	(GPC_BCASE_GPCPLL_CFG_BASE + 0xa0)
91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT	24
92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
93 	    (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
94 
95 static const u8 _pl_to_div[] = {
96 /* PL:   0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
97 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
98 };
99 
100 static u32 pl_to_div(u32 pl)
101 {
102 	if (pl >= ARRAY_SIZE(_pl_to_div))
103 		return 1;
104 
105 	return _pl_to_div[pl];
106 }
107 
108 static u32 div_to_pl(u32 div)
109 {
110 	u32 pl;
111 
112 	for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) {
113 		if (_pl_to_div[pl] >= div)
114 			return pl;
115 	}
116 
117 	return ARRAY_SIZE(_pl_to_div) - 1;
118 }
119 
120 static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
121 	.min_vco = 1000000, .max_vco = 2064000,
122 	.min_u = 12000, .max_u = 38000,
123 	.min_m = 1, .max_m = 255,
124 	.min_n = 8, .max_n = 255,
125 	.min_pl = 1, .max_pl = 32,
126 };
127 
128 static void
129 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
130 {
131 	struct nvkm_device *device = clk->base.subdev.device;
132 	u32 val;
133 
134 	val = nvkm_rd32(device, GPCPLL_COEFF);
135 	pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
136 	pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
137 	pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
138 }
139 
140 static void
141 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
142 {
143 	struct nvkm_device *device = clk->base.subdev.device;
144 	u32 val;
145 
146 	val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
147 	val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
148 	val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
149 	nvkm_wr32(device, GPCPLL_COEFF, val);
150 }
151 
152 static u32
153 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
154 {
155 	u32 rate;
156 	u32 divider;
157 
158 	rate = clk->parent_rate * pll->n;
159 	divider = pll->m * clk->pl_to_div(pll->pl);
160 
161 	return rate / divider / 2;
162 }
163 
164 static u32
165 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
166 {
167 	return DIV_ROUND_UP(pll->m * clk->params->min_vco,
168 			    clk->parent_rate / KHZ);
169 }
170 
171 static int
172 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate,
173 		    struct gk20a_pll *pll)
174 {
175 	struct nvkm_subdev *subdev = &clk->base.subdev;
176 	u32 target_clk_f, ref_clk_f, target_freq;
177 	u32 min_vco_f, max_vco_f;
178 	u32 low_pl, high_pl, best_pl;
179 	u32 target_vco_f;
180 	u32 best_m, best_n;
181 	u32 best_delta = ~0;
182 	u32 pl;
183 
184 	target_clk_f = rate * 2 / KHZ;
185 	ref_clk_f = clk->parent_rate / KHZ;
186 
187 	target_vco_f = target_clk_f + target_clk_f / 50;
188 	max_vco_f = max(clk->params->max_vco, target_vco_f);
189 	min_vco_f = clk->params->min_vco;
190 	best_m = clk->params->max_m;
191 	best_n = clk->params->min_n;
192 	best_pl = clk->params->min_pl;
193 
194 	/* min_pl <= high_pl <= max_pl */
195 	high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
196 	high_pl = min(high_pl, clk->params->max_pl);
197 	high_pl = max(high_pl, clk->params->min_pl);
198 	high_pl = clk->div_to_pl(high_pl);
199 
200 	/* min_pl <= low_pl <= max_pl */
201 	low_pl = min_vco_f / target_vco_f;
202 	low_pl = min(low_pl, clk->params->max_pl);
203 	low_pl = max(low_pl, clk->params->min_pl);
204 	low_pl = clk->div_to_pl(low_pl);
205 
206 	nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
207 		   clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl));
208 
209 	/* Select lowest possible VCO */
210 	for (pl = low_pl; pl <= high_pl; pl++) {
211 		u32 m, n, n2;
212 
213 		target_vco_f = target_clk_f * clk->pl_to_div(pl);
214 
215 		for (m = clk->params->min_m; m <= clk->params->max_m; m++) {
216 			u32 u_f = ref_clk_f / m;
217 
218 			if (u_f < clk->params->min_u)
219 				break;
220 			if (u_f > clk->params->max_u)
221 				continue;
222 
223 			n = (target_vco_f * m) / ref_clk_f;
224 			n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
225 
226 			if (n > clk->params->max_n)
227 				break;
228 
229 			for (; n <= n2; n++) {
230 				u32 vco_f;
231 
232 				if (n < clk->params->min_n)
233 					continue;
234 				if (n > clk->params->max_n)
235 					break;
236 
237 				vco_f = ref_clk_f * n / m;
238 
239 				if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
240 					u32 delta, lwv;
241 
242 					lwv = (vco_f + (clk->pl_to_div(pl) / 2))
243 						/ clk->pl_to_div(pl);
244 					delta = abs(lwv - target_clk_f);
245 
246 					if (delta < best_delta) {
247 						best_delta = delta;
248 						best_m = m;
249 						best_n = n;
250 						best_pl = pl;
251 
252 						if (best_delta == 0)
253 							goto found_match;
254 					}
255 				}
256 			}
257 		}
258 	}
259 
260 found_match:
261 	WARN_ON(best_delta == ~0);
262 
263 	if (best_delta != 0)
264 		nvkm_debug(subdev,
265 			   "no best match for target @ %dMHz on gpc_pll",
266 			   target_clk_f / KHZ);
267 
268 	pll->m = best_m;
269 	pll->n = best_n;
270 	pll->pl = best_pl;
271 
272 	target_freq = gk20a_pllg_calc_rate(clk, pll);
273 
274 	nvkm_debug(subdev,
275 		   "actual target freq %d KHz, M %d, N %d, PL %d(div%d)\n",
276 		   target_freq / KHZ, pll->m, pll->n, pll->pl,
277 		   clk->pl_to_div(pll->pl));
278 	return 0;
279 }
280 
281 static int
282 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
283 {
284 	struct nvkm_subdev *subdev = &clk->base.subdev;
285 	struct nvkm_device *device = subdev->device;
286 	struct gk20a_pll pll;
287 	int ret = 0;
288 
289 	/* get old coefficients */
290 	gk20a_pllg_read_mnp(clk, &pll);
291 	/* do nothing if NDIV is the same */
292 	if (n == pll.n)
293 		return 0;
294 
295 	/* pll slowdown mode */
296 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
297 		BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
298 		BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
299 
300 	/* new ndiv ready for ramp */
301 	pll.n = n;
302 	udelay(1);
303 	gk20a_pllg_write_mnp(clk, &pll);
304 
305 	/* dynamic ramp to new ndiv */
306 	udelay(1);
307 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
308 		  BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT),
309 		  BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT));
310 
311 	/* wait for ramping to complete */
312 	if (nvkm_wait_usec(device, 500, GPC_BCAST_NDIV_SLOWDOWN_DEBUG,
313 		GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK,
314 		GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) < 0)
315 		ret = -ETIMEDOUT;
316 
317 	/* exit slowdown mode */
318 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
319 		BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
320 		BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
321 	nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
322 
323 	return ret;
324 }
325 
326 static bool
327 gk20a_pllg_is_enabled(struct gk20a_clk *clk)
328 {
329 	struct nvkm_device *device = clk->base.subdev.device;
330 	u32 val;
331 
332 	val = nvkm_rd32(device, GPCPLL_CFG);
333 	return val & GPCPLL_CFG_ENABLE;
334 }
335 
336 static int
337 gk20a_pllg_enable(struct gk20a_clk *clk)
338 {
339 	struct nvkm_device *device = clk->base.subdev.device;
340 	u32 val;
341 
342 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
343 	nvkm_rd32(device, GPCPLL_CFG);
344 
345 	/* enable lock detection */
346 	val = nvkm_rd32(device, GPCPLL_CFG);
347 	if (val & GPCPLL_CFG_LOCK_DET_OFF) {
348 		val &= ~GPCPLL_CFG_LOCK_DET_OFF;
349 		nvkm_wr32(device, GPCPLL_CFG, val);
350 	}
351 
352 	/* wait for lock */
353 	if (nvkm_wait_usec(device, 300, GPCPLL_CFG, GPCPLL_CFG_LOCK,
354 			   GPCPLL_CFG_LOCK) < 0)
355 		return -ETIMEDOUT;
356 
357 	/* switch to VCO mode */
358 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),
359 		BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
360 
361 	return 0;
362 }
363 
364 static void
365 gk20a_pllg_disable(struct gk20a_clk *clk)
366 {
367 	struct nvkm_device *device = clk->base.subdev.device;
368 
369 	/* put PLL in bypass before disabling it */
370 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
371 
372 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
373 	nvkm_rd32(device, GPCPLL_CFG);
374 }
375 
376 static int
377 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
378 {
379 	struct nvkm_subdev *subdev = &clk->base.subdev;
380 	struct nvkm_device *device = subdev->device;
381 	struct gk20a_pll cur_pll;
382 	int ret;
383 
384 	gk20a_pllg_read_mnp(clk, &cur_pll);
385 
386 	/* split VCO-to-bypass jump in half by setting out divider 1:2 */
387 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
388 		  GPC2CLK_OUT_VCODIV2 << GPC2CLK_OUT_VCODIV_SHIFT);
389 	/* Intentional 2nd write to assure linear divider operation */
390 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
391 		  GPC2CLK_OUT_VCODIV2 << GPC2CLK_OUT_VCODIV_SHIFT);
392 	nvkm_rd32(device, GPC2CLK_OUT);
393 	udelay(2);
394 
395 	gk20a_pllg_disable(clk);
396 
397 	gk20a_pllg_write_mnp(clk, pll);
398 
399 	ret = gk20a_pllg_enable(clk);
400 	if (ret)
401 		return ret;
402 
403 	/* restore out divider 1:1 */
404 	udelay(2);
405 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
406 		  GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT);
407 	/* Intentional 2nd write to assure linear divider operation */
408 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
409 		  GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT);
410 	nvkm_rd32(device, GPC2CLK_OUT);
411 
412 	return 0;
413 }
414 
415 static int
416 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)
417 {
418 	struct gk20a_pll cur_pll;
419 	int ret;
420 
421 	if (gk20a_pllg_is_enabled(clk)) {
422 		gk20a_pllg_read_mnp(clk, &cur_pll);
423 
424 		/* just do NDIV slide if there is no change to M and PL */
425 		if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
426 			return gk20a_pllg_slide(clk, pll->n);
427 
428 		/* slide down to current NDIV_LO */
429 		cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll);
430 		ret = gk20a_pllg_slide(clk, cur_pll.n);
431 		if (ret)
432 			return ret;
433 	}
434 
435 	/* program MNP with the new clock parameters and new NDIV_LO */
436 	cur_pll = *pll;
437 	cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll);
438 	ret = gk20a_pllg_program_mnp(clk, &cur_pll);
439 	if (ret)
440 		return ret;
441 
442 	/* slide up to new NDIV */
443 	return gk20a_pllg_slide(clk, pll->n);
444 }
445 
446 static struct nvkm_pstate
447 gk20a_pstates[] = {
448 	{
449 		.base = {
450 			.domain[nv_clk_src_gpc] = 72000,
451 			.voltage = 0,
452 		},
453 	},
454 	{
455 		.base = {
456 			.domain[nv_clk_src_gpc] = 108000,
457 			.voltage = 1,
458 		},
459 	},
460 	{
461 		.base = {
462 			.domain[nv_clk_src_gpc] = 180000,
463 			.voltage = 2,
464 		},
465 	},
466 	{
467 		.base = {
468 			.domain[nv_clk_src_gpc] = 252000,
469 			.voltage = 3,
470 		},
471 	},
472 	{
473 		.base = {
474 			.domain[nv_clk_src_gpc] = 324000,
475 			.voltage = 4,
476 		},
477 	},
478 	{
479 		.base = {
480 			.domain[nv_clk_src_gpc] = 396000,
481 			.voltage = 5,
482 		},
483 	},
484 	{
485 		.base = {
486 			.domain[nv_clk_src_gpc] = 468000,
487 			.voltage = 6,
488 		},
489 	},
490 	{
491 		.base = {
492 			.domain[nv_clk_src_gpc] = 540000,
493 			.voltage = 7,
494 		},
495 	},
496 	{
497 		.base = {
498 			.domain[nv_clk_src_gpc] = 612000,
499 			.voltage = 8,
500 		},
501 	},
502 	{
503 		.base = {
504 			.domain[nv_clk_src_gpc] = 648000,
505 			.voltage = 9,
506 		},
507 	},
508 	{
509 		.base = {
510 			.domain[nv_clk_src_gpc] = 684000,
511 			.voltage = 10,
512 		},
513 	},
514 	{
515 		.base = {
516 			.domain[nv_clk_src_gpc] = 708000,
517 			.voltage = 11,
518 		},
519 	},
520 	{
521 		.base = {
522 			.domain[nv_clk_src_gpc] = 756000,
523 			.voltage = 12,
524 		},
525 	},
526 	{
527 		.base = {
528 			.domain[nv_clk_src_gpc] = 804000,
529 			.voltage = 13,
530 		},
531 	},
532 	{
533 		.base = {
534 			.domain[nv_clk_src_gpc] = 852000,
535 			.voltage = 14,
536 		},
537 	},
538 };
539 
540 int
541 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
542 {
543 	struct gk20a_clk *clk = gk20a_clk(base);
544 	struct nvkm_subdev *subdev = &clk->base.subdev;
545 	struct nvkm_device *device = subdev->device;
546 	struct gk20a_pll pll;
547 
548 	switch (src) {
549 	case nv_clk_src_crystal:
550 		return device->crystal;
551 	case nv_clk_src_gpc:
552 		gk20a_pllg_read_mnp(clk, &pll);
553 		return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV;
554 	default:
555 		nvkm_error(subdev, "invalid clock source %d\n", src);
556 		return -EINVAL;
557 	}
558 }
559 
560 int
561 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
562 {
563 	struct gk20a_clk *clk = gk20a_clk(base);
564 
565 	return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
566 					 GK20A_CLK_GPC_MDIV, &clk->pll);
567 }
568 
569 int
570 gk20a_clk_prog(struct nvkm_clk *base)
571 {
572 	struct gk20a_clk *clk = gk20a_clk(base);
573 	int ret;
574 
575 	ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll);
576 	if (ret)
577 		ret = gk20a_pllg_program_mnp(clk, &clk->pll);
578 
579 	return ret;
580 }
581 
582 void
583 gk20a_clk_tidy(struct nvkm_clk *base)
584 {
585 }
586 
587 int
588 gk20a_clk_setup_slide(struct gk20a_clk *clk)
589 {
590 	struct nvkm_subdev *subdev = &clk->base.subdev;
591 	struct nvkm_device *device = subdev->device;
592 	u32 step_a, step_b;
593 
594 	switch (clk->parent_rate) {
595 	case 12000000:
596 	case 12800000:
597 	case 13000000:
598 		step_a = 0x2b;
599 		step_b = 0x0b;
600 		break;
601 	case 19200000:
602 		step_a = 0x12;
603 		step_b = 0x08;
604 		break;
605 	case 38400000:
606 		step_a = 0x04;
607 		step_b = 0x05;
608 		break;
609 	default:
610 		nvkm_error(subdev, "invalid parent clock rate %u KHz",
611 			   clk->parent_rate / KHZ);
612 		return -EINVAL;
613 	}
614 
615 	nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
616 		step_a << GPCPLL_CFG2_PLL_STEPA_SHIFT);
617 	nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
618 		step_b << GPCPLL_CFG3_PLL_STEPB_SHIFT);
619 
620 	return 0;
621 }
622 
623 void
624 gk20a_clk_fini(struct nvkm_clk *base)
625 {
626 	struct nvkm_device *device = base->subdev.device;
627 	struct gk20a_clk *clk = gk20a_clk(base);
628 
629 	/* slide to VCO min */
630 	if (gk20a_pllg_is_enabled(clk)) {
631 		struct gk20a_pll pll;
632 		u32 n_lo;
633 
634 		gk20a_pllg_read_mnp(clk, &pll);
635 		n_lo = gk20a_pllg_n_lo(clk, &pll);
636 		gk20a_pllg_slide(clk, n_lo);
637 	}
638 
639 	gk20a_pllg_disable(clk);
640 
641 	/* set IDDQ */
642 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);
643 }
644 
645 static int
646 gk20a_clk_init(struct nvkm_clk *base)
647 {
648 	struct gk20a_clk *clk = gk20a_clk(base);
649 	struct nvkm_subdev *subdev = &clk->base.subdev;
650 	struct nvkm_device *device = subdev->device;
651 	int ret;
652 
653 	/* get out from IDDQ */
654 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);
655 	nvkm_rd32(device, GPCPLL_CFG);
656 	udelay(5);
657 
658 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK,
659 		  GPC2CLK_OUT_INIT_VAL);
660 
661 	ret = gk20a_clk_setup_slide(clk);
662 	if (ret)
663 		return ret;
664 
665 	/* Start with lowest frequency */
666 	base->func->calc(base, &base->func->pstates[0].base);
667 	ret = base->func->prog(&clk->base);
668 	if (ret) {
669 		nvkm_error(subdev, "cannot initialize clock\n");
670 		return ret;
671 	}
672 
673 	return 0;
674 }
675 
676 static const struct nvkm_clk_func
677 gk20a_clk = {
678 	.init = gk20a_clk_init,
679 	.fini = gk20a_clk_fini,
680 	.read = gk20a_clk_read,
681 	.calc = gk20a_clk_calc,
682 	.prog = gk20a_clk_prog,
683 	.tidy = gk20a_clk_tidy,
684 	.pstates = gk20a_pstates,
685 	.nr_pstates = ARRAY_SIZE(gk20a_pstates),
686 	.domains = {
687 		{ nv_clk_src_crystal, 0xff },
688 		{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
689 		{ nv_clk_src_max }
690 	}
691 };
692 
693 int
694 _gk20a_clk_ctor(struct nvkm_device *device, int index,
695 		const struct nvkm_clk_func *func,
696 		const struct gk20a_clk_pllg_params *params,
697 		struct gk20a_clk *clk)
698 {
699 	struct nvkm_device_tegra *tdev = device->func->tegra(device);
700 	int ret;
701 	int i;
702 
703 	/* Finish initializing the pstates */
704 	for (i = 0; i < func->nr_pstates; i++) {
705 		INIT_LIST_HEAD(&func->pstates[i].list);
706 		func->pstates[i].pstate = i + 1;
707 	}
708 
709 	clk->params = params;
710 	clk->parent_rate = clk_get_rate(tdev->clk);
711 
712 	ret = nvkm_clk_ctor(func, device, index, true, &clk->base);
713 	if (ret)
714 		return ret;
715 
716 	nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n",
717 		   clk->parent_rate / KHZ);
718 
719 	return 0;
720 }
721 
722 int
723 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
724 {
725 	struct gk20a_clk *clk;
726 	int ret;
727 
728 	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
729 	if (!clk)
730 		return -ENOMEM;
731 	*pclk = &clk->base;
732 
733 	ret = _gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params,
734 			      clk);
735 
736 	clk->pl_to_div = pl_to_div;
737 	clk->div_to_pl = div_to_pl;
738 
739 	return ret;
740 }
741