1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #include <subdev/clk.h> 26 #include <subdev/timer.h> 27 28 #ifdef __KERNEL__ 29 #include <nouveau_platform.h> 30 #endif 31 32 #define MHZ (1000 * 1000) 33 34 #define MASK(w) ((1 << w) - 1) 35 36 #define SYS_GPCPLL_CFG_BASE 0x00137000 37 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 38 39 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 40 #define GPCPLL_CFG_ENABLE BIT(0) 41 #define GPCPLL_CFG_IDDQ BIT(1) 42 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 43 #define GPCPLL_CFG_LOCK BIT(17) 44 45 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 46 #define GPCPLL_COEFF_M_SHIFT 0 47 #define GPCPLL_COEFF_M_WIDTH 8 48 #define GPCPLL_COEFF_N_SHIFT 8 49 #define GPCPLL_COEFF_N_WIDTH 8 50 #define GPCPLL_COEFF_P_SHIFT 16 51 #define GPCPLL_COEFF_P_WIDTH 6 52 53 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 54 #define GPCPLL_CFG2_SETUP2_SHIFT 16 55 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 56 57 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 58 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 59 60 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 61 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 62 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 63 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 64 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 65 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 66 67 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 68 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 69 70 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 71 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 72 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 73 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 74 #define GPC2CLK_OUT_VCODIV_WIDTH 6 75 #define GPC2CLK_OUT_VCODIV_SHIFT 8 76 #define GPC2CLK_OUT_VCODIV1 0 77 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 78 GPC2CLK_OUT_VCODIV_SHIFT) 79 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 80 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 81 #define GPC2CLK_OUT_BYPDIV31 0x3c 82 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 83 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 84 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 85 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 86 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 87 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 88 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 89 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 90 91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 94 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 95 96 static const u8 pl_to_div[] = { 97 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 98 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 99 }; 100 101 /* All frequencies in Mhz */ 102 struct gk20a_clk_pllg_params { 103 u32 min_vco, max_vco; 104 u32 min_u, max_u; 105 u32 min_m, max_m; 106 u32 min_n, max_n; 107 u32 min_pl, max_pl; 108 }; 109 110 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 111 .min_vco = 1000, .max_vco = 2064, 112 .min_u = 12, .max_u = 38, 113 .min_m = 1, .max_m = 255, 114 .min_n = 8, .max_n = 255, 115 .min_pl = 1, .max_pl = 32, 116 }; 117 118 struct gk20a_clk { 119 struct nvkm_clk base; 120 const struct gk20a_clk_pllg_params *params; 121 u32 m, n, pl; 122 u32 parent_rate; 123 }; 124 #define to_gk20a_clk(base) container_of(base, struct gk20a_clk, base) 125 126 static void 127 gk20a_pllg_read_mnp(struct gk20a_clk *clk) 128 { 129 struct nvkm_device *device = clk->base.subdev.device; 130 u32 val; 131 132 val = nvkm_rd32(device, GPCPLL_COEFF); 133 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 134 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 135 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 136 } 137 138 static u32 139 gk20a_pllg_calc_rate(struct gk20a_clk *clk) 140 { 141 u32 rate; 142 u32 divider; 143 144 rate = clk->parent_rate * clk->n; 145 divider = clk->m * pl_to_div[clk->pl]; 146 do_div(rate, divider); 147 148 return rate / 2; 149 } 150 151 static int 152 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) 153 { 154 struct nvkm_subdev *subdev = &clk->base.subdev; 155 u32 target_clk_f, ref_clk_f, target_freq; 156 u32 min_vco_f, max_vco_f; 157 u32 low_pl, high_pl, best_pl; 158 u32 target_vco_f, vco_f; 159 u32 best_m, best_n; 160 u32 u_f; 161 u32 m, n, n2; 162 u32 delta, lwv, best_delta = ~0; 163 u32 pl; 164 165 target_clk_f = rate * 2 / MHZ; 166 ref_clk_f = clk->parent_rate / MHZ; 167 168 max_vco_f = clk->params->max_vco; 169 min_vco_f = clk->params->min_vco; 170 best_m = clk->params->max_m; 171 best_n = clk->params->min_n; 172 best_pl = clk->params->min_pl; 173 174 target_vco_f = target_clk_f + target_clk_f / 50; 175 if (max_vco_f < target_vco_f) 176 max_vco_f = target_vco_f; 177 178 /* min_pl <= high_pl <= max_pl */ 179 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 180 high_pl = min(high_pl, clk->params->max_pl); 181 high_pl = max(high_pl, clk->params->min_pl); 182 183 /* min_pl <= low_pl <= max_pl */ 184 low_pl = min_vco_f / target_vco_f; 185 low_pl = min(low_pl, clk->params->max_pl); 186 low_pl = max(low_pl, clk->params->min_pl); 187 188 /* Find Indices of high_pl and low_pl */ 189 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 190 if (pl_to_div[pl] >= low_pl) { 191 low_pl = pl; 192 break; 193 } 194 } 195 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 196 if (pl_to_div[pl] >= high_pl) { 197 high_pl = pl; 198 break; 199 } 200 } 201 202 nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 203 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); 204 205 /* Select lowest possible VCO */ 206 for (pl = low_pl; pl <= high_pl; pl++) { 207 target_vco_f = target_clk_f * pl_to_div[pl]; 208 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 209 u_f = ref_clk_f / m; 210 211 if (u_f < clk->params->min_u) 212 break; 213 if (u_f > clk->params->max_u) 214 continue; 215 216 n = (target_vco_f * m) / ref_clk_f; 217 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 218 219 if (n > clk->params->max_n) 220 break; 221 222 for (; n <= n2; n++) { 223 if (n < clk->params->min_n) 224 continue; 225 if (n > clk->params->max_n) 226 break; 227 228 vco_f = ref_clk_f * n / m; 229 230 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 231 lwv = (vco_f + (pl_to_div[pl] / 2)) 232 / pl_to_div[pl]; 233 delta = abs(lwv - target_clk_f); 234 235 if (delta < best_delta) { 236 best_delta = delta; 237 best_m = m; 238 best_n = n; 239 best_pl = pl; 240 241 if (best_delta == 0) 242 goto found_match; 243 } 244 } 245 } 246 } 247 } 248 249 found_match: 250 WARN_ON(best_delta == ~0); 251 252 if (best_delta != 0) 253 nvkm_debug(subdev, 254 "no best match for target @ %dMHz on gpc_pll", 255 target_clk_f); 256 257 clk->m = best_m; 258 clk->n = best_n; 259 clk->pl = best_pl; 260 261 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; 262 263 nvkm_debug(subdev, 264 "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 265 target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); 266 return 0; 267 } 268 269 static int 270 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 271 { 272 struct nvkm_subdev *subdev = &clk->base.subdev; 273 struct nvkm_device *device = subdev->device; 274 u32 val; 275 int ramp_timeout; 276 277 /* get old coefficients */ 278 val = nvkm_rd32(device, GPCPLL_COEFF); 279 /* do nothing if NDIV is the same */ 280 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 281 return 0; 282 283 /* setup */ 284 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 285 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 286 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 287 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 288 289 /* pll slowdown mode */ 290 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 291 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 292 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 293 294 /* new ndiv ready for ramp */ 295 val = nvkm_rd32(device, GPCPLL_COEFF); 296 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 297 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 298 udelay(1); 299 nvkm_wr32(device, GPCPLL_COEFF, val); 300 301 /* dynamic ramp to new ndiv */ 302 val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 303 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 304 udelay(1); 305 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val); 306 307 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 308 udelay(1); 309 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 310 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 311 break; 312 } 313 314 /* exit slowdown mode */ 315 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 316 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 317 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 318 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 319 320 if (ramp_timeout <= 0) { 321 nvkm_error(subdev, "gpcpll dynamic ramp timeout\n"); 322 return -ETIMEDOUT; 323 } 324 325 return 0; 326 } 327 328 static void 329 _gk20a_pllg_enable(struct gk20a_clk *clk) 330 { 331 struct nvkm_device *device = clk->base.subdev.device; 332 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 333 nvkm_rd32(device, GPCPLL_CFG); 334 } 335 336 static void 337 _gk20a_pllg_disable(struct gk20a_clk *clk) 338 { 339 struct nvkm_device *device = clk->base.subdev.device; 340 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 341 nvkm_rd32(device, GPCPLL_CFG); 342 } 343 344 static int 345 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) 346 { 347 struct nvkm_subdev *subdev = &clk->base.subdev; 348 struct nvkm_device *device = subdev->device; 349 u32 val, cfg; 350 u32 m_old, pl_old, n_lo; 351 352 /* get old coefficients */ 353 val = nvkm_rd32(device, GPCPLL_COEFF); 354 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 355 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 356 357 /* do NDIV slide if there is no change in M and PL */ 358 cfg = nvkm_rd32(device, GPCPLL_CFG); 359 if (allow_slide && clk->m == m_old && clk->pl == pl_old && 360 (cfg & GPCPLL_CFG_ENABLE)) { 361 return gk20a_pllg_slide(clk, clk->n); 362 } 363 364 /* slide down to NDIV_LO */ 365 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, 366 clk->parent_rate / MHZ); 367 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 368 int ret = gk20a_pllg_slide(clk, n_lo); 369 370 if (ret) 371 return ret; 372 } 373 374 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 375 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 376 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 377 378 /* put PLL in bypass before programming it */ 379 val = nvkm_rd32(device, SEL_VCO); 380 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 381 udelay(2); 382 nvkm_wr32(device, SEL_VCO, val); 383 384 /* get out from IDDQ */ 385 val = nvkm_rd32(device, GPCPLL_CFG); 386 if (val & GPCPLL_CFG_IDDQ) { 387 val &= ~GPCPLL_CFG_IDDQ; 388 nvkm_wr32(device, GPCPLL_CFG, val); 389 nvkm_rd32(device, GPCPLL_CFG); 390 udelay(2); 391 } 392 393 _gk20a_pllg_disable(clk); 394 395 nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, 396 clk->m, clk->n, clk->pl); 397 398 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, 399 clk->parent_rate / MHZ); 400 val = clk->m << GPCPLL_COEFF_M_SHIFT; 401 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; 402 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; 403 nvkm_wr32(device, GPCPLL_COEFF, val); 404 405 _gk20a_pllg_enable(clk); 406 407 val = nvkm_rd32(device, GPCPLL_CFG); 408 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 409 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 410 nvkm_wr32(device, GPCPLL_CFG, val); 411 } 412 413 if (nvkm_usec(device, 300, 414 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK) 415 break; 416 ) < 0) 417 return -ETIMEDOUT; 418 419 /* switch to VCO mode */ 420 nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 421 422 /* restore out divider 1:1 */ 423 val = nvkm_rd32(device, GPC2CLK_OUT); 424 val &= ~GPC2CLK_OUT_VCODIV_MASK; 425 udelay(2); 426 nvkm_wr32(device, GPC2CLK_OUT, val); 427 428 /* slide up to new NDIV */ 429 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; 430 } 431 432 static int 433 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 434 { 435 int err; 436 437 err = _gk20a_pllg_program_mnp(clk, true); 438 if (err) 439 err = _gk20a_pllg_program_mnp(clk, false); 440 441 return err; 442 } 443 444 static void 445 gk20a_pllg_disable(struct gk20a_clk *clk) 446 { 447 struct nvkm_device *device = clk->base.subdev.device; 448 u32 val; 449 450 /* slide to VCO min */ 451 val = nvkm_rd32(device, GPCPLL_CFG); 452 if (val & GPCPLL_CFG_ENABLE) { 453 u32 coeff, m, n_lo; 454 455 coeff = nvkm_rd32(device, GPCPLL_COEFF); 456 m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 457 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, 458 clk->parent_rate / MHZ); 459 gk20a_pllg_slide(clk, n_lo); 460 } 461 462 /* put PLL in bypass before disabling it */ 463 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 464 465 _gk20a_pllg_disable(clk); 466 } 467 468 #define GK20A_CLK_GPC_MDIV 1000 469 470 static struct nvkm_domain 471 gk20a_domains[] = { 472 { nv_clk_src_crystal, 0xff }, 473 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 474 { nv_clk_src_max } 475 }; 476 477 static struct nvkm_pstate 478 gk20a_pstates[] = { 479 { 480 .base = { 481 .domain[nv_clk_src_gpc] = 72000, 482 .voltage = 0, 483 }, 484 }, 485 { 486 .base = { 487 .domain[nv_clk_src_gpc] = 108000, 488 .voltage = 1, 489 }, 490 }, 491 { 492 .base = { 493 .domain[nv_clk_src_gpc] = 180000, 494 .voltage = 2, 495 }, 496 }, 497 { 498 .base = { 499 .domain[nv_clk_src_gpc] = 252000, 500 .voltage = 3, 501 }, 502 }, 503 { 504 .base = { 505 .domain[nv_clk_src_gpc] = 324000, 506 .voltage = 4, 507 }, 508 }, 509 { 510 .base = { 511 .domain[nv_clk_src_gpc] = 396000, 512 .voltage = 5, 513 }, 514 }, 515 { 516 .base = { 517 .domain[nv_clk_src_gpc] = 468000, 518 .voltage = 6, 519 }, 520 }, 521 { 522 .base = { 523 .domain[nv_clk_src_gpc] = 540000, 524 .voltage = 7, 525 }, 526 }, 527 { 528 .base = { 529 .domain[nv_clk_src_gpc] = 612000, 530 .voltage = 8, 531 }, 532 }, 533 { 534 .base = { 535 .domain[nv_clk_src_gpc] = 648000, 536 .voltage = 9, 537 }, 538 }, 539 { 540 .base = { 541 .domain[nv_clk_src_gpc] = 684000, 542 .voltage = 10, 543 }, 544 }, 545 { 546 .base = { 547 .domain[nv_clk_src_gpc] = 708000, 548 .voltage = 11, 549 }, 550 }, 551 { 552 .base = { 553 .domain[nv_clk_src_gpc] = 756000, 554 .voltage = 12, 555 }, 556 }, 557 { 558 .base = { 559 .domain[nv_clk_src_gpc] = 804000, 560 .voltage = 13, 561 }, 562 }, 563 { 564 .base = { 565 .domain[nv_clk_src_gpc] = 852000, 566 .voltage = 14, 567 }, 568 }, 569 }; 570 571 static int 572 gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 573 { 574 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 575 struct nvkm_subdev *subdev = &clk->base.subdev; 576 struct nvkm_device *device = subdev->device; 577 578 switch (src) { 579 case nv_clk_src_crystal: 580 return device->crystal; 581 case nv_clk_src_gpc: 582 gk20a_pllg_read_mnp(clk); 583 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; 584 default: 585 nvkm_error(subdev, "invalid clock source %d\n", src); 586 return -EINVAL; 587 } 588 } 589 590 static int 591 gk20a_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 592 { 593 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 594 595 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 596 GK20A_CLK_GPC_MDIV); 597 } 598 599 static int 600 gk20a_clk_prog(struct nvkm_clk *obj) 601 { 602 struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); 603 604 return gk20a_pllg_program_mnp(clk); 605 } 606 607 static void 608 gk20a_clk_tidy(struct nvkm_clk *obj) 609 { 610 } 611 612 static int 613 gk20a_clk_fini(struct nvkm_object *object, bool suspend) 614 { 615 struct gk20a_clk *clk = (void *)object; 616 int ret; 617 618 ret = nvkm_clk_fini(&clk->base, false); 619 620 gk20a_pllg_disable(clk); 621 622 return ret; 623 } 624 625 static int 626 gk20a_clk_init(struct nvkm_object *object) 627 { 628 struct gk20a_clk *clk = (void *)object; 629 struct nvkm_subdev *subdev = &clk->base.subdev; 630 struct nvkm_device *device = subdev->device; 631 int ret; 632 633 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 634 635 ret = nvkm_clk_init(&clk->base); 636 if (ret) 637 return ret; 638 639 ret = gk20a_clk_prog(&clk->base); 640 if (ret) { 641 nvkm_error(subdev, "cannot initialize clock\n"); 642 return ret; 643 } 644 645 return 0; 646 } 647 648 static int 649 gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 650 struct nvkm_oclass *oclass, void *data, u32 size, 651 struct nvkm_object **pobject) 652 { 653 struct gk20a_clk *clk; 654 struct nouveau_platform_device *plat; 655 int ret; 656 int i; 657 658 /* Finish initializing the pstates */ 659 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { 660 INIT_LIST_HEAD(&gk20a_pstates[i].list); 661 gk20a_pstates[i].pstate = i + 1; 662 } 663 664 ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains, 665 gk20a_pstates, ARRAY_SIZE(gk20a_pstates), 666 true, &clk); 667 *pobject = nv_object(clk); 668 if (ret) 669 return ret; 670 671 clk->params = &gk20a_pllg_params; 672 673 plat = nv_device_to_platform(nv_device(parent)); 674 clk->parent_rate = clk_get_rate(plat->gpu->clk); 675 nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", 676 clk->parent_rate / MHZ); 677 678 clk->base.read = gk20a_clk_read; 679 clk->base.calc = gk20a_clk_calc; 680 clk->base.prog = gk20a_clk_prog; 681 clk->base.tidy = gk20a_clk_tidy; 682 return 0; 683 } 684 685 struct nvkm_oclass 686 gk20a_clk_oclass = { 687 .handle = NV_SUBDEV(CLK, 0xea), 688 .ofuncs = &(struct nvkm_ofuncs) { 689 .ctor = gk20a_clk_ctor, 690 .dtor = _nvkm_subdev_dtor, 691 .init = gk20a_clk_init, 692 .fini = gk20a_clk_fini, 693 }, 694 }; 695