1 /* 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) 26 #include "priv.h" 27 28 #include <core/tegra.h> 29 #include <subdev/timer.h> 30 31 #define KHZ (1000) 32 #define MHZ (KHZ * 1000) 33 34 #define MASK(w) ((1 << w) - 1) 35 36 #define SYS_GPCPLL_CFG_BASE 0x00137000 37 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 38 39 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 40 #define GPCPLL_CFG_ENABLE BIT(0) 41 #define GPCPLL_CFG_IDDQ BIT(1) 42 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 43 #define GPCPLL_CFG_LOCK BIT(17) 44 45 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 46 #define GPCPLL_COEFF_M_SHIFT 0 47 #define GPCPLL_COEFF_M_WIDTH 8 48 #define GPCPLL_COEFF_N_SHIFT 8 49 #define GPCPLL_COEFF_N_WIDTH 8 50 #define GPCPLL_COEFF_P_SHIFT 16 51 #define GPCPLL_COEFF_P_WIDTH 6 52 53 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 54 #define GPCPLL_CFG2_SETUP2_SHIFT 16 55 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 56 57 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 58 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 59 60 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 61 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 62 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 63 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 64 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 65 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 66 67 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 68 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 69 70 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 71 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 72 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 73 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 74 #define GPC2CLK_OUT_VCODIV_WIDTH 6 75 #define GPC2CLK_OUT_VCODIV_SHIFT 8 76 #define GPC2CLK_OUT_VCODIV1 0 77 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 78 GPC2CLK_OUT_VCODIV_SHIFT) 79 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 80 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 81 #define GPC2CLK_OUT_BYPDIV31 0x3c 82 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 83 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 84 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 85 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 86 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 87 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 88 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 89 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 90 91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 94 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 95 96 static const u8 pl_to_div[] = { 97 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 98 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 99 }; 100 101 /* All frequencies in Khz */ 102 struct gk20a_clk_pllg_params { 103 u32 min_vco, max_vco; 104 u32 min_u, max_u; 105 u32 min_m, max_m; 106 u32 min_n, max_n; 107 u32 min_pl, max_pl; 108 }; 109 110 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 111 .min_vco = 1000000, .max_vco = 2064000, 112 .min_u = 12000, .max_u = 38000, 113 .min_m = 1, .max_m = 255, 114 .min_n = 8, .max_n = 255, 115 .min_pl = 1, .max_pl = 32, 116 }; 117 118 struct gk20a_clk { 119 struct nvkm_clk base; 120 const struct gk20a_clk_pllg_params *params; 121 u32 m, n, pl; 122 u32 parent_rate; 123 }; 124 125 static void 126 gk20a_pllg_read_mnp(struct gk20a_clk *clk) 127 { 128 struct nvkm_device *device = clk->base.subdev.device; 129 u32 val; 130 131 val = nvkm_rd32(device, GPCPLL_COEFF); 132 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 133 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 134 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 135 } 136 137 static u32 138 gk20a_pllg_calc_rate(struct gk20a_clk *clk) 139 { 140 u32 rate; 141 u32 divider; 142 143 rate = clk->parent_rate * clk->n; 144 divider = clk->m * pl_to_div[clk->pl]; 145 146 return rate / divider / 2; 147 } 148 149 static int 150 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) 151 { 152 struct nvkm_subdev *subdev = &clk->base.subdev; 153 u32 target_clk_f, ref_clk_f, target_freq; 154 u32 min_vco_f, max_vco_f; 155 u32 low_pl, high_pl, best_pl; 156 u32 target_vco_f; 157 u32 best_m, best_n; 158 u32 best_delta = ~0; 159 u32 pl; 160 161 target_clk_f = rate * 2 / KHZ; 162 ref_clk_f = clk->parent_rate / KHZ; 163 164 max_vco_f = clk->params->max_vco; 165 min_vco_f = clk->params->min_vco; 166 best_m = clk->params->max_m; 167 best_n = clk->params->min_n; 168 best_pl = clk->params->min_pl; 169 170 target_vco_f = target_clk_f + target_clk_f / 50; 171 if (max_vco_f < target_vco_f) 172 max_vco_f = target_vco_f; 173 174 /* min_pl <= high_pl <= max_pl */ 175 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 176 high_pl = min(high_pl, clk->params->max_pl); 177 high_pl = max(high_pl, clk->params->min_pl); 178 179 /* min_pl <= low_pl <= max_pl */ 180 low_pl = min_vco_f / target_vco_f; 181 low_pl = min(low_pl, clk->params->max_pl); 182 low_pl = max(low_pl, clk->params->min_pl); 183 184 /* Find Indices of high_pl and low_pl */ 185 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 186 if (pl_to_div[pl] >= low_pl) { 187 low_pl = pl; 188 break; 189 } 190 } 191 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 192 if (pl_to_div[pl] >= high_pl) { 193 high_pl = pl; 194 break; 195 } 196 } 197 198 nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 199 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); 200 201 /* Select lowest possible VCO */ 202 for (pl = low_pl; pl <= high_pl; pl++) { 203 u32 m, n, n2; 204 205 target_vco_f = target_clk_f * pl_to_div[pl]; 206 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 207 u32 u_f, vco_f; 208 209 u_f = ref_clk_f / m; 210 211 if (u_f < clk->params->min_u) 212 break; 213 if (u_f > clk->params->max_u) 214 continue; 215 216 n = (target_vco_f * m) / ref_clk_f; 217 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 218 219 if (n > clk->params->max_n) 220 break; 221 222 for (; n <= n2; n++) { 223 if (n < clk->params->min_n) 224 continue; 225 if (n > clk->params->max_n) 226 break; 227 228 vco_f = ref_clk_f * n / m; 229 230 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 231 u32 delta, lwv; 232 233 lwv = (vco_f + (pl_to_div[pl] / 2)) 234 / pl_to_div[pl]; 235 delta = abs(lwv - target_clk_f); 236 237 if (delta < best_delta) { 238 best_delta = delta; 239 best_m = m; 240 best_n = n; 241 best_pl = pl; 242 243 if (best_delta == 0) 244 goto found_match; 245 } 246 } 247 } 248 } 249 } 250 251 found_match: 252 WARN_ON(best_delta == ~0); 253 254 if (best_delta != 0) 255 nvkm_debug(subdev, 256 "no best match for target @ %dMHz on gpc_pll", 257 target_clk_f / KHZ); 258 259 clk->m = best_m; 260 clk->n = best_n; 261 clk->pl = best_pl; 262 263 target_freq = gk20a_pllg_calc_rate(clk); 264 265 nvkm_debug(subdev, 266 "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 267 target_freq / MHZ, clk->m, clk->n, clk->pl, 268 pl_to_div[clk->pl]); 269 return 0; 270 } 271 272 static int 273 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 274 { 275 struct nvkm_subdev *subdev = &clk->base.subdev; 276 struct nvkm_device *device = subdev->device; 277 u32 val; 278 int ramp_timeout; 279 280 /* get old coefficients */ 281 val = nvkm_rd32(device, GPCPLL_COEFF); 282 /* do nothing if NDIV is the same */ 283 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 284 return 0; 285 286 /* setup */ 287 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 288 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 289 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 290 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 291 292 /* pll slowdown mode */ 293 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 294 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 295 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 296 297 /* new ndiv ready for ramp */ 298 val = nvkm_rd32(device, GPCPLL_COEFF); 299 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 300 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 301 udelay(1); 302 nvkm_wr32(device, GPCPLL_COEFF, val); 303 304 /* dynamic ramp to new ndiv */ 305 val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 306 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 307 udelay(1); 308 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val); 309 310 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 311 udelay(1); 312 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 313 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 314 break; 315 } 316 317 /* exit slowdown mode */ 318 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 319 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 320 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 321 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 322 323 if (ramp_timeout <= 0) { 324 nvkm_error(subdev, "gpcpll dynamic ramp timeout\n"); 325 return -ETIMEDOUT; 326 } 327 328 return 0; 329 } 330 331 static void 332 gk20a_pllg_enable(struct gk20a_clk *clk) 333 { 334 struct nvkm_device *device = clk->base.subdev.device; 335 336 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 337 nvkm_rd32(device, GPCPLL_CFG); 338 } 339 340 static void 341 gk20a_pllg_disable(struct gk20a_clk *clk) 342 { 343 struct nvkm_device *device = clk->base.subdev.device; 344 345 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 346 nvkm_rd32(device, GPCPLL_CFG); 347 } 348 349 static int 350 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) 351 { 352 struct nvkm_subdev *subdev = &clk->base.subdev; 353 struct nvkm_device *device = subdev->device; 354 u32 val, cfg; 355 u32 m_old, pl_old, n_lo; 356 357 /* get old coefficients */ 358 val = nvkm_rd32(device, GPCPLL_COEFF); 359 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 360 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 361 362 /* do NDIV slide if there is no change in M and PL */ 363 cfg = nvkm_rd32(device, GPCPLL_CFG); 364 if (allow_slide && clk->m == m_old && clk->pl == pl_old && 365 (cfg & GPCPLL_CFG_ENABLE)) { 366 return gk20a_pllg_slide(clk, clk->n); 367 } 368 369 /* slide down to NDIV_LO */ 370 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, 371 clk->parent_rate / KHZ); 372 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 373 int ret = gk20a_pllg_slide(clk, n_lo); 374 375 if (ret) 376 return ret; 377 } 378 379 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 380 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 381 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 382 383 /* put PLL in bypass before programming it */ 384 val = nvkm_rd32(device, SEL_VCO); 385 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 386 udelay(2); 387 nvkm_wr32(device, SEL_VCO, val); 388 389 /* get out from IDDQ */ 390 val = nvkm_rd32(device, GPCPLL_CFG); 391 if (val & GPCPLL_CFG_IDDQ) { 392 val &= ~GPCPLL_CFG_IDDQ; 393 nvkm_wr32(device, GPCPLL_CFG, val); 394 nvkm_rd32(device, GPCPLL_CFG); 395 udelay(2); 396 } 397 398 gk20a_pllg_disable(clk); 399 400 nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, 401 clk->m, clk->n, clk->pl); 402 403 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, 404 clk->parent_rate / KHZ); 405 val = clk->m << GPCPLL_COEFF_M_SHIFT; 406 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; 407 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; 408 nvkm_wr32(device, GPCPLL_COEFF, val); 409 410 gk20a_pllg_enable(clk); 411 412 val = nvkm_rd32(device, GPCPLL_CFG); 413 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 414 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 415 nvkm_wr32(device, GPCPLL_CFG, val); 416 } 417 418 if (nvkm_usec(device, 300, 419 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK) 420 break; 421 ) < 0) 422 return -ETIMEDOUT; 423 424 /* switch to VCO mode */ 425 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 426 BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 427 428 /* restore out divider 1:1 */ 429 val = nvkm_rd32(device, GPC2CLK_OUT); 430 val &= ~GPC2CLK_OUT_VCODIV_MASK; 431 udelay(2); 432 nvkm_wr32(device, GPC2CLK_OUT, val); 433 434 /* slide up to new NDIV */ 435 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; 436 } 437 438 static int 439 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 440 { 441 int err; 442 443 err = _gk20a_pllg_program_mnp(clk, true); 444 if (err) 445 err = _gk20a_pllg_program_mnp(clk, false); 446 447 return err; 448 } 449 450 #define GK20A_CLK_GPC_MDIV 1000 451 452 static struct nvkm_pstate 453 gk20a_pstates[] = { 454 { 455 .base = { 456 .domain[nv_clk_src_gpc] = 72000, 457 .voltage = 0, 458 }, 459 }, 460 { 461 .base = { 462 .domain[nv_clk_src_gpc] = 108000, 463 .voltage = 1, 464 }, 465 }, 466 { 467 .base = { 468 .domain[nv_clk_src_gpc] = 180000, 469 .voltage = 2, 470 }, 471 }, 472 { 473 .base = { 474 .domain[nv_clk_src_gpc] = 252000, 475 .voltage = 3, 476 }, 477 }, 478 { 479 .base = { 480 .domain[nv_clk_src_gpc] = 324000, 481 .voltage = 4, 482 }, 483 }, 484 { 485 .base = { 486 .domain[nv_clk_src_gpc] = 396000, 487 .voltage = 5, 488 }, 489 }, 490 { 491 .base = { 492 .domain[nv_clk_src_gpc] = 468000, 493 .voltage = 6, 494 }, 495 }, 496 { 497 .base = { 498 .domain[nv_clk_src_gpc] = 540000, 499 .voltage = 7, 500 }, 501 }, 502 { 503 .base = { 504 .domain[nv_clk_src_gpc] = 612000, 505 .voltage = 8, 506 }, 507 }, 508 { 509 .base = { 510 .domain[nv_clk_src_gpc] = 648000, 511 .voltage = 9, 512 }, 513 }, 514 { 515 .base = { 516 .domain[nv_clk_src_gpc] = 684000, 517 .voltage = 10, 518 }, 519 }, 520 { 521 .base = { 522 .domain[nv_clk_src_gpc] = 708000, 523 .voltage = 11, 524 }, 525 }, 526 { 527 .base = { 528 .domain[nv_clk_src_gpc] = 756000, 529 .voltage = 12, 530 }, 531 }, 532 { 533 .base = { 534 .domain[nv_clk_src_gpc] = 804000, 535 .voltage = 13, 536 }, 537 }, 538 { 539 .base = { 540 .domain[nv_clk_src_gpc] = 852000, 541 .voltage = 14, 542 }, 543 }, 544 }; 545 546 static int 547 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) 548 { 549 struct gk20a_clk *clk = gk20a_clk(base); 550 struct nvkm_subdev *subdev = &clk->base.subdev; 551 struct nvkm_device *device = subdev->device; 552 553 switch (src) { 554 case nv_clk_src_crystal: 555 return device->crystal; 556 case nv_clk_src_gpc: 557 gk20a_pllg_read_mnp(clk); 558 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; 559 default: 560 nvkm_error(subdev, "invalid clock source %d\n", src); 561 return -EINVAL; 562 } 563 } 564 565 static int 566 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) 567 { 568 struct gk20a_clk *clk = gk20a_clk(base); 569 570 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 571 GK20A_CLK_GPC_MDIV); 572 } 573 574 static int 575 gk20a_clk_prog(struct nvkm_clk *base) 576 { 577 struct gk20a_clk *clk = gk20a_clk(base); 578 579 return gk20a_pllg_program_mnp(clk); 580 } 581 582 static void 583 gk20a_clk_tidy(struct nvkm_clk *base) 584 { 585 } 586 587 static void 588 gk20a_clk_fini(struct nvkm_clk *base) 589 { 590 struct nvkm_device *device = base->subdev.device; 591 struct gk20a_clk *clk = gk20a_clk(base); 592 u32 val; 593 594 /* slide to VCO min */ 595 val = nvkm_rd32(device, GPCPLL_CFG); 596 if (val & GPCPLL_CFG_ENABLE) { 597 u32 coef, m, n_lo; 598 599 coef = nvkm_rd32(device, GPCPLL_COEFF); 600 m = (coef >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 601 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, 602 clk->parent_rate / KHZ); 603 gk20a_pllg_slide(clk, n_lo); 604 } 605 606 /* put PLL in bypass before disabling it */ 607 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 608 609 gk20a_pllg_disable(clk); 610 } 611 612 static int 613 gk20a_clk_init(struct nvkm_clk *base) 614 { 615 struct gk20a_clk *clk = gk20a_clk(base); 616 struct nvkm_subdev *subdev = &clk->base.subdev; 617 struct nvkm_device *device = subdev->device; 618 int ret; 619 620 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 621 622 ret = gk20a_clk_prog(&clk->base); 623 if (ret) { 624 nvkm_error(subdev, "cannot initialize clock\n"); 625 return ret; 626 } 627 628 return 0; 629 } 630 631 static const struct nvkm_clk_func 632 gk20a_clk = { 633 .init = gk20a_clk_init, 634 .fini = gk20a_clk_fini, 635 .read = gk20a_clk_read, 636 .calc = gk20a_clk_calc, 637 .prog = gk20a_clk_prog, 638 .tidy = gk20a_clk_tidy, 639 .pstates = gk20a_pstates, 640 .nr_pstates = ARRAY_SIZE(gk20a_pstates), 641 .domains = { 642 { nv_clk_src_crystal, 0xff }, 643 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 644 { nv_clk_src_max } 645 } 646 }; 647 648 int 649 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) 650 { 651 struct nvkm_device_tegra *tdev = device->func->tegra(device); 652 struct gk20a_clk *clk; 653 int ret, i; 654 655 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) 656 return -ENOMEM; 657 *pclk = &clk->base; 658 659 /* Finish initializing the pstates */ 660 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { 661 INIT_LIST_HEAD(&gk20a_pstates[i].list); 662 gk20a_pstates[i].pstate = i + 1; 663 } 664 665 clk->params = &gk20a_pllg_params; 666 clk->parent_rate = clk_get_rate(tdev->clk); 667 668 ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); 669 nvkm_info(&clk->base.subdev, "parent clock rate: %d Khz\n", 670 clk->parent_rate / KHZ); 671 return ret; 672 } 673