1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) 26 #include "priv.h" 27 28 #include <subdev/timer.h> 29 30 #ifdef __KERNEL__ 31 #include <nouveau_platform.h> 32 #endif 33 34 #define MHZ (1000 * 1000) 35 36 #define MASK(w) ((1 << w) - 1) 37 38 #define SYS_GPCPLL_CFG_BASE 0x00137000 39 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 40 41 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 42 #define GPCPLL_CFG_ENABLE BIT(0) 43 #define GPCPLL_CFG_IDDQ BIT(1) 44 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 45 #define GPCPLL_CFG_LOCK BIT(17) 46 47 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 48 #define GPCPLL_COEFF_M_SHIFT 0 49 #define GPCPLL_COEFF_M_WIDTH 8 50 #define GPCPLL_COEFF_N_SHIFT 8 51 #define GPCPLL_COEFF_N_WIDTH 8 52 #define GPCPLL_COEFF_P_SHIFT 16 53 #define GPCPLL_COEFF_P_WIDTH 6 54 55 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 56 #define GPCPLL_CFG2_SETUP2_SHIFT 16 57 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 58 59 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 60 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 61 62 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 63 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 64 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 65 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 66 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 67 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 68 69 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 70 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 71 72 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 73 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 74 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 75 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 76 #define GPC2CLK_OUT_VCODIV_WIDTH 6 77 #define GPC2CLK_OUT_VCODIV_SHIFT 8 78 #define GPC2CLK_OUT_VCODIV1 0 79 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 80 GPC2CLK_OUT_VCODIV_SHIFT) 81 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 82 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 83 #define GPC2CLK_OUT_BYPDIV31 0x3c 84 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 85 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 86 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 87 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 88 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 89 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 90 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 91 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 92 93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 94 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 95 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 96 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 97 98 static const u8 pl_to_div[] = { 99 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 100 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 101 }; 102 103 /* All frequencies in Mhz */ 104 struct gk20a_clk_pllg_params { 105 u32 min_vco, max_vco; 106 u32 min_u, max_u; 107 u32 min_m, max_m; 108 u32 min_n, max_n; 109 u32 min_pl, max_pl; 110 }; 111 112 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 113 .min_vco = 1000, .max_vco = 2064, 114 .min_u = 12, .max_u = 38, 115 .min_m = 1, .max_m = 255, 116 .min_n = 8, .max_n = 255, 117 .min_pl = 1, .max_pl = 32, 118 }; 119 120 struct gk20a_clk { 121 struct nvkm_clk base; 122 const struct gk20a_clk_pllg_params *params; 123 u32 m, n, pl; 124 u32 parent_rate; 125 }; 126 127 static void 128 gk20a_pllg_read_mnp(struct gk20a_clk *clk) 129 { 130 struct nvkm_device *device = clk->base.subdev.device; 131 u32 val; 132 133 val = nvkm_rd32(device, GPCPLL_COEFF); 134 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 135 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 136 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 137 } 138 139 static u32 140 gk20a_pllg_calc_rate(struct gk20a_clk *clk) 141 { 142 u32 rate; 143 u32 divider; 144 145 rate = clk->parent_rate * clk->n; 146 divider = clk->m * pl_to_div[clk->pl]; 147 do_div(rate, divider); 148 149 return rate / 2; 150 } 151 152 static int 153 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) 154 { 155 struct nvkm_subdev *subdev = &clk->base.subdev; 156 u32 target_clk_f, ref_clk_f, target_freq; 157 u32 min_vco_f, max_vco_f; 158 u32 low_pl, high_pl, best_pl; 159 u32 target_vco_f, vco_f; 160 u32 best_m, best_n; 161 u32 u_f; 162 u32 m, n, n2; 163 u32 delta, lwv, best_delta = ~0; 164 u32 pl; 165 166 target_clk_f = rate * 2 / MHZ; 167 ref_clk_f = clk->parent_rate / MHZ; 168 169 max_vco_f = clk->params->max_vco; 170 min_vco_f = clk->params->min_vco; 171 best_m = clk->params->max_m; 172 best_n = clk->params->min_n; 173 best_pl = clk->params->min_pl; 174 175 target_vco_f = target_clk_f + target_clk_f / 50; 176 if (max_vco_f < target_vco_f) 177 max_vco_f = target_vco_f; 178 179 /* min_pl <= high_pl <= max_pl */ 180 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 181 high_pl = min(high_pl, clk->params->max_pl); 182 high_pl = max(high_pl, clk->params->min_pl); 183 184 /* min_pl <= low_pl <= max_pl */ 185 low_pl = min_vco_f / target_vco_f; 186 low_pl = min(low_pl, clk->params->max_pl); 187 low_pl = max(low_pl, clk->params->min_pl); 188 189 /* Find Indices of high_pl and low_pl */ 190 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 191 if (pl_to_div[pl] >= low_pl) { 192 low_pl = pl; 193 break; 194 } 195 } 196 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { 197 if (pl_to_div[pl] >= high_pl) { 198 high_pl = pl; 199 break; 200 } 201 } 202 203 nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 204 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); 205 206 /* Select lowest possible VCO */ 207 for (pl = low_pl; pl <= high_pl; pl++) { 208 target_vco_f = target_clk_f * pl_to_div[pl]; 209 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 210 u_f = ref_clk_f / m; 211 212 if (u_f < clk->params->min_u) 213 break; 214 if (u_f > clk->params->max_u) 215 continue; 216 217 n = (target_vco_f * m) / ref_clk_f; 218 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 219 220 if (n > clk->params->max_n) 221 break; 222 223 for (; n <= n2; n++) { 224 if (n < clk->params->min_n) 225 continue; 226 if (n > clk->params->max_n) 227 break; 228 229 vco_f = ref_clk_f * n / m; 230 231 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 232 lwv = (vco_f + (pl_to_div[pl] / 2)) 233 / pl_to_div[pl]; 234 delta = abs(lwv - target_clk_f); 235 236 if (delta < best_delta) { 237 best_delta = delta; 238 best_m = m; 239 best_n = n; 240 best_pl = pl; 241 242 if (best_delta == 0) 243 goto found_match; 244 } 245 } 246 } 247 } 248 } 249 250 found_match: 251 WARN_ON(best_delta == ~0); 252 253 if (best_delta != 0) 254 nvkm_debug(subdev, 255 "no best match for target @ %dMHz on gpc_pll", 256 target_clk_f); 257 258 clk->m = best_m; 259 clk->n = best_n; 260 clk->pl = best_pl; 261 262 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; 263 264 nvkm_debug(subdev, 265 "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 266 target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); 267 return 0; 268 } 269 270 static int 271 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 272 { 273 struct nvkm_subdev *subdev = &clk->base.subdev; 274 struct nvkm_device *device = subdev->device; 275 u32 val; 276 int ramp_timeout; 277 278 /* get old coefficients */ 279 val = nvkm_rd32(device, GPCPLL_COEFF); 280 /* do nothing if NDIV is the same */ 281 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 282 return 0; 283 284 /* setup */ 285 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 286 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 287 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 288 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 289 290 /* pll slowdown mode */ 291 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 292 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 293 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 294 295 /* new ndiv ready for ramp */ 296 val = nvkm_rd32(device, GPCPLL_COEFF); 297 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 298 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 299 udelay(1); 300 nvkm_wr32(device, GPCPLL_COEFF, val); 301 302 /* dynamic ramp to new ndiv */ 303 val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 304 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 305 udelay(1); 306 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val); 307 308 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 309 udelay(1); 310 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 311 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 312 break; 313 } 314 315 /* exit slowdown mode */ 316 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 317 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 318 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 319 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 320 321 if (ramp_timeout <= 0) { 322 nvkm_error(subdev, "gpcpll dynamic ramp timeout\n"); 323 return -ETIMEDOUT; 324 } 325 326 return 0; 327 } 328 329 static void 330 _gk20a_pllg_enable(struct gk20a_clk *clk) 331 { 332 struct nvkm_device *device = clk->base.subdev.device; 333 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 334 nvkm_rd32(device, GPCPLL_CFG); 335 } 336 337 static void 338 _gk20a_pllg_disable(struct gk20a_clk *clk) 339 { 340 struct nvkm_device *device = clk->base.subdev.device; 341 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 342 nvkm_rd32(device, GPCPLL_CFG); 343 } 344 345 static int 346 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) 347 { 348 struct nvkm_subdev *subdev = &clk->base.subdev; 349 struct nvkm_device *device = subdev->device; 350 u32 val, cfg; 351 u32 m_old, pl_old, n_lo; 352 353 /* get old coefficients */ 354 val = nvkm_rd32(device, GPCPLL_COEFF); 355 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 356 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 357 358 /* do NDIV slide if there is no change in M and PL */ 359 cfg = nvkm_rd32(device, GPCPLL_CFG); 360 if (allow_slide && clk->m == m_old && clk->pl == pl_old && 361 (cfg & GPCPLL_CFG_ENABLE)) { 362 return gk20a_pllg_slide(clk, clk->n); 363 } 364 365 /* slide down to NDIV_LO */ 366 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, 367 clk->parent_rate / MHZ); 368 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 369 int ret = gk20a_pllg_slide(clk, n_lo); 370 371 if (ret) 372 return ret; 373 } 374 375 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 376 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 377 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 378 379 /* put PLL in bypass before programming it */ 380 val = nvkm_rd32(device, SEL_VCO); 381 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 382 udelay(2); 383 nvkm_wr32(device, SEL_VCO, val); 384 385 /* get out from IDDQ */ 386 val = nvkm_rd32(device, GPCPLL_CFG); 387 if (val & GPCPLL_CFG_IDDQ) { 388 val &= ~GPCPLL_CFG_IDDQ; 389 nvkm_wr32(device, GPCPLL_CFG, val); 390 nvkm_rd32(device, GPCPLL_CFG); 391 udelay(2); 392 } 393 394 _gk20a_pllg_disable(clk); 395 396 nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, 397 clk->m, clk->n, clk->pl); 398 399 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, 400 clk->parent_rate / MHZ); 401 val = clk->m << GPCPLL_COEFF_M_SHIFT; 402 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; 403 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; 404 nvkm_wr32(device, GPCPLL_COEFF, val); 405 406 _gk20a_pllg_enable(clk); 407 408 val = nvkm_rd32(device, GPCPLL_CFG); 409 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 410 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 411 nvkm_wr32(device, GPCPLL_CFG, val); 412 } 413 414 if (nvkm_usec(device, 300, 415 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK) 416 break; 417 ) < 0) 418 return -ETIMEDOUT; 419 420 /* switch to VCO mode */ 421 nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 422 423 /* restore out divider 1:1 */ 424 val = nvkm_rd32(device, GPC2CLK_OUT); 425 val &= ~GPC2CLK_OUT_VCODIV_MASK; 426 udelay(2); 427 nvkm_wr32(device, GPC2CLK_OUT, val); 428 429 /* slide up to new NDIV */ 430 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; 431 } 432 433 static int 434 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 435 { 436 int err; 437 438 err = _gk20a_pllg_program_mnp(clk, true); 439 if (err) 440 err = _gk20a_pllg_program_mnp(clk, false); 441 442 return err; 443 } 444 445 static void 446 gk20a_pllg_disable(struct gk20a_clk *clk) 447 { 448 struct nvkm_device *device = clk->base.subdev.device; 449 u32 val; 450 451 /* slide to VCO min */ 452 val = nvkm_rd32(device, GPCPLL_CFG); 453 if (val & GPCPLL_CFG_ENABLE) { 454 u32 coeff, m, n_lo; 455 456 coeff = nvkm_rd32(device, GPCPLL_COEFF); 457 m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 458 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, 459 clk->parent_rate / MHZ); 460 gk20a_pllg_slide(clk, n_lo); 461 } 462 463 /* put PLL in bypass before disabling it */ 464 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 465 466 _gk20a_pllg_disable(clk); 467 } 468 469 #define GK20A_CLK_GPC_MDIV 1000 470 471 static struct nvkm_pstate 472 gk20a_pstates[] = { 473 { 474 .base = { 475 .domain[nv_clk_src_gpc] = 72000, 476 .voltage = 0, 477 }, 478 }, 479 { 480 .base = { 481 .domain[nv_clk_src_gpc] = 108000, 482 .voltage = 1, 483 }, 484 }, 485 { 486 .base = { 487 .domain[nv_clk_src_gpc] = 180000, 488 .voltage = 2, 489 }, 490 }, 491 { 492 .base = { 493 .domain[nv_clk_src_gpc] = 252000, 494 .voltage = 3, 495 }, 496 }, 497 { 498 .base = { 499 .domain[nv_clk_src_gpc] = 324000, 500 .voltage = 4, 501 }, 502 }, 503 { 504 .base = { 505 .domain[nv_clk_src_gpc] = 396000, 506 .voltage = 5, 507 }, 508 }, 509 { 510 .base = { 511 .domain[nv_clk_src_gpc] = 468000, 512 .voltage = 6, 513 }, 514 }, 515 { 516 .base = { 517 .domain[nv_clk_src_gpc] = 540000, 518 .voltage = 7, 519 }, 520 }, 521 { 522 .base = { 523 .domain[nv_clk_src_gpc] = 612000, 524 .voltage = 8, 525 }, 526 }, 527 { 528 .base = { 529 .domain[nv_clk_src_gpc] = 648000, 530 .voltage = 9, 531 }, 532 }, 533 { 534 .base = { 535 .domain[nv_clk_src_gpc] = 684000, 536 .voltage = 10, 537 }, 538 }, 539 { 540 .base = { 541 .domain[nv_clk_src_gpc] = 708000, 542 .voltage = 11, 543 }, 544 }, 545 { 546 .base = { 547 .domain[nv_clk_src_gpc] = 756000, 548 .voltage = 12, 549 }, 550 }, 551 { 552 .base = { 553 .domain[nv_clk_src_gpc] = 804000, 554 .voltage = 13, 555 }, 556 }, 557 { 558 .base = { 559 .domain[nv_clk_src_gpc] = 852000, 560 .voltage = 14, 561 }, 562 }, 563 }; 564 565 static int 566 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) 567 { 568 struct gk20a_clk *clk = gk20a_clk(base); 569 struct nvkm_subdev *subdev = &clk->base.subdev; 570 struct nvkm_device *device = subdev->device; 571 572 switch (src) { 573 case nv_clk_src_crystal: 574 return device->crystal; 575 case nv_clk_src_gpc: 576 gk20a_pllg_read_mnp(clk); 577 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; 578 default: 579 nvkm_error(subdev, "invalid clock source %d\n", src); 580 return -EINVAL; 581 } 582 } 583 584 static int 585 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) 586 { 587 struct gk20a_clk *clk = gk20a_clk(base); 588 589 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 590 GK20A_CLK_GPC_MDIV); 591 } 592 593 static int 594 gk20a_clk_prog(struct nvkm_clk *base) 595 { 596 struct gk20a_clk *clk = gk20a_clk(base); 597 598 return gk20a_pllg_program_mnp(clk); 599 } 600 601 static void 602 gk20a_clk_tidy(struct nvkm_clk *base) 603 { 604 } 605 606 static void 607 gk20a_clk_fini(struct nvkm_clk *base) 608 { 609 struct gk20a_clk *clk = gk20a_clk(base); 610 gk20a_pllg_disable(clk); 611 } 612 613 static int 614 gk20a_clk_init(struct nvkm_clk *base) 615 { 616 struct gk20a_clk *clk = gk20a_clk(base); 617 struct nvkm_subdev *subdev = &clk->base.subdev; 618 struct nvkm_device *device = subdev->device; 619 int ret; 620 621 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); 622 623 ret = gk20a_clk_prog(&clk->base); 624 if (ret) { 625 nvkm_error(subdev, "cannot initialize clock\n"); 626 return ret; 627 } 628 629 return 0; 630 } 631 632 static const struct nvkm_clk_func 633 gk20a_clk = { 634 .init = gk20a_clk_init, 635 .fini = gk20a_clk_fini, 636 .read = gk20a_clk_read, 637 .calc = gk20a_clk_calc, 638 .prog = gk20a_clk_prog, 639 .tidy = gk20a_clk_tidy, 640 .pstates = gk20a_pstates, 641 .nr_pstates = ARRAY_SIZE(gk20a_pstates), 642 .domains = { 643 { nv_clk_src_crystal, 0xff }, 644 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 645 { nv_clk_src_max } 646 } 647 }; 648 649 int 650 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) 651 { 652 struct gk20a_clk *clk; 653 int ret, i; 654 655 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) 656 return -ENOMEM; 657 *pclk = &clk->base; 658 659 /* Finish initializing the pstates */ 660 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { 661 INIT_LIST_HEAD(&gk20a_pstates[i].list); 662 gk20a_pstates[i].pstate = i + 1; 663 } 664 665 clk->params = &gk20a_pllg_params; 666 clk->parent_rate = clk_get_rate(device->gpu->clk); 667 668 ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); 669 nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", 670 clk->parent_rate / MHZ); 671 return ret; 672 } 673