1 /* 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c 23 * 24 */ 25 #include "priv.h" 26 #include "gk20a.h" 27 28 #include <core/tegra.h> 29 #include <subdev/timer.h> 30 31 #define KHZ (1000) 32 #define MHZ (KHZ * 1000) 33 34 #define MASK(w) ((1 << w) - 1) 35 36 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 37 #define GPCPLL_CFG_ENABLE BIT(0) 38 #define GPCPLL_CFG_IDDQ BIT(1) 39 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 40 #define GPCPLL_CFG_LOCK BIT(17) 41 42 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 43 #define GPCPLL_COEFF_M_SHIFT 0 44 #define GPCPLL_COEFF_M_WIDTH 8 45 #define GPCPLL_COEFF_N_SHIFT 8 46 #define GPCPLL_COEFF_N_WIDTH 8 47 #define GPCPLL_COEFF_P_SHIFT 16 48 #define GPCPLL_COEFF_P_WIDTH 6 49 50 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 51 #define GPCPLL_CFG2_SETUP2_SHIFT 16 52 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 53 54 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 55 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 56 57 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 58 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 59 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 60 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 61 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 62 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 63 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 64 65 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 66 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 67 68 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 69 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 70 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 71 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 72 #define GPC2CLK_OUT_VCODIV_WIDTH 6 73 #define GPC2CLK_OUT_VCODIV_SHIFT 8 74 #define GPC2CLK_OUT_VCODIV1 0 75 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 76 GPC2CLK_OUT_VCODIV_SHIFT) 77 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 78 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 79 #define GPC2CLK_OUT_BYPDIV31 0x3c 80 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 81 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 82 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 83 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 84 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 85 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 86 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 87 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 88 89 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) 90 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 92 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 93 94 static const u8 _pl_to_div[] = { 95 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ 96 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, 97 }; 98 99 static u32 pl_to_div(u32 pl) 100 { 101 if (pl >= ARRAY_SIZE(_pl_to_div)) 102 return 1; 103 104 return _pl_to_div[pl]; 105 } 106 107 static u32 div_to_pl(u32 div) 108 { 109 u32 pl; 110 111 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { 112 if (_pl_to_div[pl] >= div) 113 return pl; 114 } 115 116 return ARRAY_SIZE(_pl_to_div) - 1; 117 } 118 119 static const struct gk20a_clk_pllg_params gk20a_pllg_params = { 120 .min_vco = 1000000, .max_vco = 2064000, 121 .min_u = 12000, .max_u = 38000, 122 .min_m = 1, .max_m = 255, 123 .min_n = 8, .max_n = 255, 124 .min_pl = 1, .max_pl = 32, 125 }; 126 127 static void 128 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) 129 { 130 struct nvkm_device *device = clk->base.subdev.device; 131 u32 val; 132 133 val = nvkm_rd32(device, GPCPLL_COEFF); 134 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 135 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 136 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 137 } 138 139 static u32 140 gk20a_pllg_calc_rate(struct gk20a_clk *clk) 141 { 142 u32 rate; 143 u32 divider; 144 145 rate = clk->parent_rate * clk->pll.n; 146 divider = clk->pll.m * clk->pl_to_div(clk->pll.pl); 147 148 return rate / divider / 2; 149 } 150 151 static int 152 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) 153 { 154 struct nvkm_subdev *subdev = &clk->base.subdev; 155 u32 target_clk_f, ref_clk_f, target_freq; 156 u32 min_vco_f, max_vco_f; 157 u32 low_pl, high_pl, best_pl; 158 u32 target_vco_f; 159 u32 best_m, best_n; 160 u32 best_delta = ~0; 161 u32 pl; 162 163 target_clk_f = rate * 2 / KHZ; 164 ref_clk_f = clk->parent_rate / KHZ; 165 166 max_vco_f = clk->params->max_vco; 167 min_vco_f = clk->params->min_vco; 168 best_m = clk->params->max_m; 169 best_n = clk->params->min_n; 170 best_pl = clk->params->min_pl; 171 172 target_vco_f = target_clk_f + target_clk_f / 50; 173 if (max_vco_f < target_vco_f) 174 max_vco_f = target_vco_f; 175 176 /* min_pl <= high_pl <= max_pl */ 177 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; 178 high_pl = min(high_pl, clk->params->max_pl); 179 high_pl = max(high_pl, clk->params->min_pl); 180 high_pl = clk->div_to_pl(high_pl); 181 182 /* min_pl <= low_pl <= max_pl */ 183 low_pl = min_vco_f / target_vco_f; 184 low_pl = min(low_pl, clk->params->max_pl); 185 low_pl = max(low_pl, clk->params->min_pl); 186 low_pl = clk->div_to_pl(low_pl); 187 188 nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, 189 clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl)); 190 191 /* Select lowest possible VCO */ 192 for (pl = low_pl; pl <= high_pl; pl++) { 193 u32 m, n, n2; 194 195 target_vco_f = target_clk_f * clk->pl_to_div(pl); 196 197 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { 198 u32 u_f, vco_f; 199 200 u_f = ref_clk_f / m; 201 202 if (u_f < clk->params->min_u) 203 break; 204 if (u_f > clk->params->max_u) 205 continue; 206 207 n = (target_vco_f * m) / ref_clk_f; 208 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; 209 210 if (n > clk->params->max_n) 211 break; 212 213 for (; n <= n2; n++) { 214 if (n < clk->params->min_n) 215 continue; 216 if (n > clk->params->max_n) 217 break; 218 219 vco_f = ref_clk_f * n / m; 220 221 if (vco_f >= min_vco_f && vco_f <= max_vco_f) { 222 u32 delta, lwv; 223 224 lwv = (vco_f + (clk->pl_to_div(pl) / 2)) 225 / clk->pl_to_div(pl); 226 delta = abs(lwv - target_clk_f); 227 228 if (delta < best_delta) { 229 best_delta = delta; 230 best_m = m; 231 best_n = n; 232 best_pl = pl; 233 234 if (best_delta == 0) 235 goto found_match; 236 } 237 } 238 } 239 } 240 } 241 242 found_match: 243 WARN_ON(best_delta == ~0); 244 245 if (best_delta != 0) 246 nvkm_debug(subdev, 247 "no best match for target @ %dMHz on gpc_pll", 248 target_clk_f / KHZ); 249 250 clk->pll.m = best_m; 251 clk->pll.n = best_n; 252 clk->pll.pl = best_pl; 253 254 target_freq = gk20a_pllg_calc_rate(clk); 255 256 nvkm_debug(subdev, 257 "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", 258 target_freq / MHZ, clk->pll.m, clk->pll.n, clk->pll.pl, 259 clk->pl_to_div(clk->pll.pl)); 260 return 0; 261 } 262 263 static int 264 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) 265 { 266 struct nvkm_subdev *subdev = &clk->base.subdev; 267 struct nvkm_device *device = subdev->device; 268 u32 val; 269 int ramp_timeout; 270 271 /* get old coefficients */ 272 val = nvkm_rd32(device, GPCPLL_COEFF); 273 /* do nothing if NDIV is the same */ 274 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) 275 return 0; 276 277 /* setup */ 278 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, 279 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); 280 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, 281 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); 282 283 /* pll slowdown mode */ 284 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 285 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), 286 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); 287 288 /* new ndiv ready for ramp */ 289 val = nvkm_rd32(device, GPCPLL_COEFF); 290 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); 291 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 292 udelay(1); 293 nvkm_wr32(device, GPCPLL_COEFF, val); 294 295 /* dynamic ramp to new ndiv */ 296 val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 297 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; 298 udelay(1); 299 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val); 300 301 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { 302 udelay(1); 303 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); 304 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) 305 break; 306 } 307 308 /* exit slowdown mode */ 309 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, 310 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | 311 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); 312 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); 313 314 if (ramp_timeout <= 0) { 315 nvkm_error(subdev, "gpcpll dynamic ramp timeout\n"); 316 return -ETIMEDOUT; 317 } 318 319 return 0; 320 } 321 322 static void 323 gk20a_pllg_enable(struct gk20a_clk *clk) 324 { 325 struct nvkm_device *device = clk->base.subdev.device; 326 327 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); 328 nvkm_rd32(device, GPCPLL_CFG); 329 } 330 331 static void 332 gk20a_pllg_disable(struct gk20a_clk *clk) 333 { 334 struct nvkm_device *device = clk->base.subdev.device; 335 336 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); 337 nvkm_rd32(device, GPCPLL_CFG); 338 } 339 340 static int 341 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) 342 { 343 struct nvkm_subdev *subdev = &clk->base.subdev; 344 struct nvkm_device *device = subdev->device; 345 u32 val, cfg; 346 struct gk20a_pll old_pll; 347 u32 n_lo; 348 349 /* get old coefficients */ 350 gk20a_pllg_read_mnp(clk, &old_pll); 351 352 /* do NDIV slide if there is no change in M and PL */ 353 cfg = nvkm_rd32(device, GPCPLL_CFG); 354 if (allow_slide && clk->pll.m == old_pll.m && 355 clk->pll.pl == old_pll.pl && (cfg & GPCPLL_CFG_ENABLE)) { 356 return gk20a_pllg_slide(clk, clk->pll.n); 357 } 358 359 /* slide down to NDIV_LO */ 360 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { 361 int ret; 362 363 n_lo = DIV_ROUND_UP(old_pll.m * clk->params->min_vco, 364 clk->parent_rate / KHZ); 365 ret = gk20a_pllg_slide(clk, n_lo); 366 367 if (ret) 368 return ret; 369 } 370 371 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ 372 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, 373 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); 374 375 /* put PLL in bypass before programming it */ 376 val = nvkm_rd32(device, SEL_VCO); 377 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 378 udelay(2); 379 nvkm_wr32(device, SEL_VCO, val); 380 381 /* get out from IDDQ */ 382 val = nvkm_rd32(device, GPCPLL_CFG); 383 if (val & GPCPLL_CFG_IDDQ) { 384 val &= ~GPCPLL_CFG_IDDQ; 385 nvkm_wr32(device, GPCPLL_CFG, val); 386 nvkm_rd32(device, GPCPLL_CFG); 387 udelay(2); 388 } 389 390 gk20a_pllg_disable(clk); 391 392 nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, 393 clk->pll.m, clk->pll.n, clk->pll.pl); 394 395 n_lo = DIV_ROUND_UP(clk->pll.m * clk->params->min_vco, 396 clk->parent_rate / KHZ); 397 val = clk->pll.m << GPCPLL_COEFF_M_SHIFT; 398 val |= (allow_slide ? n_lo : clk->pll.n) << GPCPLL_COEFF_N_SHIFT; 399 val |= clk->pll.pl << GPCPLL_COEFF_P_SHIFT; 400 nvkm_wr32(device, GPCPLL_COEFF, val); 401 402 gk20a_pllg_enable(clk); 403 404 val = nvkm_rd32(device, GPCPLL_CFG); 405 if (val & GPCPLL_CFG_LOCK_DET_OFF) { 406 val &= ~GPCPLL_CFG_LOCK_DET_OFF; 407 nvkm_wr32(device, GPCPLL_CFG, val); 408 } 409 410 if (nvkm_usec(device, 300, 411 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK) 412 break; 413 ) < 0) 414 return -ETIMEDOUT; 415 416 /* switch to VCO mode */ 417 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 418 BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); 419 420 /* restore out divider 1:1 */ 421 val = nvkm_rd32(device, GPC2CLK_OUT); 422 if ((val & GPC2CLK_OUT_VCODIV_MASK) != 423 (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT)) { 424 val &= ~GPC2CLK_OUT_VCODIV_MASK; 425 val |= GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT; 426 udelay(2); 427 nvkm_wr32(device, GPC2CLK_OUT, val); 428 /* Intentional 2nd write to assure linear divider operation */ 429 nvkm_wr32(device, GPC2CLK_OUT, val); 430 nvkm_rd32(device, GPC2CLK_OUT); 431 } 432 433 /* slide up to new NDIV */ 434 return allow_slide ? gk20a_pllg_slide(clk, clk->pll.n) : 0; 435 } 436 437 static int 438 gk20a_pllg_program_mnp(struct gk20a_clk *clk) 439 { 440 int err; 441 442 err = _gk20a_pllg_program_mnp(clk, true); 443 if (err) 444 err = _gk20a_pllg_program_mnp(clk, false); 445 446 return err; 447 } 448 449 static struct nvkm_pstate 450 gk20a_pstates[] = { 451 { 452 .base = { 453 .domain[nv_clk_src_gpc] = 72000, 454 .voltage = 0, 455 }, 456 }, 457 { 458 .base = { 459 .domain[nv_clk_src_gpc] = 108000, 460 .voltage = 1, 461 }, 462 }, 463 { 464 .base = { 465 .domain[nv_clk_src_gpc] = 180000, 466 .voltage = 2, 467 }, 468 }, 469 { 470 .base = { 471 .domain[nv_clk_src_gpc] = 252000, 472 .voltage = 3, 473 }, 474 }, 475 { 476 .base = { 477 .domain[nv_clk_src_gpc] = 324000, 478 .voltage = 4, 479 }, 480 }, 481 { 482 .base = { 483 .domain[nv_clk_src_gpc] = 396000, 484 .voltage = 5, 485 }, 486 }, 487 { 488 .base = { 489 .domain[nv_clk_src_gpc] = 468000, 490 .voltage = 6, 491 }, 492 }, 493 { 494 .base = { 495 .domain[nv_clk_src_gpc] = 540000, 496 .voltage = 7, 497 }, 498 }, 499 { 500 .base = { 501 .domain[nv_clk_src_gpc] = 612000, 502 .voltage = 8, 503 }, 504 }, 505 { 506 .base = { 507 .domain[nv_clk_src_gpc] = 648000, 508 .voltage = 9, 509 }, 510 }, 511 { 512 .base = { 513 .domain[nv_clk_src_gpc] = 684000, 514 .voltage = 10, 515 }, 516 }, 517 { 518 .base = { 519 .domain[nv_clk_src_gpc] = 708000, 520 .voltage = 11, 521 }, 522 }, 523 { 524 .base = { 525 .domain[nv_clk_src_gpc] = 756000, 526 .voltage = 12, 527 }, 528 }, 529 { 530 .base = { 531 .domain[nv_clk_src_gpc] = 804000, 532 .voltage = 13, 533 }, 534 }, 535 { 536 .base = { 537 .domain[nv_clk_src_gpc] = 852000, 538 .voltage = 14, 539 }, 540 }, 541 }; 542 543 int 544 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) 545 { 546 struct gk20a_clk *clk = gk20a_clk(base); 547 struct nvkm_subdev *subdev = &clk->base.subdev; 548 struct nvkm_device *device = subdev->device; 549 550 switch (src) { 551 case nv_clk_src_crystal: 552 return device->crystal; 553 case nv_clk_src_gpc: 554 gk20a_pllg_read_mnp(clk, &clk->pll); 555 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; 556 default: 557 nvkm_error(subdev, "invalid clock source %d\n", src); 558 return -EINVAL; 559 } 560 } 561 562 int 563 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) 564 { 565 struct gk20a_clk *clk = gk20a_clk(base); 566 567 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * 568 GK20A_CLK_GPC_MDIV); 569 } 570 571 int 572 gk20a_clk_prog(struct nvkm_clk *base) 573 { 574 struct gk20a_clk *clk = gk20a_clk(base); 575 576 return gk20a_pllg_program_mnp(clk); 577 } 578 579 void 580 gk20a_clk_tidy(struct nvkm_clk *base) 581 { 582 } 583 584 void 585 gk20a_clk_fini(struct nvkm_clk *base) 586 { 587 struct nvkm_device *device = base->subdev.device; 588 struct gk20a_clk *clk = gk20a_clk(base); 589 u32 val; 590 591 /* slide to VCO min */ 592 val = nvkm_rd32(device, GPCPLL_CFG); 593 if (val & GPCPLL_CFG_ENABLE) { 594 struct gk20a_pll pll; 595 u32 n_lo; 596 597 gk20a_pllg_read_mnp(clk, &pll); 598 n_lo = DIV_ROUND_UP(pll.m * clk->params->min_vco, 599 clk->parent_rate / KHZ); 600 gk20a_pllg_slide(clk, n_lo); 601 } 602 603 /* put PLL in bypass before disabling it */ 604 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); 605 606 gk20a_pllg_disable(clk); 607 } 608 609 static int 610 gk20a_clk_init(struct nvkm_clk *base) 611 { 612 struct gk20a_clk *clk = gk20a_clk(base); 613 struct nvkm_subdev *subdev = &clk->base.subdev; 614 struct nvkm_device *device = subdev->device; 615 int ret; 616 617 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, 618 GPC2CLK_OUT_INIT_VAL); 619 620 /* Start with lowest frequency */ 621 base->func->calc(base, &base->func->pstates[0].base); 622 ret = base->func->prog(&clk->base); 623 if (ret) { 624 nvkm_error(subdev, "cannot initialize clock\n"); 625 return ret; 626 } 627 628 return 0; 629 } 630 631 static const struct nvkm_clk_func 632 gk20a_clk = { 633 .init = gk20a_clk_init, 634 .fini = gk20a_clk_fini, 635 .read = gk20a_clk_read, 636 .calc = gk20a_clk_calc, 637 .prog = gk20a_clk_prog, 638 .tidy = gk20a_clk_tidy, 639 .pstates = gk20a_pstates, 640 .nr_pstates = ARRAY_SIZE(gk20a_pstates), 641 .domains = { 642 { nv_clk_src_crystal, 0xff }, 643 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, 644 { nv_clk_src_max } 645 } 646 }; 647 648 int 649 _gk20a_clk_ctor(struct nvkm_device *device, int index, 650 const struct nvkm_clk_func *func, 651 const struct gk20a_clk_pllg_params *params, 652 struct gk20a_clk *clk) 653 { 654 struct nvkm_device_tegra *tdev = device->func->tegra(device); 655 int ret; 656 int i; 657 658 /* Finish initializing the pstates */ 659 for (i = 0; i < func->nr_pstates; i++) { 660 INIT_LIST_HEAD(&func->pstates[i].list); 661 func->pstates[i].pstate = i + 1; 662 } 663 664 clk->params = params; 665 clk->parent_rate = clk_get_rate(tdev->clk); 666 667 ret = nvkm_clk_ctor(func, device, index, true, &clk->base); 668 if (ret) 669 return ret; 670 671 nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n", 672 clk->parent_rate / KHZ); 673 674 return 0; 675 } 676 677 int 678 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) 679 { 680 struct gk20a_clk *clk; 681 int ret; 682 683 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 684 if (!clk) 685 return -ENOMEM; 686 *pclk = &clk->base; 687 688 ret = _gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params, 689 clk); 690 691 clk->pl_to_div = pl_to_div; 692 clk->div_to_pl = div_to_pl; 693 694 return ret; 695 } 696