1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <subdev/clk.h>
25 #include "pll.h"
26 
27 #include <subdev/timer.h>
28 #include <subdev/bios.h>
29 #include <subdev/bios/pll.h>
30 
31 struct gk104_clk_info {
32 	u32 freq;
33 	u32 ssel;
34 	u32 mdiv;
35 	u32 dsrc;
36 	u32 ddiv;
37 	u32 coef;
38 };
39 
40 struct gk104_clk {
41 	struct nvkm_clk base;
42 	struct gk104_clk_info eng[16];
43 };
44 
45 static u32 read_div(struct gk104_clk *, int, u32, u32);
46 static u32 read_pll(struct gk104_clk *, u32);
47 
48 static u32
49 read_vco(struct gk104_clk *clk, u32 dsrc)
50 {
51 	u32 ssrc = nv_rd32(clk, dsrc);
52 	if (!(ssrc & 0x00000100))
53 		return read_pll(clk, 0x00e800);
54 	return read_pll(clk, 0x00e820);
55 }
56 
57 static u32
58 read_pll(struct gk104_clk *clk, u32 pll)
59 {
60 	u32 ctrl = nv_rd32(clk, pll + 0x00);
61 	u32 coef = nv_rd32(clk, pll + 0x04);
62 	u32 P = (coef & 0x003f0000) >> 16;
63 	u32 N = (coef & 0x0000ff00) >> 8;
64 	u32 M = (coef & 0x000000ff) >> 0;
65 	u32 sclk;
66 	u16 fN = 0xf000;
67 
68 	if (!(ctrl & 0x00000001))
69 		return 0;
70 
71 	switch (pll) {
72 	case 0x00e800:
73 	case 0x00e820:
74 		sclk = nv_device(clk)->crystal;
75 		P = 1;
76 		break;
77 	case 0x132000:
78 		sclk = read_pll(clk, 0x132020);
79 		P = (coef & 0x10000000) ? 2 : 1;
80 		break;
81 	case 0x132020:
82 		sclk = read_div(clk, 0, 0x137320, 0x137330);
83 		fN   = nv_rd32(clk, pll + 0x10) >> 16;
84 		break;
85 	case 0x137000:
86 	case 0x137020:
87 	case 0x137040:
88 	case 0x1370e0:
89 		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
90 		break;
91 	default:
92 		return 0;
93 	}
94 
95 	if (P == 0)
96 		P = 1;
97 
98 	sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
99 	return sclk / (M * P);
100 }
101 
102 static u32
103 read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl)
104 {
105 	u32 ssrc = nv_rd32(clk, dsrc + (doff * 4));
106 	u32 sctl = nv_rd32(clk, dctl + (doff * 4));
107 
108 	switch (ssrc & 0x00000003) {
109 	case 0:
110 		if ((ssrc & 0x00030000) != 0x00030000)
111 			return nv_device(clk)->crystal;
112 		return 108000;
113 	case 2:
114 		return 100000;
115 	case 3:
116 		if (sctl & 0x80000000) {
117 			u32 sclk = read_vco(clk, dsrc + (doff * 4));
118 			u32 sdiv = (sctl & 0x0000003f) + 2;
119 			return (sclk * 2) / sdiv;
120 		}
121 
122 		return read_vco(clk, dsrc + (doff * 4));
123 	default:
124 		return 0;
125 	}
126 }
127 
128 static u32
129 read_mem(struct gk104_clk *clk)
130 {
131 	switch (nv_rd32(clk, 0x1373f4) & 0x0000000f) {
132 	case 1: return read_pll(clk, 0x132020);
133 	case 2: return read_pll(clk, 0x132000);
134 	default:
135 		return 0;
136 	}
137 }
138 
139 static u32
140 read_clk(struct gk104_clk *clk, int idx)
141 {
142 	u32 sctl = nv_rd32(clk, 0x137250 + (idx * 4));
143 	u32 sclk, sdiv;
144 
145 	if (idx < 7) {
146 		u32 ssel = nv_rd32(clk, 0x137100);
147 		if (ssel & (1 << idx)) {
148 			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
149 			sdiv = 1;
150 		} else {
151 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
152 			sdiv = 0;
153 		}
154 	} else {
155 		u32 ssrc = nv_rd32(clk, 0x137160 + (idx * 0x04));
156 		if ((ssrc & 0x00000003) == 0x00000003) {
157 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
158 			if (ssrc & 0x00000100) {
159 				if (ssrc & 0x40000000)
160 					sclk = read_pll(clk, 0x1370e0);
161 				sdiv = 1;
162 			} else {
163 				sdiv = 0;
164 			}
165 		} else {
166 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
167 			sdiv = 0;
168 		}
169 	}
170 
171 	if (sctl & 0x80000000) {
172 		if (sdiv)
173 			sdiv = ((sctl & 0x00003f00) >> 8) + 2;
174 		else
175 			sdiv = ((sctl & 0x0000003f) >> 0) + 2;
176 		return (sclk * 2) / sdiv;
177 	}
178 
179 	return sclk;
180 }
181 
182 static int
183 gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
184 {
185 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
186 	struct nvkm_device *device = nv_device(clk);
187 
188 	switch (src) {
189 	case nv_clk_src_crystal:
190 		return device->crystal;
191 	case nv_clk_src_href:
192 		return 100000;
193 	case nv_clk_src_mem:
194 		return read_mem(clk);
195 	case nv_clk_src_gpc:
196 		return read_clk(clk, 0x00);
197 	case nv_clk_src_rop:
198 		return read_clk(clk, 0x01);
199 	case nv_clk_src_hubk07:
200 		return read_clk(clk, 0x02);
201 	case nv_clk_src_hubk06:
202 		return read_clk(clk, 0x07);
203 	case nv_clk_src_hubk01:
204 		return read_clk(clk, 0x08);
205 	case nv_clk_src_daemon:
206 		return read_clk(clk, 0x0c);
207 	case nv_clk_src_vdec:
208 		return read_clk(clk, 0x0e);
209 	default:
210 		nv_error(clk, "invalid clock source %d\n", src);
211 		return -EINVAL;
212 	}
213 }
214 
215 static u32
216 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
217 {
218 	u32 div = min((ref * 2) / freq, (u32)65);
219 	if (div < 2)
220 		div = 2;
221 
222 	*ddiv = div - 2;
223 	return (ref * 2) / div;
224 }
225 
226 static u32
227 calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
228 {
229 	u32 sclk;
230 
231 	/* use one of the fixed frequencies if possible */
232 	*ddiv = 0x00000000;
233 	switch (freq) {
234 	case  27000:
235 	case 108000:
236 		*dsrc = 0x00000000;
237 		if (freq == 108000)
238 			*dsrc |= 0x00030000;
239 		return freq;
240 	case 100000:
241 		*dsrc = 0x00000002;
242 		return freq;
243 	default:
244 		*dsrc = 0x00000003;
245 		break;
246 	}
247 
248 	/* otherwise, calculate the closest divider */
249 	sclk = read_vco(clk, 0x137160 + (idx * 4));
250 	if (idx < 7)
251 		sclk = calc_div(clk, idx, sclk, freq, ddiv);
252 	return sclk;
253 }
254 
255 static u32
256 calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)
257 {
258 	struct nvkm_bios *bios = nvkm_bios(clk);
259 	struct nvbios_pll limits;
260 	int N, M, P, ret;
261 
262 	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
263 	if (ret)
264 		return 0;
265 
266 	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
267 	if (!limits.refclk)
268 		return 0;
269 
270 	ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
271 	if (ret <= 0)
272 		return 0;
273 
274 	*coef = (P << 16) | (N << 8) | M;
275 	return ret;
276 }
277 
278 static int
279 calc_clk(struct gk104_clk *clk,
280 	 struct nvkm_cstate *cstate, int idx, int dom)
281 {
282 	struct gk104_clk_info *info = &clk->eng[idx];
283 	u32 freq = cstate->domain[dom];
284 	u32 src0, div0, div1D, div1P = 0;
285 	u32 clk0, clk1 = 0;
286 
287 	/* invalid clock domain */
288 	if (!freq)
289 		return 0;
290 
291 	/* first possible path, using only dividers */
292 	clk0 = calc_src(clk, idx, freq, &src0, &div0);
293 	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
294 
295 	/* see if we can get any closer using PLLs */
296 	if (clk0 != freq && (0x0000ff87 & (1 << idx))) {
297 		if (idx <= 7)
298 			clk1 = calc_pll(clk, idx, freq, &info->coef);
299 		else
300 			clk1 = cstate->domain[nv_clk_src_hubk06];
301 		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
302 	}
303 
304 	/* select the method which gets closest to target freq */
305 	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
306 		info->dsrc = src0;
307 		if (div0) {
308 			info->ddiv |= 0x80000000;
309 			info->ddiv |= div0;
310 		}
311 		if (div1D) {
312 			info->mdiv |= 0x80000000;
313 			info->mdiv |= div1D;
314 		}
315 		info->ssel = 0;
316 		info->freq = clk0;
317 	} else {
318 		if (div1P) {
319 			info->mdiv |= 0x80000000;
320 			info->mdiv |= div1P << 8;
321 		}
322 		info->ssel = (1 << idx);
323 		info->dsrc = 0x40000100;
324 		info->freq = clk1;
325 	}
326 
327 	return 0;
328 }
329 
330 static int
331 gk104_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
332 {
333 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
334 	int ret;
335 
336 	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
337 	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
338 	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
339 	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
340 	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
341 	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
342 	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
343 		return ret;
344 
345 	return 0;
346 }
347 
348 static void
349 gk104_clk_prog_0(struct gk104_clk *clk, int idx)
350 {
351 	struct gk104_clk_info *info = &clk->eng[idx];
352 	if (!info->ssel) {
353 		nv_mask(clk, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);
354 		nv_wr32(clk, 0x137160 + (idx * 0x04), info->dsrc);
355 	}
356 }
357 
358 static void
359 gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)
360 {
361 	nv_mask(clk, 0x137100, (1 << idx), 0x00000000);
362 	nv_wait(clk, 0x137100, (1 << idx), 0x00000000);
363 }
364 
365 static void
366 gk104_clk_prog_1_1(struct gk104_clk *clk, int idx)
367 {
368 	nv_mask(clk, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000);
369 }
370 
371 static void
372 gk104_clk_prog_2(struct gk104_clk *clk, int idx)
373 {
374 	struct gk104_clk_info *info = &clk->eng[idx];
375 	const u32 addr = 0x137000 + (idx * 0x20);
376 	nv_mask(clk, addr + 0x00, 0x00000004, 0x00000000);
377 	nv_mask(clk, addr + 0x00, 0x00000001, 0x00000000);
378 	if (info->coef) {
379 		nv_wr32(clk, addr + 0x04, info->coef);
380 		nv_mask(clk, addr + 0x00, 0x00000001, 0x00000001);
381 		nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000);
382 		nv_mask(clk, addr + 0x00, 0x00020004, 0x00000004);
383 	}
384 }
385 
386 static void
387 gk104_clk_prog_3(struct gk104_clk *clk, int idx)
388 {
389 	struct gk104_clk_info *info = &clk->eng[idx];
390 	if (info->ssel)
391 		nv_mask(clk, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);
392 	else
393 		nv_mask(clk, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);
394 }
395 
396 static void
397 gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)
398 {
399 	struct gk104_clk_info *info = &clk->eng[idx];
400 	if (info->ssel) {
401 		nv_mask(clk, 0x137100, (1 << idx), info->ssel);
402 		nv_wait(clk, 0x137100, (1 << idx), info->ssel);
403 	}
404 }
405 
406 static void
407 gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)
408 {
409 	struct gk104_clk_info *info = &clk->eng[idx];
410 	if (info->ssel) {
411 		nv_mask(clk, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000);
412 		nv_mask(clk, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100);
413 	}
414 }
415 
416 static int
417 gk104_clk_prog(struct nvkm_clk *obj)
418 {
419 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
420 	struct {
421 		u32 mask;
422 		void (*exec)(struct gk104_clk *, int);
423 	} stage[] = {
424 		{ 0x007f, gk104_clk_prog_0   }, /* div programming */
425 		{ 0x007f, gk104_clk_prog_1_0 }, /* select div mode */
426 		{ 0xff80, gk104_clk_prog_1_1 },
427 		{ 0x00ff, gk104_clk_prog_2   }, /* (maybe) program pll */
428 		{ 0xff80, gk104_clk_prog_3   }, /* final divider */
429 		{ 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */
430 		{ 0xff80, gk104_clk_prog_4_1 },
431 	};
432 	int i, j;
433 
434 	for (i = 0; i < ARRAY_SIZE(stage); i++) {
435 		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
436 			if (!(stage[i].mask & (1 << j)))
437 				continue;
438 			if (!clk->eng[j].freq)
439 				continue;
440 			stage[i].exec(clk, j);
441 		}
442 	}
443 
444 	return 0;
445 }
446 
447 static void
448 gk104_clk_tidy(struct nvkm_clk *obj)
449 {
450 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
451 	memset(clk->eng, 0x00, sizeof(clk->eng));
452 }
453 
454 static struct nvkm_domain
455 gk104_domain[] = {
456 	{ nv_clk_src_crystal, 0xff },
457 	{ nv_clk_src_href   , 0xff },
458 	{ nv_clk_src_gpc    , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
459 	{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
460 	{ nv_clk_src_rop    , 0x02, NVKM_CLK_DOM_FLAG_CORE },
461 	{ nv_clk_src_mem    , 0x03, 0, "memory", 500 },
462 	{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
463 	{ nv_clk_src_hubk01 , 0x05 },
464 	{ nv_clk_src_vdec   , 0x06 },
465 	{ nv_clk_src_daemon , 0x07 },
466 	{ nv_clk_src_max }
467 };
468 
469 static int
470 gk104_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
471 	       struct nvkm_oclass *oclass, void *data, u32 size,
472 	       struct nvkm_object **pobject)
473 {
474 	struct gk104_clk *clk;
475 	int ret;
476 
477 	ret = nvkm_clk_create(parent, engine, oclass, gk104_domain,
478 			      NULL, 0, true, &clk);
479 	*pobject = nv_object(clk);
480 	if (ret)
481 		return ret;
482 
483 	clk->base.read = gk104_clk_read;
484 	clk->base.calc = gk104_clk_calc;
485 	clk->base.prog = gk104_clk_prog;
486 	clk->base.tidy = gk104_clk_tidy;
487 	return 0;
488 }
489 
490 struct nvkm_oclass
491 gk104_clk_oclass = {
492 	.handle = NV_SUBDEV(CLK, 0xe0),
493 	.ofuncs = &(struct nvkm_ofuncs) {
494 		.ctor = gk104_clk_ctor,
495 		.dtor = _nvkm_clk_dtor,
496 		.init = _nvkm_clk_init,
497 		.fini = _nvkm_clk_fini,
498 	},
499 };
500